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Mon, 03 Aug 2026 11:07:58 -0700 (PDT) From: =?utf-8?q?Juan_Manuel_L=C3=B3pez_Carrillo?= To: mturquette@baylibre.com, sboyd@kernel.org, wens@kernel.org, jernej.skrabec@gmail.com, samuel@sholland.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: andre.przywara@arm.com, bmasney@redhat.com, linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Juan_Ma?= =?utf-8?q?nuel_L=C3=B3pez_Carrillo?= Subject: [PATCH v2 0/3] clk: sunxi-ng: fix the A523/T527 GPU clock model, enable GPU DVFS Date: Mon, 3 Aug 2026 20:07:52 +0200 Message-ID: <20260803180755.288793-1-juanmanuellopezcarrillo@gmail.com> X-Mailer: git-send-email 2.47.3 Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Hi, v2 of the A523/T527 GPU clock series. v1 is here: https://lore.kernel.org/linux-sunxi/20260719211319.982285-1-juanmanuellopezcarrillo@gmail.com/ The GPU mod clock is not a linear M+1 divider: the M factor masks M pulses out of every 16 parent cycles, so rate = parent * (16 - M) / 16 (T527 user manual v0.92, section 2.7.6.58). Modelling it with ccu_div programs a faster clock than requested for every M > 0, which is what mainline does today. Measured on an Orange Pi 4A with the Mali cycle counter, the OPPs labelled 150/200/300/400 MHz were really running at 487/648/560/750 MHz, and thermal throttling to "400" actually raised the clock to 750. With this series the same measurement gives 149/199/300/399/597 MHz. Changes since v1: - Dropped the pll-gpu reparenting notifier (patch 3/4 in v1). I wrote it when the plan for the higher speed-bin points was to retune pll-gpu at runtime: it parked the GPU on the fixed pll-periph0-600M output while the PLL was being reprogrammed, so the GPU would never see it relocking. That plan has been superseded. The maskdiv in patch 1 can divide any parent down, and the speed-bin work on top of it (first follow-up below) pins pll-gpu once via assigned-clock-rates and reaches every operating point by moving only the mux and the divider. The PLL therefore never changes rate at runtime, the notifier can never fire, and gpu_clk deliberately does not set CLK_SET_RATE_PARENT either. That is how the 696 MHz point runs here today, with no notifier. It would only be needed again if a future series reprograms the PLL instead of pinning it. Chen-Yu, you asked for this notifier in the v1 discussion: tell me if you would rather have it now anyway and I will put it back. - maskdiv: honour CCU_FEATURE_UPDATE_BIT and CCU_FEATURE_KEY_FIELD in set_rate, clamp determine_rate() to the request bounds, and document that CLK_SET_RATE_PARENT is not supported. These were folded into patch 1 so the new type is correct as introduced, rather than introduced and then fixed. They also address the two issues the CI bot reported on v1. - The GPU OPP table moved from the board .dts to sun55i-a523.dtsi, and the operating-points-v2 reference now lives in the SoC's GPU node (Chen-Yu). - opp-microvolt now uses the form, <900000 900000 920000>: 900 mV is what the BSP universal table specifies, and the 920 mV ceiling covers boards whose GPU rail is a fixed 920 mV supply (Chen-Yu). - Rebased from v7.2-rc4 onto sunxi/for-next. Tested on an Orange Pi 4A (T527, 2 GB): rates verified with the Mali cycle counter under load, thermal-emulation throttling exercised, no job faults. Two follow-ups are already working on the board and I can send them next. Tell me which one is more useful to you first, or if you would rather they waited: - GPU operating points above 600 MHz, gated on the SoC speed bin read from the SID. This chip is bin 1, where the vendor table sanctions 696 MHz at the same 900 mV; it has been running games here without job faults. - The A523/T527 CPU clock unit (ccu-sun55i-a523-cpu.c) and the generic sunxi-ng fix it depends on, which is what cpufreq needs on this SoC. The DSU/L3 clock lives in the same unit. Juan Manuel López Carrillo (3): clk: sunxi-ng: add cycle-masking divider (maskdiv) clock type clk: sunxi-ng: sun55i-a523: GPU clock divider is fractional, not linear arm64: dts: allwinner: a523: add GPU OPP table .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 30 +++ drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 32 ++- drivers/clk/sunxi-ng/ccu_common.h | 3 + drivers/clk/sunxi-ng/ccu_maskdiv.c | 213 ++++++++++++++++++ drivers/clk/sunxi-ng/ccu_maskdiv.h | 76 +++++++ drivers/clk/sunxi-ng/ccu_mux.c | 2 - 7 files changed, 349 insertions(+), 8 deletions(-) create mode 100644 drivers/clk/sunxi-ng/ccu_maskdiv.c create mode 100644 drivers/clk/sunxi-ng/ccu_maskdiv.h base-commit: 859c0e1925332d413ca8f9159c8ca5d04eea32a2