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Sun, 6 Sep 2026 00:07:06 -0700 (PDT) From: Junhui Liu Subject: [PATCH 0/4] clk: sunxi-ng: a523: Fix single-divider clocks Date: Sun, 06 Sep 2026 15:06:37 +0800 Message-Id: <20260906-sunxi-clk-no-p-v1-0-cbde21c9fe69@pigmoral.tech> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAAAAAAAC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzMDSwMz3eLSvIpM3eScbN28fN0C3ZRUY1Nzk1RTCyPjRCWgpoKi1LTMCrC B0bEQfnFpUlZqcgnIFKXaWgAkAhN5cgAAAA== X-Change-ID: 20260906-sunxi-clk-no-p-de3574e5823a To: Stephen Boyd , Brian Masney , Jerome Brunet , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Junhui Liu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2495; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=iKacs7dw+/b845xjJsLw2XuiPPAnkyl59zLiFFJQOGk=; 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FORGED_RECIPIENTS_MAILLIST(0.00)[]; DKIM_TRACE(0.00)[pigmoral.tech:+]; R_SPF_ALLOW(0.00)[+ip4:172.234.253.10]; FORGED_SENDER_MAILLIST(0.00)[]; MIME_TRACE(0.00)[0:+]; MID_RHS_MATCH_FROM(0.00)[]; FROM_NEQ_ENVFROM(0.00)[junhui.liu@pigmoral.tech,linux-sunxi@lists.linux.dev]; RCVD_TLS_LAST(0.00)[]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; TAGGED_FROM(0.00)[bounces-25630-noreply=patchwork.local]; TO_DN_SOME(0.00)[] X-Rspamd-Queue-Id: D9B341C075F X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Sashiko pointed out two issues in my series adding clock driver support for the Allwinner A733 SoC [1][2]. First, ccu_mp_set_rate() generates an invalid mask when an MP clock is defined with a zero-width P divider, clearing unrelated register fields. Second, ccu_mp_set_rate() does not handle CCU_FEATURE_UPDATE_BIT, so divider changes are not latched by the hardware. The affected A733 clocks were modeled after the existing A523 MBUS, IOMMU, and DRAM clocks, which have the same issues. According to the hardware description, these clocks only contain an M divider and should be modeled as M-only clocks. The A523 high-speed and PRCM timer clocks have the opposite problem. They only contain a P divider but are modeled as MP clocks with a zero-width M divider. Add a feature-capable variant of the M-only clock macro and migrate the affected A523 clocks to it. Convert the timer clocks to the existing P-only clock type. The affected A733 clocks will use the new M-only macro in the next revision of the A733 CCU series. Tested on Radxa Cubie A5E with CLOCK_ALLOW_WRITE_DEBUGFS enabled: # cat /sys/kernel/debug/clk/mbus/clk_rate 600000000 # devmem 0x02001540 32 0xC0000003 # echo 300000000 > /sys/kernel/debug/clk/mbus/clk_rate Results without this series: # cat /sys/kernel/debug/clk/mbus/clk_rate 600000000 # devmem 0x02001540 32 0x00000003 Results with this series: # cat /sys/kernel/debug/clk/mbus/clk_rate 300000000 # devmem 0x02001540 32 0xC0000007 Link: https://lore.kernel.org/r/20260905164854.57BEF1F00A3A@smtp.kernel.org [1] Link: https://lore.kernel.org/r/20260905164855.57E751F00A3D@smtp.kernel.org [2] Signed-off-by: Junhui Liu --- Junhui Liu (4): clk: sunxi-ng: div: Add feature support to M clock macro clk: sunxi-ng: sun55i-a523-ccu: Use M-only clocks for MBUS, IOMMU and DRAM clk: sunxi-ng: sun55i-a523-ccu: Use P-only clocks for high-speed timers clk: sunxi-ng: sun55i-a523-r-ccu: Use P-only clocks for timers drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c | 37 ++++----- drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 128 ++++++++++++++----------------- drivers/clk/sunxi-ng/ccu_div.h | 18 ++++- 3 files changed, 88 insertions(+), 95 deletions(-) --- base-commit: 4d7d9486c04d917265f64c55bd23b2cc4fe7749c change-id: 20260906-sunxi-clk-no-p-de3574e5823a Best regards, -- Junhui Liu