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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-850f8458d8esm565721a34.1.2026.10.23.14.19.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Oct 2026 14:19:30 -0700 (PDT) From: James Hilliard Subject: [PATCH v2 0/3] serial: 8250_dw: describe the Allwinner H616 UART configuration Date: Fri, 23 Oct 2026 15:19:26 -0600 Message-Id: <20261023-submit-h616-uart-fifo-v1-v2-0-af0593504635@gmail.com> X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAAAAAAAC/3WSzW4bMQyEXyXYc7egRImUcup7FDlI/Im3aOLWd oIWQd69tIMetkCBvRCrb4Yz0ttyttNm5+X+7m052et23o7PMeRPd4scxvOjrZvGvGTIlCDn9fw yn7bLeqBE68s4XVbf/Li+plXqcFG3KhOWwH+czLdfN+mvDx9zsN9MLle964nDdr4cT79v3q/pe u6vDf7fJj5YrQycw7LN0b48Po3t+2c5Pi0P7x8+J/v5EkkuH+bLHGdb438IRjIYiEKTZBpbaVD VY1BqLVFHLgXHSKXdIoyLHKKA+zsl7K0UpsJjgM4JUGc10lAanYxKNh+N9pQTS/KmTbtBKiJUw bNjyDSiXBAEJ/PcU63m3LipFxMtHlYsrhjFJKzdyGZtI5nvqa7uNQH3KVUxlsnduPXBgg6lNWn JKzPuKRtpdPfJXQujskYJKc3J4eWS0yRUYfxnQyuTmBxqyb2SIoQ5qCZqyhFMoBp2qmNPVcjKZ rVL5EfrOZo0FshdZCIbUayOXfdUSgDxINg7QEi7DvbEUT+kuEkoKTP7mLKnUKRJmg08RZ0aN5R nZRNW6MM7VitSEo54Mu9/AE2U8xkEAwAA X-Change-ID: 20261022-submit-h616-uart-fifo-v1-c5afcdfe5cb0 To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4?= =?utf-8?q?rvinen?= , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, James Hilliard X-Mailer: b4 0.15.2 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-1.19 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.234.253.10:from]; SUSPICIOUS_RECIPS(1.50)[]; DMARC_POLICY_SOFTFAIL(1.00)[gmail.com : SPF not aligned (relaxed), No valid DKIM,none]; MAILLIST(-0.18)[generic]; MIME_GOOD(-0.10)[text/plain]; BAD_REP_POLICIES(0.10)[]; HAS_LIST_UNSUB(-0.01)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[sea.lore.kernel.org:helo,sea.lore.kernel.org:rdns]; FORGED_SENDER_MAILLIST(0.00)[]; RCVD_COUNT_FIVE(0.00)[6]; RCPT_COUNT_TWELVE(0.00)[16]; FROM_HAS_DN(0.00)[]; FREEMAIL_CC(0.00)[vger.kernel.org,lists.infradead.org,lists.linux.dev,gmail.com]; TAGGED_RCPT(0.00)[dt]; FROM_NEQ_ENVFROM(0.00)[jameshilliard1@gmail.com,linux-sunxi@lists.linux.dev]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; MID_RHS_MATCH_FROM(0.00)[]; TO_DN_SOME(0.00)[]; FREEMAIL_FROM(0.00)[gmail.com]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[174.29.1.49:received,100.77.114.92:received,209.85.210.51:received]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.234.253.10:from]; TAGGED_FROM(0.00)[bounces-26831-noreply=patchwork.local]; R_SPF_ALLOW(0.00)[+ip4:172.234.253.10]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc20261015:i=2]; FREEMAIL_TO(0.00)[linuxfoundation.org,kernel.org,linux.intel.com,gmail.com,sholland.org]; RCVD_TLS_LAST(0.00)[]; MIME_TRACE(0.00)[0:+]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 1A54A1C0982 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= H616 has 256-byte UART FIFOs, but lacks the DesignWare component parameter register used to discover their capacity. Its debug-divisor and RS485 registers also overlap offsets used to probe optional DesignWare features. Add an H616 compatible and configure the existing 16550A port type with the documented FIFO capacity, receive thresholds and automatic flow control. Preserve the BUSY-safe integer divisor path and keep the UART gate enabled during termios changes. Attach the existing 8250 DMA path using single-byte peripheral bursts, with channel acquisition and PIO fallback handled by the normal startup path. The patches add the binding, driver configuration and SoC DTS compatible in that order. Based on next-20261023, which includes the TTY changes and A733 DMA register-layout updates, with the posted IRQ-safe locking fix [0], pause-bit fix [1], virt-dma synchronization helper [2], and sun6i channel lifetime v2 series [3] applied first. The sun6i pause bookkeeping lets an 8250 RX flush account the paused transfer and release its running state, including when it is flushed before the allocator starts it. Apply [3] with git am -3 on this base to combine its tx_status() changes with the intervening NULL-descriptor cleanup. [0] https://lore.kernel.org/r/20260926171049.841335-1-tien.nguyenminh@embeddedlinux.blog [1] https://lore.kernel.org/r/20261021-submit-sun6i-dma-pause-bit-v1-v1-1-38d286b69dab@gmail.com [2] https://lore.kernel.org/r/20261022-submit-mtk-uart-dma-synchronize-v1-v2-1-fdaef0e2edd6@gmail.com [3] https://lore.kernel.org/r/20261023-submit-sun6i-dma-lifetime-next-v1-v2-0-c9e07cc44bf8@gmail.com Assisted-by: Codex:gpt-6-astra Signed-off-by: James Hilliard --- Changes in v2: - Keep PORT_16550A and set the FIFO size, transmit load and capabilities during setup, following Andy's review. - Select H616 setup through the matched platform-data pointer and remove the type and DMA burst-size platform-data members. - Use get_rxtrig/set_rxtrig for the 1/64/128/254-byte receive thresholds, with port locking and runtime PM around register updates. Keep the standard half-full FCR default, selecting 128 bytes on H616. - Advertise UART_CAP_AFE so CRTSCTS enables hardware automatic flow control. - Rebase onto next-20261023 and declare the posted sun6i pause/lifetime fixes and their prerequisites for DMA enablement. - Link to v1: https://lore.kernel.org/r/20261023-submit-h616-uart-fifo-v1-v1-0-e4a3bae2eba8@gmail.com --- James Hilliard (3): dt-bindings: serial: snps-dw-apb-uart: add Allwinner H616 serial: 8250_dw: configure the Allwinner H616 UART arm64: dts: allwinner: h616: identify the UART integration .../bindings/serial/snps-dw-apb-uart.yaml | 1 + arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 12 +-- drivers/tty/serial/8250/8250_dw.c | 87 ++++++++++++++++++++-- 3 files changed, 86 insertions(+), 14 deletions(-) --- base-commit: 20a33c6b6cbe7e4805dfb6cd68816937443aa148 change-id: 20261022-submit-h616-uart-fifo-v1-c5afcdfe5cb0 prerequisite-patch-id: d6398447647aa0dbb005b5e6dc6ba96e642efa86 prerequisite-patch-id: f67c1f8d8d9e014cc650f2f37648662430c3b77b prerequisite-patch-id: 8522878df4ecd4fb007cfd32611359e6eb58a1ef prerequisite-patch-id: 9dff51079bc5d3efa29e789a7c3f0488c81f5773 prerequisite-patch-id: ea1a9ffb79d473d7d81611bb7113fc21b63dc73b prerequisite-patch-id: e4b676f0542956d309df0dd168d7866c05e3965a prerequisite-patch-id: 502d7ee59c7643e92aa0e7c029ccb37e66bc539d prerequisite-patch-id: 11000237f90066cfda7f17005010a3041277fabc prerequisite-patch-id: 3cc8c1b80f1852d96e2b57ec7d09af935e4c413a Best regards, -- James Hilliard