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Wed, 07 May 2025 13:22:45 -0700 (PDT) Received: from localhost.localdomain ([2600:1700:fb0:1bcf:e46c:46ba:cecd:a52c]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-732109df2dcsm725945a34.9.2025.05.07.13.22.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 May 2025 13:22:45 -0700 (PDT) From: Chris Morgan To: linux-sunxi@lists.linux.dev Cc: devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, ryan@testtoast.com, macromorgan@hotmail.com, p.zabel@pengutronix.de, tzimmermann@suse.de, maarten.lankhorst@linux.intel.com, simona@ffwll.ch, airlied@gmail.com, mripard@kernel.org, samuel@sholland.org, jernej.skrabec@gmail.com, wens@csie.org, conor+dt@kernel.org, krzk+dt@kernel.org, robh@kernel.org Subject: [PATCH V9 24/24] arm64: dts: allwinner: rg35xx: Enable LCD output Date: Wed, 7 May 2025 15:19:43 -0500 Message-ID: <20250507201943.330111-25-macroalpha82@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250507201943.330111-1-macroalpha82@gmail.com> References: <20250507201943.330111-1-macroalpha82@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O From: Chris Morgan The RG35XX has a 640x480 RGB/SPI LCD panel, supported by the SoC display pipeline and an NV3052C controller. The H616 SOC's GPIO bank D contains the muxed display pins for RGB and LVDS output support. Enable the display engine and LCD timing controller, configure the panel, and add a fixed 3.3v GPIO-controlled regulator for the panel, and a VCC supply for the display pins as per the other GPIO banks. Signed-off-by: Ryan Walklin Signed-off-by: Chris Morgan --- .../sun50i-h700-anbernic-rg35xx-2024.dts | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts index 95f2ae04bd95..260c2d55a86e 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts @@ -187,6 +187,49 @@ reg_vcc5v: regulator-vcc5v { /* USB-C power input */ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + reg_lcd: regulator-gpio-lcd-vdd { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vdd-lcd"; + gpio = <&pio 8 15 GPIO_ACTIVE_HIGH>; // PI15 + enable-active-high; + }; + + spi_lcd: spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&pio 8 9 GPIO_ACTIVE_HIGH>; // PI9 + mosi-gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>; // PI10 + cs-gpios = <&pio 8 8 GPIO_ACTIVE_HIGH>; // PI8 + num-chipselects = <1>; + + panel: panel@0 { + compatible = "anbernic,rg35xx-plus-panel"; + + reg = <0>; + + spi-max-frequency = <3125000>; + spi-3wire; + + reset-gpios = <&pio 8 14 GPIO_ACTIVE_LOW>; // PI14 + + backlight = <&backlight>; + power-supply = <®_lcd>; + + pinctrl-0 = <&lcd0_rgb888_pins>; + pinctrl-names = "default"; + + port { + panel_in_rgb: endpoint { + remote-endpoint = <&tcon_lcd0_out_lcd>; + }; + }; + }; + }; }; &codec { @@ -199,6 +242,10 @@ &cpu0 { cpu-supply = <®_dcdc1>; }; +&de { + status = "okay"; +}; + &ehci0 { status = "okay"; }; @@ -218,6 +265,7 @@ &ohci0 { &pio { vcc-pa-supply = <®_cldo3>; vcc-pc-supply = <®_cldo3>; + vcc-pd-supply = <®_cldo3>; vcc-pe-supply = <®_cldo3>; vcc-pf-supply = <®_cldo3>; vcc-pg-supply = <®_aldo4>; @@ -377,3 +425,14 @@ &usbotg { &usbphy { status = "okay"; }; + +&tcon_lcd0 { + status = "okay"; +}; + +&tcon_lcd0_out { + tcon_lcd0_out_lcd: endpoint@1 { + reg = <1>; + remote-endpoint = <&panel_in_rgb>; + }; +};