From patchwork Fri Jul 4 15:46:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Kocialkowski X-Patchwork-Id: 1463 Received: from leonov.paulk.fr (leonov.paulk.fr [185.233.101.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 416CA32718D for ; Fri, 4 Jul 2025 15:58:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.233.101.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751644739; cv=none; b=stwU3QblW9nubD0r7LZb9huTZeOgHGuhtfW981fbrunKZUGNE9TyZDr/rad1qzxBxCFKsFrTldE8DImkw2u0k7rQWuDC3y+uMom7DE/Pm3ji/zGkclzB4sc3ETkZzV0vRyLC7c8qOH+sj7Z3LU/n/BmJ3fjqRc46eUgqfBa3+CU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751644739; c=relaxed/simple; bh=Q78f1QuSFzz5rj+1pXgpOayq9ghe6QXSykrzUaECxnA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eDj647jIAOM/qsZ9OcI+zYIzTjUJhgAde8QZz0g+QEMpzwGWvgpl5RNfx8dZfK480AyV5ZKOiknApiMSPizF+pT/x/LXuvbJaXpCgCB1AZn18Uwlve6iSn5LPiEKgxN7EINRpFe3v0kupb+xoarb/1T0/RrfPTC4C7/dzcbKTj4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io; spf=pass smtp.mailfrom=sys-base.io; arc=none smtp.client-ip=185.233.101.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sys-base.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sys-base.io Received: from laika.paulk.fr (12.234.24.109.rev.sfr.net [109.24.234.12]) by leonov.paulk.fr (Postfix) with ESMTPS id 75C3C1F0004F for ; Fri, 4 Jul 2025 15:58:54 +0000 (UTC) Received: by laika.paulk.fr (Postfix, from userid 65534) id 520B5ACA6B4; Fri, 4 Jul 2025 15:51:42 +0000 (UTC) X-Spam-Level: * Received: from localhost.localdomain (unknown [192.168.1.64]) by laika.paulk.fr (Postfix) with ESMTP id C5661ACA659; Fri, 4 Jul 2025 15:46:40 +0000 (UTC) From: Paul Kocialkowski To: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: Yong Deng , Paul Kocialkowski , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Michael Turquette , Stephen Boyd , Maxime Ripard , Paul Kocialkowski Subject: [PATCH v8 7/9] ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node Date: Fri, 4 Jul 2025 17:46:24 +0200 Message-ID: <20250704154628.3468793-8-paulk@sys-base.io> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250704154628.3468793-1-paulk@sys-base.io> References: <20250704154628.3468793-1-paulk@sys-base.io> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O From: Paul Kocialkowski MIPI CSI-2 is supported on the A83T with a dedicated controller that covers both the protocol and D-PHY. It is connected to the only CSI receiver with a fwnode graph link. Note that the CSI receiver supports both this MIPI CSI-2 source and a parallel source. An empty port with a label for the MIPI CSI-2 sensor input is also defined for convenience. Signed-off-by: Paul Kocialkowski Reviewed-by: Jernej Skrabec --- arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 43 +++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi index 6f88d8764e6a..cc107c6030de 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi @@ -1062,6 +1062,49 @@ csi: camera@1cb0000 { clock-names = "bus", "mod", "ram"; resets = <&ccu RST_BUS_CSI>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + csi_in_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_out_csi>; + }; + }; + }; + }; + + mipi_csi2: csi@1cb1000 { + compatible = "allwinner,sun8i-a83t-mipi-csi2"; + reg = <0x01cb1000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI_SCLK>, + <&ccu CLK_MIPI_CSI>, + <&ccu CLK_CSI_MISC>; + clock-names = "bus", "mod", "mipi", "misc"; + resets = <&ccu RST_BUS_CSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_in: port@0 { + reg = <0>; + }; + + mipi_csi2_out: port@1 { + reg = <1>; + + mipi_csi2_out_csi: endpoint { + remote-endpoint = <&csi_in_mipi_csi2>; + }; + }; + }; }; hdmi: hdmi@1ee0000 {