From patchwork Thu Aug 21 00:42:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1197 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 87F3F1B4F0E for ; Thu, 21 Aug 2025 00:46:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755737163; cv=none; b=DKBhCnlwIMLPUpyURC2kw2kxTa79HRAYldCdwS4SoUd9r5Ni3YzVtWGwf3uhBqGl/7RL7Xmbn7KBJpEcvsaJ0EWLge5ByGU6Nvxbr5/xPliD0iHYDuJLFhZgjvgAT1a9vWAYT0ocHxDLrw4s1q3WIkryc5YOb9/TkGu/Gj7fi1A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755737163; c=relaxed/simple; bh=lmvN+PIx41sGMMSHZVzOz18gMEdYBoA31KC2+1JFtjw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oXrPae+NZwBiTjF1Rs1f3jJZHlkoQOsFmr7x/znnrKBBpARsC5sPuabu0DBSQYf9kU2HbIUbbZUIAXfryJn1OqucEDWCFoGBNQ3Wkw1wh9jeonStBS7y+1RKCXtTAUOYKo4fs82xi0SeJQfgAApscWsXODIeL5qBfPg3nwq4wkY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E59FE12FC; Wed, 20 Aug 2025 17:45:52 -0700 (PDT) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 310E43F63F; Wed, 20 Aug 2025 17:45:59 -0700 (PDT) From: Andre Przywara To: Linus Walleij , Chen-Yu Tsai , Samuel Holland , Jernej Skrabec Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [RFC PATCH 9/9] pinctrl: sunxi: Add support for the Allwinner A733 Date: Thu, 21 Aug 2025 01:42:32 +0100 Message-ID: <20250821004232.8134-10-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250821004232.8134-1-andre.przywara@arm.com> References: <20250821004232.8134-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O The Allwinner A733 changes the layout of the pinctrl MMIO register frame, but stays otherwise rather close to the previous IP. The main PIO looks similar to the one in the A523, with ports B-K being implemented, each also with the same number of pins per port as on the A523. Use the DT based pinctrl driver to describe just the generic pinctrl properties, so advertise the number of pins per bank, interrupt capabilities and the new quirks. The actual function/mux assignment will be taken from the devicetree. Signed-off-by: Andre Przywara --- drivers/pinctrl/sunxi/Kconfig | 5 ++ drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c | 51 +++++++++++++++++++++ 3 files changed, 57 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index dc62eba96348e..831bb1dc93738 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -141,4 +141,9 @@ config PINCTRL_SUN55I_A523_R default ARM64 && ARCH_SUNXI select PINCTRL_SUNXI +config PINCTRL_SUN60I_A733 + bool "Support for the Allwinner A733 PIO" + default ARM64 && ARCH_SUNXI + select PINCTRL_SUNXI + endif diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 951b3f1e4b4f1..3658c9d06b498 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -29,5 +29,6 @@ obj-$(CONFIG_PINCTRL_SUN50I_H616) += pinctrl-sun50i-h616.o obj-$(CONFIG_PINCTRL_SUN50I_H616_R) += pinctrl-sun50i-h616-r.o obj-$(CONFIG_PINCTRL_SUN55I_A523) += pinctrl-sun55i-a523.o obj-$(CONFIG_PINCTRL_SUN55I_A523_R) += pinctrl-sun55i-a523-r.o +obj-$(CONFIG_PINCTRL_SUN60I_A733) += pinctrl-sun60i-a733.o obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c b/drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c new file mode 100644 index 0000000000000..1eafbf2ab3c97 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Allwinner A733 SoC pinctrl driver. + * + * Copyright (C) 2025 Arm Ltd. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" + +static const u8 a733_nr_bank_pins[SUNXI_PINCTRL_MAX_BANKS] = +/* PA PB PC PD PE PF PG PH PI PJ PK */ + { 0, 11, 17, 24, 16, 7, 15, 20, 17, 28, 26 }; + +static const u8 a733_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] = +/* PA PB PC PD PE PF PG PH PI PJ PK */ + { 0, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}; + +static struct sunxi_pinctrl_desc a733_pinctrl_data = { + .irq_banks = 10, + .irq_read_needs_mux = true, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, +}; + +static int a733_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_dt_table_init(pdev, a733_nr_bank_pins, + a733_irq_bank_muxes, + &a733_pinctrl_data, + SUNXI_PINCTRL_NCAT3_REG_LAYOUT | + SUNXI_PINCTRL_HAS_SET_CLEAR_REGS); +} + +static const struct of_device_id a733_pinctrl_match[] = { + { .compatible = "allwinner,sun60i-a733-pinctrl", }, + {} +}; + +static struct platform_driver a733_pinctrl_driver = { + .probe = a733_pinctrl_probe, + .driver = { + .name = "sun60i-a733-pinctrl", + .of_match_table = a733_pinctrl_match, + }, +}; +builtin_platform_driver(a733_pinctrl_driver);