From patchwork Wed Sep 3 00:09:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1090 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B2C1933993 for ; Wed, 3 Sep 2025 00:09:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756858191; cv=none; b=jl7ZJ7fVLz+mir4Te8VwL+JkFnbx9kzFSXF/698ruwmpu2bLSm5XJVN8zTrvW24PemcDP2Rs5Bzt2hIb5TjVwGFYrJf29k0I6PrP6Vw2VAKi/pa66h675eSjTo11wkqO0+nTC5M+Mh+V/wV3GluuKHaYOFZt+IParR/wdUxeqbw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756858191; c=relaxed/simple; bh=7jaBhKP6aquj0QdiYHOsMLmAdxNIil2qtgUj/DA20FA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IQilRhnLHsPycI77hFK29iYRRMWLod3omrVLNO4479eLT2qNPfFbqNWhgrW3h5KcsxPo6ImVAbIajvnFjr3lquUXsFxO3RVT+6Z9s2g7adIZXsG7lEzaZdCpXfGwM4dI5HNJCZlpvpvhcwity/PIXTk3X6YYyom1jWAGM4fR6Xs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A7548176A; Tue, 2 Sep 2025 17:09:40 -0700 (PDT) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 411363F63F; Tue, 2 Sep 2025 17:09:47 -0700 (PDT) From: Andre Przywara To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jernej Skrabec , Chen-Yu Tsai , Samuel Holland Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Mikhail Kalashnikov Subject: [PATCH 5/5] arm64: dts: allwinner: a523: add CPU clocks Date: Wed, 3 Sep 2025 01:09:10 +0100 Message-ID: <20250903000910.4860-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250903000910.4860-1-andre.przywara@arm.com> References: <20250903000910.4860-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O The Allwinner A523 family of SoCs feature a separate clock unit for the CPU PLLs and muxes, including one for the DSU interconnect. Add a DT node for the CPU clock controller, and list all the clocks from the other CCUs that this controller needs. Also list the clock source for each CPU: there is one clock for each cluster of four cores, suffixed L and B, for little and big (although all cores are of the same Cortex-A55 type). Signed-off-by: Andre Przywara --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index 6b6f2296bdff6..98a59d324bfeb 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,7 @@ cpu0: cpu@0 { device_type = "cpu"; reg = <0x000>; enable-method = "psci"; + clocks = <&cpu_ccu CLK_CPU_L>; }; cpu1: cpu@100 { @@ -31,6 +33,7 @@ cpu1: cpu@100 { device_type = "cpu"; reg = <0x100>; enable-method = "psci"; + clocks = <&cpu_ccu CLK_CPU_L>; }; cpu2: cpu@200 { @@ -38,6 +41,7 @@ cpu2: cpu@200 { device_type = "cpu"; reg = <0x200>; enable-method = "psci"; + clocks = <&cpu_ccu CLK_CPU_L>; }; cpu3: cpu@300 { @@ -45,6 +49,7 @@ cpu3: cpu@300 { device_type = "cpu"; reg = <0x300>; enable-method = "psci"; + clocks = <&cpu_ccu CLK_CPU_L>; }; cpu4: cpu@400 { @@ -52,6 +57,7 @@ cpu4: cpu@400 { device_type = "cpu"; reg = <0x400>; enable-method = "psci"; + clocks = <&cpu_ccu CLK_CPU_B>; }; cpu5: cpu@500 { @@ -59,6 +65,7 @@ cpu5: cpu@500 { device_type = "cpu"; reg = <0x500>; enable-method = "psci"; + clocks = <&cpu_ccu CLK_CPU_B>; }; cpu6: cpu@600 { @@ -66,6 +73,7 @@ cpu6: cpu@600 { device_type = "cpu"; reg = <0x600>; enable-method = "psci"; + clocks = <&cpu_ccu CLK_CPU_B>; }; cpu7: cpu@700 { @@ -73,6 +81,7 @@ cpu7: cpu@700 { device_type = "cpu"; reg = <0x700>; enable-method = "psci"; + clocks = <&cpu_ccu CLK_CPU_B>; }; }; @@ -690,5 +699,18 @@ rtc: rtc@7090000 { clock-names = "bus", "hosc", "ahb"; #clock-cells = <1>; }; + + cpu_ccu: clock-controller@8817000 { + compatible = "allwinner,sun55i-a523-cpu-ccu"; + reg = <0x08817000 0x80>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, <&ccu CLK_PLL_PERIPH0_2X>, + <&ccu CLK_PLL_PERIPH0_600M>; + clock-names = "hosc", "losc", + "iosc", "pll-periph0-2x", + "pll-periph0-600M"; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; };