From patchwork Fri Oct 10 08:40:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Genoud X-Patchwork-Id: 832 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C252B26D4F9 for ; Fri, 10 Oct 2025 08:41:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760085700; cv=none; b=SJpsHU+euVhg/3yabybL3kJ93X0aZz5zw3R1LtHhgw5eqKQIJzSkscwmMU8fF4uFOOhpbxrmE+mL8yHQfbsd6MKCi3bH4cGjexyfdPJYi90dSmm7ZKdn3zbSu6IRKE1vgcHtyOHVJZ+hwosKwsTHp5D3DVgivsAXeUvScjDs4aI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760085700; c=relaxed/simple; bh=22swiJ90UQtWYmeqL+UpJi6ywc207cbqVKAmiXiqLpU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=b9YueERF6vs5QLq2NXSLwrlxbnTj/45uu/epdlf8u1GYTazfvvJw/EXdALSM8/Ha/E1gqIdsUcI2rMoCLJ1DD7f+155pO044oRHW2YMdtbVQzz+lP7UGDj66RTWJTXT7VvLPxBNK5OYeBbKFVIi9yenTdKywhurGZ9ZLA9Bvy1Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=y8phVoq8; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="y8phVoq8" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id C167AC08CC4; Fri, 10 Oct 2025 08:41:18 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 6BAFB60667; Fri, 10 Oct 2025 08:41:37 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 63206102F2204; Fri, 10 Oct 2025 10:41:33 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1760085696; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=QLUI3DAeOf8Gf/4795RSqwfpn1jrg6BWZGq810jHUE4=; b=y8phVoq8g2wcSrJsqn8y2JdqJUR8dFEW9/j4t3nDpBDLbY5CvPoiRl9A7HYeMR2wPcv1zn ibcYf67gZJs5b8/51Mk0vtTcg4ueao9J1qgGBTN+ZKTycbF4nnisRmVZki3vdgtyQhUw1v uT613Xta3u40dAgd+sOgVMF/305o227he+bWqA9EU6Sn14sy2PXkWqhp6OPvcSvdAmGYuN OT5zDHb93cFUxVkLC0zLof/koSW6ujqGy1LBiy9wZ1NpANCLzt/ODzCpnzIuRdBLFbpmDS nCGwsAUxWBzajNNXlJ4J21hYkp7MQFFRbVnKoO21aLKeQHODOThkXM1UhBRRxw== From: Richard Genoud To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Wentao Liang , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Maxime Ripard , Thomas Petazzoni , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: [PATCH 03/15] arm64: dts: allwinner: h616: add NAND controller Date: Fri, 10 Oct 2025 10:40:30 +0200 Message-ID: <20251010084042.341224-4-richard.genoud@bootlin.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251010084042.341224-1-richard.genoud@bootlin.com> References: <20251010084042.341224-1-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 Status: O The H616 has a NAND controller quite similar to the A10/A23 ones, but with some register differences, more clocks (for ECC and MBUS), more ECC strengths, so this requires a new compatible string. This patch adds the NAND controller node and pins in the device tree. Signed-off-by: Richard Genoud --- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index ceedae9e399b..60626eba7f7c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -278,6 +278,37 @@ ir_rx_pin: ir-rx-pin { function = "ir_rx"; }; + nand_pins: nand-pins { + pins = "PC0", "PC1", "PC2", "PC5", "PC8", "PC9", + "PC10", "PC11", "PC12", "PC13", "PC14", + "PC15", "PC16"; + function = "nand0"; + }; + + nand_cs0_pin: nand-cs0-pin { + pins = "PC4"; + function = "nand0"; + bias-pull-up; + }; + + nand_cs1_pin: nand-cs1-pin { + pins = "PC3"; + function = "nand0"; + bias-pull-up; + }; + + nand_rb0_pin: nand-rb0-pin { + pins = "PC6"; + function = "nand0"; + bias-pull-up; + }; + + nand_rb1_pin: nand-rb1-pin { + pins = "PC7"; + function = "nand0"; + bias-pull-up; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -440,6 +471,25 @@ mmc2: mmc@4022000 { #size-cells = <0>; }; + nfc: nand-controller@4011000 { + compatible = "allwinner,sun50i-h616-nand-controller"; + reg = <0x04011000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND0>, + <&ccu CLK_NAND1>, <&ccu CLK_MBUS_NAND>; + clock-names = "ahb", "mod", "ecc", "mbus"; + resets = <&ccu RST_BUS_NAND>; + reset-names = "ahb"; + dmas = <&dma 10>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins>, <&nand_cs0_pin>, + <&nand_cs1_pin>, <&nand_rb0_pin>, + <&nand_rb1_pin>; + #address-cells = <1>; + #size-cells = <0>; + }; + uart0: serial@5000000 { compatible = "snps,dw-apb-uart"; reg = <0x05000000 0x400>;