From patchwork Thu Apr 23 17:40:01 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Mehall X-Patchwork-Id: 2028 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114]) by mxe881.netcup.net (Postfix) with ESMTPS id 1A4691C0063 for ; Thu, 23 Apr 2026 19:45:25 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=kevinmehall.net; dkim=pass header.d=messagingengine.com; spf=pass (sender IP is 172.105.105.114) smtp.mailfrom=linux-sunxi+bounces-22928-noreply=patchwork.local@lists.linux.dev smtp.helo=tor.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.105.105.114 as permitted sender) client-ip=172.105.105.114; envelope-from=linux-sunxi+bounces-22928-noreply=patchwork.local@lists.linux.dev; helo=tor.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by tor.lore.kernel.org (Postfix) with ESMTP id 0F6E330E2DE3 for ; Thu, 23 Apr 2026 17:40:59 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E78B13AB273; Thu, 23 Apr 2026 17:40:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kevinmehall.net header.i=@kevinmehall.net header.b="C8o916Sj"; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b="rXQ4sGqt" X-Original-To: linux-sunxi@lists.linux.dev Received: from fhigh-a1-smtp.messagingengine.com (fhigh-a1-smtp.messagingengine.com [103.168.172.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 015193A9DB3 for ; Thu, 23 Apr 2026 17:40:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.168.172.152 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776966045; cv=none; b=fMqd1IXTgE2y1aWq8Fi5xcnCzdFc3fLnkJhqlyCN3bxO/YYWJaKM/nXLqH283Ie4hWTPFlR/MuyIaGys1aZHHL6UpWpyBKuAtUlJlT7AISyFKmdXfrVa60Q3GFKwBFygKgCAVbI3KEAXpSvzjx5dRGLs3iMPJxl7p0VXXdzLdBY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776966045; c=relaxed/simple; bh=AVlgud0DfG/DvkOrRMBV349x4XRm8AFK7JWFHTSPPoo=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eFAyoG1f/4ffYttPzuXiP9rKqCxe4yvTc6Y5ZuKdjYyUCi9Q2/gbJhPRAoGBSxYGlAsmA2yHOeq8VOuBn1NjZv5hKVHqL5CuEG/r+H8Ex/t3OcMeMvCOzDSX2EW/SndYyGZIE0P6h32bqbL20JDte88/iwv6yH+VeZMVIcUcNMY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=kevinmehall.net; spf=pass smtp.mailfrom=kevinmehall.net; dkim=pass (2048-bit key) header.d=kevinmehall.net header.i=@kevinmehall.net header.b=C8o916Sj; dkim=pass (2048-bit key) header.d=messagingengine.com header.i=@messagingengine.com header.b=rXQ4sGqt; arc=none smtp.client-ip=103.168.172.152 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=kevinmehall.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=kevinmehall.net Received: from phl-compute-01.internal (phl-compute-01.internal [10.202.2.41]) by mailfhigh.phl.internal (Postfix) with ESMTP id 4762C1400050; Thu, 23 Apr 2026 13:40:42 -0400 (EDT) Received: from phl-frontend-03 ([10.202.2.162]) by phl-compute-01.internal (MEProxy); Thu, 23 Apr 2026 13:40:42 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kevinmehall.net; h=cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:subject:subject:to:to; s=fm1; t=1776966042; x= 1777052442; bh=eWtbr5dqWZd3m3MctHshuBfTOIExMLaOJtKGOKoZ2hk=; b=C 8o916SjzcFtReqmIs0JsHbuG2F8fuvpMUe39aAdWDgV1Grx/HUiZmoQe6Sn55ko2 Cvx4vO/jsRdcYsjdgBLUce3Bp/3qS0RW83FjgvYdJhcGYueZ3i4tIBkLB8uyMsYu Bj/CabzxSio9LwVVYnhDx2x7a66zC4br7xdu24qtR5UXgV1fAZI6bXf7yFMwDEkm oIiQVGYcXiWVdQL1wq/ZJqvuWhfX8OjtDUKv4ABo23ByatTuEPY3eH5uEInD8IpH t/o+PtgCs764EbOMqIrxPZ0BADXBq1NEJrX2BREz2uj4axYJLmApOcTja2yX0bRX Vpdh8yg3XS/Df1xfEwTjQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:date:feedback-id:feedback-id:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:subject :subject:to:to:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; t=1776966042; x=1777052442; bh=eWtbr5dqWZd3m3MctHshuBfTOIEx MLaOJtKGOKoZ2hk=; b=rXQ4sGqtKVq11G3IbWkYip96992ZT3SccFbUIG9anLU5 lmDgCZp1UKVeWik5SbMCROY750HZKh0heXJsDhKq9fwDFjZJHQ32VlYiHohvY6QW rSV4kEi37g+n23zQBXrGx1C/bJ76EXW24XkZ+h+0nGzwfwgWbBjkXpR1PYtLrHTD zmskTHgFpfyM1YmnhJGI14fBFnqQZTa9dFbiH/GKlXKVRG/B9Kfd2YJ/iblWhqNZ 6HkBS9cQEJbVCwqRh5CTIzn+TMHgka4SMMKO2Q158SjJZvkIKMQl48JLprxPQFnA cpZGdxGFYiCtWphd4IJnH/hEHoPCjqqfvKyIdcCO+g== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeefhedrtddtgdeijeejjecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpuffrtefokffrpgfnqfghnecuuegr ihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjug hrpefhvffufffkofgjfhgggfestdekredtredttdenucfhrhhomhepmfgvvhhinhcuofgv hhgrlhhluceokhhmsehkvghvihhnmhgvhhgrlhhlrdhnvghtqeenucggtffrrghtthgvrh hnpedttdefjeevjedvteekuedthefgueejuedujeehkeduudduieffteekjeektdegheen ucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehkmheskh gvvhhinhhmvghhrghllhdrnhgvthdpnhgspghrtghpthhtohepuddtpdhmohguvgepshhm thhpohhuthdprhgtphhtthhopegsrhhoohhnihgvsehkvghrnhgvlhdrohhrghdprhgtph htthhopeifvghnsheskhgvrhhnvghlrdhorhhgpdhrtghpthhtohepjhgvrhhnvghjrdhs khhrrggsvggtsehgmhgrihhlrdgtohhmpdhrtghpthhtohepshgrmhhuvghlsehshhholh hlrghnugdrohhrghdprhgtphhtthhopehmihhrkhhoqdguvghvkihlihhnuhigsehnrghn lhdruggvpdhrtghpthhtoheprhhstgesrhhunhhtuhigrdgtohhmpdhrtghpthhtoheplh hinhhugidqshhpihesvhhgvghrrdhkvghrnhgvlhdrohhrghdprhgtphhtthhopehlihhn uhigqdgrrhhmqdhkvghrnhgvlheslhhishhtshdrihhnfhhrrgguvggrugdrohhrghdprh gtphhtthhopehlihhnuhigqdhsuhhngihisehlihhsthhsrdhlihhnuhigrdguvghv X-ME-Proxy: Feedback-ID: i421842c8:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Thu, 23 Apr 2026 13:40:41 -0400 (EDT) From: Kevin Mehall To: Mark Brown , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Mirko Vogt , Ralf Schlatterbeck , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] spi: sun6i: Set SPI mode in prepare_message Date: Thu, 23 Apr 2026 11:40:01 -0600 Message-ID: <20260423174001.2797797-3-km@kevinmehall.net> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260423174001.2797797-1-km@kevinmehall.net> References: <20260423174001.2797797-1-km@kevinmehall.net> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-0.66 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.105.105.114:from]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; MAILLIST(-0.15)[generic]; BAD_REP_POLICIES(0.10)[]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; FROM_HAS_DN(0.00)[]; R_DKIM_ALLOW(0.00)[kevinmehall.net:s=fm1,messagingengine.com:s=fm2]; PRECEDENCE_BULK(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[kevinmehall.net:email,kevinmehall.net:dkim,messagingengine.com:dkim,tor.lore.kernel.org:rdns,tor.lore.kernel.org:helo]; TAGGED_RCPT(0.00)[]; RCVD_COUNT_SEVEN(0.00)[7]; FUZZY_BLOCKED(0.00)[rspamd.com]; FROM_NEQ_ENVFROM(0.00)[km@kevinmehall.net,linux-sunxi@lists.linux.dev]; TAGGED_FROM(0.00)[bounces-22928-noreply=patchwork.local]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; R_SPF_ALLOW(0.00)[+ip4:172.105.105.114]; DKIM_TRACE(0.00)[kevinmehall.net:+,messagingengine.com:+]; TO_DN_SOME(0.00)[]; FORGED_SENDER_MAILLIST(0.00)[]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[100.90.174.1:received,103.168.172.152:received]; ASN(0.00)[asn:63949, ipnet:172.105.96.0/20, country:SG]; DMARC_POLICY_ALLOW(0.00)[kevinmehall.net,reject]; FREEMAIL_TO(0.00)[kernel.org,gmail.com,sholland.org,nanl.de,runtux.com,vger.kernel.org,lists.infradead.org,lists.linux.dev]; RCVD_TLS_LAST(0.00)[]; RCPT_COUNT_SEVEN(0.00)[10]; MIME_TRACE(0.00)[0:+]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.105.105.114:from] X-Rspamd-Queue-Id: 1A4691C0063 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= With a GPIO chip select, CS is asserted before entering transfer_one. The spi-sun6i driver previously configured the SPI mode (including clock polarity) and enabled the bus in transfer_one, which can cause an extraneous SCK transition with CS asserted, corrupting the transferred data. This patch moves the SPI mode configuration and bus enable to the spi_prepare_message callback, ensuring that SCK is driven to the correct level prior to asserting CS. A previous fix for a related issue (0d7993b234c9f) was incomplete in that it only delayed enabling the SCK output drive to prevent it from being driven at the wrong level when resuming from autosuspend, but didn't help if switching CPOL modes between chip selects while active, or if SCK floats to the opposite level when suspended. Fixes: 0d7993b234c9 ("spi: spi-sun6i: Fix chipselect/clock bug") Signed-off-by: Kevin Mehall --- drivers/spi/spi-sun6i.c | 67 +++++++++++++++++++++++++---------------- 1 file changed, 41 insertions(+), 26 deletions(-) diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c index fc228574ed38..983e791e3396 100644 --- a/drivers/spi/spi-sun6i.c +++ b/drivers/spi/spi-sun6i.c @@ -205,6 +205,44 @@ static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) return SUN6I_MAX_XFER_SIZE - 1; } +static int sun6i_spi_prepare_message(struct spi_controller *ctlr, + struct spi_message *msg) +{ + struct sun6i_spi *sspi = spi_controller_get_devdata(ctlr); + struct spi_device *spi = msg->spi; + u32 reg; + + /* Set the mode bits in the transfer control register */ + reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); + + if (spi->mode & SPI_CPOL) + reg |= SUN6I_TFR_CTL_CPOL; + else + reg &= ~SUN6I_TFR_CTL_CPOL; + + if (spi->mode & SPI_CPHA) + reg |= SUN6I_TFR_CTL_CPHA; + else + reg &= ~SUN6I_TFR_CTL_CPHA; + + if (spi->mode & SPI_LSB_FIRST) + reg |= SUN6I_TFR_CTL_FBS; + else + reg &= ~SUN6I_TFR_CTL_FBS; + + sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); + + /* + * Now that the clock polarity is configured, enable the bus if the + * controller was previously suspended. + */ + reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG); + reg |= SUN6I_GBL_CTL_BUS_ENABLE; + sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg); + + return 0; +} + static void sun6i_spi_dma_rx_cb(void *param) { struct sun6i_spi *sspi = param; @@ -336,31 +374,12 @@ static int sun6i_spi_transfer_one(struct spi_controller *host, sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, reg); - /* - * Setup the transfer control register: Chip Select, - * polarities, etc. - */ - reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); - - if (spi->mode & SPI_CPOL) - reg |= SUN6I_TFR_CTL_CPOL; - else - reg &= ~SUN6I_TFR_CTL_CPOL; - - if (spi->mode & SPI_CPHA) - reg |= SUN6I_TFR_CTL_CPHA; - else - reg &= ~SUN6I_TFR_CTL_CPHA; - - if (spi->mode & SPI_LSB_FIRST) - reg |= SUN6I_TFR_CTL_FBS; - else - reg &= ~SUN6I_TFR_CTL_FBS; - /* * If it's a TX only transfer, we don't want to fill the RX * FIFO with bogus data */ + reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); + if (sspi->rx_buf) { reg &= ~SUN6I_TFR_CTL_DHB; rx_len = tfr->len; @@ -429,11 +448,6 @@ static int sun6i_spi_transfer_one(struct spi_controller *host, sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); } - /* Finally enable the bus - doing so before might raise SCK to HIGH */ - reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG); - reg |= SUN6I_GBL_CTL_BUS_ENABLE; - sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg); - /* Setup the transfer now... */ if (sspi->tx_buf) { tx_len = tfr->len; @@ -668,6 +682,7 @@ static int sun6i_spi_probe(struct platform_device *pdev) host->max_speed_hz = 100 * 1000 * 1000; host->min_speed_hz = 3 * 1000; host->use_gpio_descriptors = true; + host->prepare_message = sun6i_spi_prepare_message; host->set_cs = sun6i_spi_set_cs; host->transfer_one = sun6i_spi_transfer_one; host->num_chipselect = 4;