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a=ed25519-sha256; t=1777393718; l=1131; i=michal.piekos@mmpsystems.pl; s=20260301; h=from:subject:message-id; bh=WB+FLCQ1pB6/hLLpL8qe5azyJH79mgJP5EWQCmjzLQg=; b=3GNyRfpjDbtcqK/LKJuzrzfNjknCnh257Oxx/AACPv/6jmBonzBlC/rUmweHPXkCCV2s9ovxW +RWr7slZII6AWiXogzBlFfjGAxODMDIGJnMukfzR5ZNI2rzhBaiw/26 X-Developer-Key: i=michal.piekos@mmpsystems.pl; a=ed25519; pk=Aixyx03If7ZDamiKKN0lsa+0mtA+WjIuIf2ZQVYNBqg= X-Authenticated-Id: michal.piekos@mmpsystems.pl X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Describe high speed timer block on Allwinner T113-S3. Tested on LCPI-PC-T113/F113: - hstimer is registered as clocksource - switching clocksource at runtime works - after rating increase hstimer operates as a broadcast clockevent device Signed-off-by: Michal Piekos Reviewed-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi index 424f4a2487e2..40e76cfc8a1d 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi @@ -34,6 +34,17 @@ cpu1: cpu@1 { }; }; + soc { + hstimer@3008000 { + compatible = "allwinner,sun20i-d1-hstimer"; + reg = <0x03008000 0x1000>; + interrupts = , + ; + clocks = <&ccu CLK_BUS_HSTIMER>; + resets = <&ccu RST_BUS_HSTIMER>; + }; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x03021000 0x1000>,