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Sun, 19 Jul 2026 14:13:49 -0700 (PDT) Received: from localhost.localdomain ([2a0d:3344:2841:7708:a101:2b8a:f76:a00f]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49549a3e2a9sm224108815e9.4.2026.07.19.14.13.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Jul 2026 14:13:48 -0700 (PDT) From: =?utf-8?q?Juan_Manuel_L=C3=B3pez_Carrillo?= To: Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Brian Masney , Andre Przywara , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Juan_Manuel_L=C3=B3pez_Carrillo?= Subject: [PATCH v1 3/4] clk: sunxi-ng: sun55i-a523: reparent GPU while pll-gpu changes rate Date: Sun, 19 Jul 2026 23:13:18 +0200 Message-ID: <20260719211319.982285-4-juanmanuellopezcarrillo@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260719211319.982285-1-juanmanuellopezcarrillo@gmail.com> References: <20260719211319.982285-1-juanmanuellopezcarrillo@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-0.16 / 15.00]; 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TAGGED_FROM(0.00)[bounces-24534-noreply=patchwork.local]; R_SPF_ALLOW(0.00)[+ip4:172.234.253.10]; RCVD_COUNT_FIVE(0.00)[6]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 7FCE41C2CAE X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Register the existing sunxi-ng mux notifier on pll-gpu so the GPU mod clock is parked on the fixed pll-periph0-600M output while the PLL is being reprogrammed, and switched back once it has locked, following the cpux precedent of other sunxi SoCs. The mux switch is glitch-free per the T527 manual (GPU_CLK_REG, "The clock selection supports glitch-free switch"). Nothing retunes pll-gpu at runtime today (the mux does not propagate rate requests and all standard OPPs resolve to pll-periph0 outputs), but the higher speed-bin operating points (648-792 MHz) will need pll-gpu as a live parent, and any direct clk_set_rate() on the PLL is now safe. Signed-off-by: Juan Manuel López Carrillo --- drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c index 979e53e63..4341eb66c 100644 --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c @@ -1667,6 +1667,17 @@ static const u32 pll_regs[] = { SUN55I_A523_PLL_NPU_REG, }; +/* + * Park the GPU on the fixed pll-periph0-600M output while pll-gpu + * changes rate; the mux switch is glitch-free (T527 manual, GPU_CLK_REG). + */ +static struct ccu_mux_nb sun55i_a523_gpu_nb = { + .common = &gpu_clk.common, + .cm = &gpu_clk.mux, + .delay_us = 1, + .bypass_index = 1, /* pll-periph0-600M */ +}; + static int sun55i_a523_ccu_probe(struct platform_device *pdev) { void __iomem *reg; @@ -1698,6 +1709,10 @@ static int sun55i_a523_ccu_probe(struct platform_device *pdev) if (ret) return ret; + /* Reparent the GPU during pll-gpu rate changes */ + ccu_mux_notifier_register(pll_gpu_clk.common.hw.clk, + &sun55i_a523_gpu_nb); + return 0; }