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Wed, 22 Jul 2026 13:17:33 -0700 (PDT) Received: from zenbox ([2600:1700:18fb:6011:4392:41cd:1ce2:e391]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-6689056dfbasm1958866d50.9.2026.07.22.13.17.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2026 13:17:33 -0700 (PDT) From: Justin Suess To: Sean Young , Mauro Carvalho Chehab , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Sashiko , Justin Suess , Andre Przywara Subject: [PATCH v2 2/3] arm64: dts: allwinner: a523: add IR receiver nodes Date: Wed, 22 Jul 2026 16:17:16 -0400 Message-ID: <20260722201717.2205609-3-utilityemal77@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260722201717.2205609-1-utilityemal77@gmail.com> References: <20260722201717.2205609-1-utilityemal77@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [0.34 / 15.00]; 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PRECEDENCE_BULK(0.00)[]; ASN(0.00)[asn:63949, ipnet:172.105.96.0/20, country:SG]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; FREEMAIL_FROM(0.00)[gmail.com]; TAGGED_FROM(0.00)[bounces-24616-noreply=patchwork.local]; RCVD_COUNT_FIVE(0.00)[6]; FROM_NEQ_ENVFROM(0.00)[utilityemal77@gmail.com,linux-sunxi@lists.linux.dev]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: A6FA51C2B5B X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The A523 has two CIR receivers, both compatible with the A31 CIR: one in the CPUX domain, clocked from the main CCU, and one in the RTC power domain, clocked from the R-CCU. Add nodes for both instances, disabled by default. Since the RX signal of each instance can be routed to more than one pin, boards with an IR receiver are expected to add the pinctrl properties next to where they enable the node. Keep the PL11 pin description in the dtsi, as boards commonly use that pin for the RTC domain instance. Cc: Andre Przywara Signed-off-by: Justin Suess Reviewed-by: Andre Przywara --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index ca6a16807049..19771aac68e5 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -327,6 +327,17 @@ ccu: clock-controller@2001000 { #reset-cells = <1>; }; + ir: ir@2005000 { + compatible = "allwinner,sun55i-a523-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x02005000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_IR_RX>, <&ccu CLK_IR_RX>; + clock-names = "apb", "ir"; + resets = <&ccu RST_BUS_IR_RX>; + status = "disabled"; + }; + ledc: led-controller@2008000 { compatible = "allwinner,sun55i-a523-ledc", "allwinner,sun50i-a100-ledc"; @@ -927,6 +938,23 @@ r_i2c_pins: r-i2c-pins { allwinner,pinmux = <2>; function = "r_i2c0"; }; + + r_ir_rx_pin: r-ir-rx-pin { + pins = "PL11"; + allwinner,pinmux = <2>; + function = "s_cir"; + }; + }; + + r_ir: ir@7040000 { + compatible = "allwinner,sun55i-a523-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x07040000 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_BUS_R_IR_RX>, <&r_ccu CLK_R_IR_RX>; + clock-names = "apb", "ir"; + resets = <&r_ccu RST_BUS_R_IR_RX>; + status = "disabled"; }; pck600: power-controller@7060000 {