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Wed, 22 Jul 2026 14:01:17 -0700 (PDT) Received: from coolemuke.fritz.box ([2a00:6020:b320:1a00:c256:1463:a40b:d8c6]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f85c63678sm8610812f8f.29.2026.07.22.14.01.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2026 14:01:17 -0700 (PDT) From: " =?utf-8?q?S=C3=B6ren_Hantel?= " X-Google-Original-From: =?utf-8?q?S=C3=B6ren_Hantel?= To: linux-pm@vger.kernel.org Cc: Vasily Khoruzhick , Yangtao Li , "Rafael J . Wysocki" , Daniel Lezcano , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Rossak , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Claude Fable 5 , =?utf-8?q?S=C3=B6ren_Hantel?= Subject: [PATCH v2 3/3] ARM: dts: sun9i-a80: Add thermal sensor and thermal zones Date: Wed, 22 Jul 2026 23:00:46 +0200 Message-ID: <20260722210046.2932498-4-fugininsane@googlemail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260722210046.2932498-1-fugininsane@googlemail.com> References: <20260722203341.2917852-1-fugininsane@googlemail.com> <20260722210046.2932498-1-fugininsane@googlemail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= From: Philipp Rossak Now that the A80 thermal sensor is supported, add its device node and the thermal zones to the device tree. The clocks and the resets are shared between the GPADC and the THS sensor. Sensor 0 is located beside the big CPU cluster, sensor 1 beside the DRAM controller, sensor 2 beside the GPU and sensor 3 beside the little CPU cluster. Signed-off-by: Philipp Rossak [soeren: rebased from the 2018 series, fixed the interrupt number (SPI 115 as in the vendor BSP; verified on hardware - SPI 31 stays silent), added critical trip points matching the driver's emergency shutdown threshold] Co-authored-by: Claude Fable 5 Signed-off-by: Sören Hantel --- arch/arm/boot/dts/allwinner/sun9i-a80.dtsi | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi index a1ae092..8e7f8cd 100644 --- a/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi @@ -941,6 +941,16 @@ #reset-cells = <1>; }; + ths: thermal-sensor@6004c00 { + compatible = "allwinner,sun9i-a80-ths"; + reg = <0x06004c00 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_GPADC>, <&ccu CLK_GPADC>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_GPADC>; + #thermal-sensor-cells = <1>; + }; + timer@6000c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x06000c00 0xa0>; @@ -1250,4 +1260,62 @@ #size-cells = <0>; }; }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&ths 0>; + + trips { + cpu0_crit: cpu0-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + dram_thermal: dram-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&ths 1>; + + trips { + dram_crit: dram-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&ths 2>; + + trips { + gpu_crit: gpu-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu2_thermal: cpu2-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&ths 3>; + + trips { + cpu2_crit: cpu2-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; };