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FORGED_SENDER_MAILLIST(0.00)[]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; RCVD_TLS_LAST(0.00)[]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; MIME_TRACE(0.00)[0:+]; TAGGED_FROM(0.00)[bounces-24670-noreply=patchwork.local]; ASN(0.00)[asn:63949, ipnet:172.105.96.0/20, country:SG]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: BDAA11C2B5B X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Extract the GRF-level HPD interrupt mask/unmask register writes into dedicated dw_hdmi_qp_rk35{88,76}_{mask,unmask}_hpd() helpers, and use them from the .enable_hpd()/.disable_hpd() phy ops as well as the hardirq, threaded re-arm and io_init() paths. This is a preparatory refactor that separates the SoC-level HPD mask from the phy op entry points, so a subsequent change can gate the platform HPD IRQ line without affecting the debounce paths. Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 54 ++++++++++++++++++-------- 1 file changed, 37 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c index 5067e3cf0e88..cdddbbb8b80b 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -277,9 +277,8 @@ dw_hdmi_qp_rk3588_read_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) return val ? connector_status_connected : connector_status_disconnected; } -static void dw_hdmi_qp_rk3588_enable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) +static void dw_hdmi_qp_rk3588_unmask_hpd(struct rockchip_hdmi_qp *hdmi) { - struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; u32 val; if (hdmi->port_id) @@ -292,9 +291,8 @@ static void dw_hdmi_qp_rk3588_enable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); } -static void dw_hdmi_qp_rk3588_disable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) +static void dw_hdmi_qp_rk3588_mask_hpd(struct rockchip_hdmi_qp *hdmi) { - struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; u32 val; if (hdmi->port_id) @@ -305,6 +303,20 @@ static void dw_hdmi_qp_rk3588_disable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); } +static void dw_hdmi_qp_rk3588_enable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) +{ + struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; + + dw_hdmi_qp_rk3588_unmask_hpd(hdmi); +} + +static void dw_hdmi_qp_rk3588_disable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) +{ + struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; + + dw_hdmi_qp_rk3588_mask_hpd(hdmi); +} + static const struct dw_hdmi_qp_phy_ops rk3588_hdmi_phy_ops = { .init = dw_hdmi_qp_rk3588_phy_init, .disable = dw_hdmi_qp_rk3588_phy_disable, @@ -325,23 +337,31 @@ dw_hdmi_qp_rk3576_read_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) connector_status_connected : connector_status_disconnected; } +static void dw_hdmi_qp_rk3576_unmask_hpd(struct rockchip_hdmi_qp *hdmi) +{ + regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, + FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_CLR, 1) | + FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 0)); +} + +static void dw_hdmi_qp_rk3576_mask_hpd(struct rockchip_hdmi_qp *hdmi) +{ + regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, + FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 1)); +} + static void dw_hdmi_qp_rk3576_enable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) { struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; - u32 val; - val = (FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_CLR, 1) | - FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 0)); - - regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val); + dw_hdmi_qp_rk3576_unmask_hpd(hdmi); } static void dw_hdmi_qp_rk3576_disable_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) { struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; - regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, - FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 1)); + dw_hdmi_qp_rk3576_mask_hpd(hdmi); } static const struct dw_hdmi_qp_phy_ops rk3576_hdmi_phy_ops = { @@ -375,7 +395,7 @@ static irqreturn_t dw_hdmi_qp_rk3576_hardirq(int irq, void *dev_id) regmap_read(hdmi->regmap, RK3576_IOC_HDMI_HPD_STATUS, &intr_stat); if (intr_stat & RK3576_HDMI_OHPD_INT) { - dw_hdmi_qp_rk3576_disable_hpd(NULL, hdmi); + dw_hdmi_qp_rk3576_mask_hpd(hdmi); return IRQ_WAKE_THREAD; } @@ -389,7 +409,7 @@ static irqreturn_t dw_hdmi_qp_rk3576_irq(int irq, void *dev_id) mod_delayed_work(system_percpu_wq, &hdmi->hpd_work, msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS)); - dw_hdmi_qp_rk3576_enable_hpd(NULL, hdmi); + dw_hdmi_qp_rk3576_unmask_hpd(hdmi); return IRQ_HANDLED; } @@ -404,7 +424,7 @@ static irqreturn_t dw_hdmi_qp_rk3588_hardirq(int irq, void *dev_id) intr_stat &= hdmi->port_id ? RK3588_HDMI1_OHPD_INT : RK3588_HDMI0_OHPD_INT; if (intr_stat) { - dw_hdmi_qp_rk3588_disable_hpd(NULL, hdmi); + dw_hdmi_qp_rk3588_mask_hpd(hdmi); return IRQ_WAKE_THREAD; } @@ -418,7 +438,7 @@ static irqreturn_t dw_hdmi_qp_rk3588_irq(int irq, void *dev_id) mod_delayed_work(system_percpu_wq, &hdmi->hpd_work, msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS)); - dw_hdmi_qp_rk3588_enable_hpd(NULL, hdmi); + dw_hdmi_qp_rk3588_unmask_hpd(hdmi); return IRQ_HANDLED; } @@ -435,7 +455,7 @@ static void dw_hdmi_qp_rk3576_io_init(struct rockchip_hdmi_qp *hdmi) regmap_write(hdmi->regmap, 0xa404, 0xffff0102); - dw_hdmi_qp_rk3576_disable_hpd(NULL, hdmi); + dw_hdmi_qp_rk3576_mask_hpd(hdmi); } static void dw_hdmi_qp_rk3588_io_init(struct rockchip_hdmi_qp *hdmi) @@ -460,7 +480,7 @@ static void dw_hdmi_qp_rk3588_io_init(struct rockchip_hdmi_qp *hdmi) val = FIELD_PREP_WM16(RK3588_HDMI0_GRANT_SEL, 1); regmap_write(hdmi->vo_regmap, RK3588_GRF_VO1_CON9, val); - dw_hdmi_qp_rk3588_disable_hpd(NULL, hdmi); + dw_hdmi_qp_rk3588_mask_hpd(hdmi); } static void dw_hdmi_qp_rk3576_enc_init(struct rockchip_hdmi_qp *hdmi,