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Mon, 27 Jul 2026 19:49:22 -0700 (PDT) Received: from zenbox ([2600:1700:18fb:6011:722a:22a9:308b:2c35]) by smtp.gmail.com with ESMTPSA id 00721157ae682-81f6579f462sm40974847b3.11.2026.07.27.19.49.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jul 2026 19:49:21 -0700 (PDT) From: Justin Suess To: Sean Young , Mauro Carvalho Chehab , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Sashiko , Justin Suess , Andre Przywara Subject: [PATCH v4 2/4] arm64: dts: allwinner: a523: add IR receiver nodes Date: Mon, 27 Jul 2026 22:49:14 -0400 Message-ID: <20260728024916.993224-3-utilityemal77@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260728024916.993224-1-utilityemal77@gmail.com> References: <20260728024916.993224-1-utilityemal77@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The A523 has two CIR receivers, both compatible with the A31 CIR: one in the CPUX domain, clocked from the main CCU, and one in the RTC power domain, clocked from the R-CCU. The RTC domain instance's RX signal is typically muxed to PL11, as on the X96Q Pro+. The CPUX instance's can be muxed to PI8, which is what the Avaota A1 uses. Add nodes for both instances, disabled by default. Since the RX signal of each instance can be routed to more than one pin, boards with an IR receiver are expected to add the pinctrl properties next to where they enable the node. Add pinmux nodes for both pins: PL11 for the RTC domain instance, and PI8 for the CPUX one. Co-developed-by: Andre Przywara Signed-off-by: Andre Przywara Signed-off-by: Justin Suess --- Notes: v4: - add /omit-if-no-ref/ and rename to r-ir-rx-pl-pin (Chen-Yu) - take the PI8 pinmux node from Andre's Avaota patch, named ir-rx-pi-pin (Chen-Yu); Co-developed-by added and Andre's Reviewed-by dropped, since the patch has a new hunk plus pinmux node name change. .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index ca6a16807049..f0b74693da7f 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -155,6 +155,13 @@ i2s2_pi_pins: i2s2-pi-pins { bias-disable; }; + /omit-if-no-ref/ + ir_rx_pin: ir-rx-pi-pin { + pins = "PI8"; + allwinner,pinmux = <3>; + function = "cir_rx"; + }; + /omit-if-no-ref/ ledc_ph_pin: ledc-ph-pin { pins = "PH19"; @@ -327,6 +334,17 @@ ccu: clock-controller@2001000 { #reset-cells = <1>; }; + ir: ir@2005000 { + compatible = "allwinner,sun55i-a523-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x02005000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_IR_RX>, <&ccu CLK_IR_RX>; + clock-names = "apb", "ir"; + resets = <&ccu RST_BUS_IR_RX>; + status = "disabled"; + }; + ledc: led-controller@2008000 { compatible = "allwinner,sun55i-a523-ledc", "allwinner,sun50i-a100-ledc"; @@ -927,6 +945,24 @@ r_i2c_pins: r-i2c-pins { allwinner,pinmux = <2>; function = "r_i2c0"; }; + + /omit-if-no-ref/ + r_ir_rx_pin: r-ir-rx-pl-pin { + pins = "PL11"; + allwinner,pinmux = <2>; + function = "s_cir_rx"; + }; + }; + + r_ir: ir@7040000 { + compatible = "allwinner,sun55i-a523-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x07040000 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_BUS_R_IR_RX>, <&r_ccu CLK_R_IR_RX>; + clock-names = "apb", "ir"; + resets = <&r_ccu RST_BUS_R_IR_RX>; + status = "disabled"; }; pck600: power-controller@7060000 {