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[184.96.154.59]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-45e3510fa5fsm713176fac.1.2026.08.11.16.11.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Aug 2026 16:11:56 -0700 (PDT) From: James Hilliard Date: Tue, 11 Aug 2026 17:11:30 -0600 Subject: [PATCH v7 1/2] dt-bindings: mfd: x-powers: Add AC200 Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260811-submit-ac200-mfd-v7-1-8b06f552a4d7@gmail.com> References: <20260811-submit-ac200-mfd-v7-0-8b06f552a4d7@gmail.com> In-Reply-To: <20260811-submit-ac200-mfd-v7-0-8b06f552a4d7@gmail.com> To: Lee Jones , Arnd Bergmann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , James Hilliard Cc: Andrew Lunn , "Jagielski, Jedrzej" , Andre Przywara , Chen-Yu Tsai , =?utf-8?q?Jernej_=C5=A0krabec?= , linux-sunxi@lists.linux.dev, mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-1.16 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[104.64.211.4:from]; SUSPICIOUS_RECIPS(1.50)[]; DMARC_POLICY_SOFTFAIL(1.00)[gmail.com : SPF not aligned (relaxed), No valid DKIM,none]; MAILLIST(-0.15)[generic]; MIME_GOOD(-0.10)[text/plain]; BAD_REP_POLICIES(0.10)[]; HAS_LIST_UNSUB(-0.01)[]; RCPT_COUNT_TWELVE(0.00)[15]; PRECEDENCE_BULK(0.00)[]; FROM_HAS_DN(0.00)[]; FORGED_SENDER_MAILLIST(0.00)[]; TAGGED_RCPT(0.00)[dt]; FREEMAIL_CC(0.00)[lunn.ch,intel.com,arm.com,kernel.org,gmail.com,lists.linux.dev,vger.kernel.org]; DBL_BLOCKED_OPENRESOLVER(0.00)[sin.lore.kernel.org:rdns,sin.lore.kernel.org:helo,devicetree.org:url]; DBL_PROHIBIT(0.00)[0.0.0.10:email]; RCVD_COUNT_FIVE(0.00)[6]; ASN(0.00)[asn:63949, ipnet:104.64.192.0/19, country:SG]; R_SPF_ALLOW(0.00)[+ip4:104.64.211.4]; FREEMAIL_TO(0.00)[kernel.org,arndb.de,gmail.com]; FREEMAIL_FROM(0.00)[gmail.com]; TO_DN_SOME(0.00)[]; FROM_NEQ_ENVFROM(0.00)[jameshilliard1@gmail.com,linux-sunxi@lists.linux.dev]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; RCVD_TLS_LAST(0.00)[]; TAGGED_FROM(0.00)[bounces-25114-noreply=patchwork.local]; MIME_TRACE(0.00)[0:+]; MID_RHS_MATCH_FROM(0.00)[]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: B43451C0244 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The AC200 is an I2C-controlled mixed-signal companion IC containing audio, video, RTC and Fast Ethernet PHY functions. Describe the parent device and its shared input clock. The Ethernet PHY is represented by a PHY package on its MDIO bus, with a phandle back to this device for access to the package control registers, so it does not require an MFD child node. Function-specific supplies belong to their consumer bindings rather than the shared parent. The input clock must run at 24 or 27 MHz when the Ethernet PHY is used, matching the rates encoded by its documented clock selector. Signed-off-by: James Hilliard Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/mfd/x-powers,ac200.yaml | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/x-powers,ac200.yaml b/Documentation/devicetree/bindings/mfd/x-powers,ac200.yaml new file mode 100644 index 000000000000..609831b15c80 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/x-powers,ac200.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/x-powers,ac200.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: X-Powers AC200 mixed-signal IC + +maintainers: + - James Hilliard + +description: + The AC200 is a mixed-signal companion IC containing audio, video, RTC and + Fast Ethernet PHY functions. Its control registers are accessed over I2C. + +properties: + compatible: + const: x-powers,ac200 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: + AC200 input clock. When using the Ethernet PHY, its configured rate must + be 24 or 27 MHz, matching the rates encoded by the documented EPHY clock + selector. + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + mixed-signal@10 { + compatible = "x-powers,ac200"; + reg = <0x10>; + clocks = <&pwm 5>; + }; + }; +...