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Tue, 25 Aug 2026 18:30:27 -0700 (PDT) Received: from [172.17.0.2] ([138.28.231.64]) by smtp.gmail.com with ESMTPSA id af79cd13be357-9377e67c52csm102398585a.38.2026.08.25.18.30.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2026 18:30:26 -0700 (PDT) From: Yuanshen Cao Date: Wed, 26 Aug 2026 01:30:05 +0000 Subject: [PATCH v4 3/5] dmaengine: sun6i-dma: Add num_channels_per_reg for flexible interrupt mapping Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260826-sun60i-a733-dma-v4-3-dc2f745f40dc@gmail.com> References: <20260826-sun60i-a733-dma-v4-0-dc2f745f40dc@gmail.com> In-Reply-To: <20260826-sun60i-a733-dma-v4-0-dc2f745f40dc@gmail.com> To: Vinod Koul , Frank Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: Yuanshen Cao , dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.16.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-1.16 / 15.00]; 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FREEMAIL_TO(0.00)[kernel.org,gmail.com,sholland.org]; MIME_TRACE(0.00)[0:+]; TAGGED_FROM(0.00)[bounces-25352-noreply=patchwork.local]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; RCVD_TLS_LAST(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 9B3371C0565 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The `sun6i-dma` driver previously assumed a fixed number of channels per interrupt register. For example, `sun6i_kill_tasklet` was hardcoded to disable interrupts only for registers 0 and 1. `DMA_MAX_CHANNELS` was also not in used previously, and the old SoCs never has more than 16 channels. The A733 has a different interrupt structure where the number of channels per register may differ. Add `num_channels_per_reg` to `struct sun6i_dma_config` to make the interrupt handling logic handware-agnostic Update `sun6i_dma_interrupt`, `sun6i_dma_start_desc`, and `sun6i_kill_tasklet` to use this value. Additionally, set `DMA_MAX_CHANNELS` to 16 to ensure loops over interrupts are correctly bounded, aligning with the hardware specifications. Signed-off-by: Yuanshen Cao --- drivers/dma/sun6i-dma.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index 53c54161e32a..b96d7d90f6b5 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -35,14 +35,13 @@ #define DMA_IRQ_PKG BIT(1) #define DMA_IRQ_QUEUE BIT(2) -#define DMA_IRQ_CHAN_NR 8 #define DMA_IRQ_CHAN_WIDTH 4 #define DMA_STAT 0x30 /* Offset between DMA_IRQ_EN and DMA_IRQ_STAT limits number of channels */ -#define DMA_MAX_CHANNELS (DMA_IRQ_CHAN_NR * 0x10 / 4) +#define DMA_MAX_CHANNELS 16 /* * sun8i specific registers @@ -61,6 +60,8 @@ #define DMA_IRQ_EN_OFFSET_A31 0x00 #define DMA_IRQ_STAT_OFFSET_A31 0x10 +#define DMA_IRQ_CHAN_NR_A31 8 + /* * Channels specific registers */ @@ -157,6 +158,7 @@ struct sun6i_dma_config { u32 irq_stride; u32 irq_en_offset; u32 irq_stat_offset; + u32 num_channels_per_reg; }; /* @@ -271,7 +273,7 @@ static inline void sun6i_dma_dump_com_regs(struct sun6i_dma_dev *sdev) { int i; - for (i = 0; i < 2; i++) { + for (i = 0; i < DIV_ROUND_UP(sdev->num_pchans, sdev->cfg->num_channels_per_reg); i++) { dev_dbg(sdev->slave.dev, "Common register:\n" "chan num %d\n" "\tmask(%04x): 0x%08x\n" @@ -492,8 +494,8 @@ static int sun6i_dma_start_desc(struct sun6i_vchan *vchan) sun6i_dma_dump_lli(vchan, pchan->desc->v_lli, pchan->desc->p_lli); - irq_reg = pchan->idx / DMA_IRQ_CHAN_NR; - irq_offset = pchan->idx % DMA_IRQ_CHAN_NR; + irq_reg = pchan->idx / sdev->cfg->num_channels_per_reg; + irq_offset = pchan->idx % sdev->cfg->num_channels_per_reg; vchan->irq_type = vchan->cyclic ? DMA_IRQ_PKG : DMA_IRQ_QUEUE; @@ -585,7 +587,7 @@ static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id) int i, j, ret = IRQ_NONE; u32 status; - for (i = 0; i < sdev->num_pchans / DMA_IRQ_CHAN_NR; i++) { + for (i = 0; i < sdev->num_pchans / sdev->cfg->num_channels_per_reg; i++) { status = sun6i_read_irq_stat(sdev, i); if (!status) continue; @@ -595,7 +597,7 @@ static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id) sun6i_write_irq_stat(sdev, i, status); - for (j = 0; (j < DMA_IRQ_CHAN_NR) && status; j++) { + for (j = 0; (j < sdev->cfg->num_channels_per_reg) && status; j++) { pchan = sdev->pchans + j; vchan = pchan->vchan; if (vchan && (status & vchan->irq_type)) { @@ -1113,7 +1115,7 @@ static inline void sun6i_kill_tasklet(struct sun6i_dma_dev *sdev) int i; /* Disable all interrupts from DMA */ - for (i = 0; i < 2; i++) + for (i = 0; i < DMA_MAX_CHANNELS / sdev->cfg->num_channels_per_reg; i++) sun6i_write_irq_en(sdev, i, 0); /* Prevent spurious interrupts from scheduling the tasklet */ @@ -1141,7 +1143,8 @@ static inline void sun6i_dma_free(struct sun6i_dma_dev *sdev) #define SUN6I_DMA_IRQ_A31_COMMON_CFG \ .irq_stride = DMA_IRQ_STRIDE_A31, \ .irq_en_offset = DMA_IRQ_EN_OFFSET_A31, \ - .irq_stat_offset = DMA_IRQ_STAT_OFFSET_A31, + .irq_stat_offset = DMA_IRQ_STAT_OFFSET_A31, \ + .num_channels_per_reg = DMA_IRQ_CHAN_NR_A31, /* * For A31: