From patchwork Sun Sep 6 07:06:39 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junhui Liu X-Patchwork-Id: 3202 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 4628D1C075F for ; Sun, 6 Sep 2026 09:07:52 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=pigmoral.tech; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-25632-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; envelope-from=linux-sunxi+bounces-25632-noreply=patchwork.local@lists.linux.dev; helo=sea.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sea.lore.kernel.org (Postfix) with ESMTP id 009D330A3A for ; Sun, 6 Sep 2026 07:07:32 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D23E930BBBF; Sun, 6 Sep 2026 07:07:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="ErSJ/RhF" X-Original-To: linux-sunxi@lists.linux.dev Received: from sender6-op-o12.zoho.com (sender6-op-o12.zoho.com [165.173.180.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD945233956 for ; Sun, 6 Sep 2026 07:07:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=165.173.180.12 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788678451; cv=pass; b=DxOimTUARNoE8hgiNJ8E83fYlhzc3ORl8jt3os+pj58lr2sn6NinVKBO09PhG7d5isq6Ot21CG2hT1xVt+UfRVW875yHsPShIZm4RWVxEPcYfgOarAQR1n6FHNAcZ18FRBsMgFMQ7iTob+EYWLpnStp8XPH9HEfHyxOkFuNVFIg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788678451; c=relaxed/simple; bh=sx6BJ1JsCbiIy8jm4gR7Z3AI1Jw4H0UuT/5mJyKCVds=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DTU2y35RglLMvU3xAmREnr8UQL//6yVZC+V5/p6Cf5PytiRpotJoUzL+oXElbryzVoZHMumy74NrkdN0iyv6zaSggd8QiCnHOlt9HNrk6t6lNv+eCZLxfS7QeDUfLt+QZJrHf1Z81h+Bjt+B1IsSnprqGElkt6UqzVdp4TsEAXI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=ErSJ/RhF; arc=pass smtp.client-ip=165.173.180.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech ARC-Seal: i=1; a=rsa-sha256; t=1788678441; cv=none; d=zohomail.com; s=zohoarc; b=dniKCp0OKnLpZamZrVrHUROl0KW+1eQHZuv7oT3JVmt/p27lpT03/6kTertNcG08PdyHz6VhMcgxfPpy0dxJWMM5fLJtvs6Mf8+UwOuQByjqiuNe4XvQuMr7FhCXlSdlU3dxuv8AdmACCIX8+v+Gwn+f6n0XzvzYIITshGTgxSM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1788678441; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:Subject:Subject:To:To:Message-Id:Reply-To; bh=vuBYatI2A+T0vk/pTOo+2ExTt5PEnYd3ra3QdMzmI10=; b=gt55zeeI20UFoJk+ZKKfmFV5MUkS2F9KfBeM5agDm3kThBC333WYni+KvO1NcrMqrnoQtMwUE3+Ywrof8cRrYaVayTO8tdWcvCZ/IUTx6dElKTimYbBXLlC0PspMLzg4+S0Aw5WGyMWgbPF8dLvCzWLpBfo8yw/pMk2SUkJUvyw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1788678441; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=vuBYatI2A+T0vk/pTOo+2ExTt5PEnYd3ra3QdMzmI10=; b=ErSJ/RhFd6V5oLq18stBgO1xfg11N3i3KgR8rm6cDgEt8p7/rv9DmrRyTW6XLSqm 450s0pM7kCr/nXiQE4t2Wt5Lc4jGwTV9ihk5NvJDpAytkcOT7vRK4iqWY38BcXa6QUS xLGlN0qseY9voEXzaul+wBfY5s1wUPnHvLH0Gq5Q= Received: by mx.zohomail.com with SMTPS id 1788678439638627.6650541040009; Sun, 6 Sep 2026 00:07:19 -0700 (PDT) From: Junhui Liu Date: Sun, 06 Sep 2026 15:06:39 +0800 Subject: [PATCH 2/4] clk: sunxi-ng: sun55i-a523-ccu: Use M-only clocks for MBUS, IOMMU and DRAM Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260906-sunxi-clk-no-p-v1-2-cbde21c9fe69@pigmoral.tech> References: <20260906-sunxi-clk-no-p-v1-0-cbde21c9fe69@pigmoral.tech> In-Reply-To: <20260906-sunxi-clk-no-p-v1-0-cbde21c9fe69@pigmoral.tech> To: Stephen Boyd , Brian Masney , Jerome Brunet , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Junhui Liu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3217; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=sx6BJ1JsCbiIy8jm4gR7Z3AI1Jw4H0UuT/5mJyKCVds=; b=owGbwMvMwCWWvDb1VEXc8j+Mp9WSGLLmCnL/FcvceERrrnjPiqn+Kx85S18/1bgokbf53hLfP Z55dUtlOkpZGMS4GGTFFFm4/MX/WevwfDsi0HofZg4rE8gQBi5OAZjIKmdGhj0BzNz3NH9q1oQ1 F1hbrXuT7Ls8p3pGQIJb0ZZnf1bOdmP4K3hRQyFZVELXZ9lHjiuBrDfcv/nxPNi5oKCvTzHg+uE QPgA= X-Developer-Key: i=junhui.liu@pigmoral.tech; a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The MBUS, IOMMU, and DRAM clocks only have an M divider, but are currently modeled as MP clocks with a zero-width P divider. ccu_mp_set_rate() generates an invalid mask for the zero-width P divider, clearing unrelated register fields. It also ignores CCU_FEATURE_UPDATE_BIT, so the new divider value does not take effect. Model these clocks as M-only clocks instead. This avoids accessing a nonexistent P divider and uses ccu_div_set_rate(), which handles the update bit. Fixes: 74b0443a0d0a ("clk: sunxi-ng: a523: add system mod clocks") Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 45 ++++++++++++++++------------------ 1 file changed, 21 insertions(+), 24 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c index 20dad06b37ca..9bc3ff0ab12d 100644 --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c @@ -380,14 +380,13 @@ static const struct clk_parent_data mbus_parents[] = { { .hw = &pll_periph1_150M_clk.hw }, { .fw_name = "hosc" }, }; -static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, - 0x540, - 0, 5, /* M */ - 0, 0, /* no P */ - 24, 3, /* mux */ - BIT(31), /* gate */ - CLK_IS_CRITICAL, - CCU_FEATURE_UPDATE_BIT); +static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, + 0x540, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_IS_CRITICAL, + CCU_FEATURE_UPDATE_BIT); static const struct clk_hw *mbus_hws[] = { &mbus_clk.common.hw }; @@ -584,14 +583,13 @@ static const struct clk_parent_data iommu_parents[] = { { .fw_name = "hosc" }, }; -static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(iommu_clk, "iommu", iommu_parents, - 0x7b0, - 0, 5, /* M */ - 0, 0, /* no P */ - 24, 3, /* mux */ - BIT(31), /* gate */ - CLK_SET_RATE_PARENT, - CCU_FEATURE_UPDATE_BIT); +static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(iommu_clk, "iommu", iommu_parents, + 0x7b0, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT, + CCU_FEATURE_UPDATE_BIT); static SUNXI_CCU_GATE_HWS(bus_iommu_clk, "bus-iommu", apb0_hws, 0x7bc, BIT(0), 0); @@ -603,14 +601,13 @@ static const struct clk_parent_data dram_parents[] = { { .hw = &pll_periph0_400M_clk.hw }, { .hw = &pll_periph0_150M_clk.hw }, }; -static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(dram_clk, "dram", dram_parents, - 0x800, - 0, 5, /* M */ - 0, 0, /* no P */ - 24, 3, /* mux */ - BIT(31), /* gate */ - CLK_IS_CRITICAL, - CCU_FEATURE_UPDATE_BIT); +static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(dram_clk, "dram", dram_parents, + 0x800, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_IS_CRITICAL, + CCU_FEATURE_UPDATE_BIT); static SUNXI_CCU_GATE_HWS(mbus_dma_clk, "mbus-dma", mbus_hws, 0x804, BIT(0), 0);