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Mon, 07 Sep 2026 17:32:04 +0200 (CEST) Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac]) by drehscheibe.grey.stw.pengutronix.de with esmtp (Exim 4.96) (envelope-from ) id 1x3bKG-000Ym1-0P; Mon, 07 Sep 2026 17:32:04 +0200 From: Jonas Rebmann Date: Mon, 07 Sep 2026 17:31:41 +0200 Subject: [PATCH v2 2/6] spi: spi-sun4i: sun4i_spi_fill_fifo(): always apply A10 FIFO fill level workaround Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260907-spi-sun4i-fixes-v2-2-7e805662b9bd@pengutronix.de> References: <20260907-spi-sun4i-fixes-v2-0-7e805662b9bd@pengutronix.de> In-Reply-To: <20260907-spi-sun4i-fixes-v2-0-7e805662b9bd@pengutronix.de> To: Mark Brown , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard , Alexandru Gagniuc , Olliver Schinagl Cc: linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Mark Brown , kernel@pengutronix.de, Marc Kleine-Budde , Jonas Rebmann X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2965; i=jre@pengutronix.de; h=from:subject:message-id; bh=TyIg6fa906BvVGJmUbL2uFkFKtz0nx9DEAKb+ItgMx8=; b=owGbwMvMwCV2ZcYT3onnbjcwnlZLYsiad+NjfujlU9Xca7e9//dESvhjwtX8LhmWsFDdCv1m0 fZ9rm3XOkpZGMS4GGTFFFli1eQUhIz9r5tV2sXCzGFlAhnCwMUpABMpmMbwP3yD74O1ml7hrqzJ CoaeJ4VXMM/l+z+HfbHnWaf1grUdCxn+l1zYM1/zl6Khw6Nva2ZM1M5Vk+EOOV9Qv9agY8/Jo1v 1WQA= X-Developer-Key: i=jre@pengutronix.de; a=openpgp; fpr=0B7B750D5D3CD21B3B130DE8B61515E135CD49B5 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= From: Marc Kleine-Budde In commit 6d9fe44bd73d ("spi: sun4i: fix FIFO limit"), the TX FIFO is filled max to SUN4I_FIFO_DEPTH - 1 (= 63) bytes to work around timeouts observed on A10s SoCs. Commit 196737912da5 ("spi: sun4i: Allow transfers larger than FIFO size") added support for transfers larger than the FIFO size. This commit did not consider the A10 workaround (limit the TX FIFO fill size to SUN4I_FIFO_DEPTH - 1 (= 63) bytes) for refilling the TX FIFO in the IRQ handler. To apply the workaround independent from where sun4i_spi_fill_fifo() is called, remove the length argument from the function and directly take the max fill level of SUN4I_FIFO_DEPTH - 1 into account when calculating the free space in the FIFO. Due to the lack of HW this patch has not been tested on an A10 SoC, but on an A20 SoC. It was not possible to reproduce the timeout on the A20. Fixes: 196737912da5 ("spi: sun4i: Allow transfers larger than FIFO size") Signed-off-by: Marc Kleine-Budde Signed-off-by: Jonas Rebmann --- drivers/spi/spi-sun4i.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c index 2e2324453905..3649bcabcc9a 100644 --- a/drivers/spi/spi-sun4i.c +++ b/drivers/spi/spi-sun4i.c @@ -142,15 +142,21 @@ static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len) } } -static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len) +static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi) { u32 cnt; + int len; u8 byte; - /* See how much data we can fit */ - cnt = SUN4I_FIFO_DEPTH - sun4i_spi_get_tx_fifo_count(sspi); + /* + * See how much data we can fit + * + * Filling the FIFO fully causes timeout for some reason + * at least on spi2 on A10s + */ + cnt = SUN4I_FIFO_DEPTH - 1 - sun4i_spi_get_tx_fifo_count(sspi); - len = min3(len, (int)cnt, sspi->len); + len = min_t(int, cnt, sspi->len); while (len--) { byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; @@ -311,12 +317,8 @@ static int sun4i_spi_transfer_one(struct spi_controller *host, sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len)); sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len)); - /* - * Fill the TX FIFO - * Filling the FIFO fully causes timeout for some reason - * at least on spi2 on A10s - */ - sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1); + /* Fill the TX FIFO */ + sun4i_spi_fill_fifo(sspi); /* Enable the interrupts */ sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TC | @@ -373,7 +375,7 @@ static irqreturn_t sun4i_spi_handler(int irq, void *dev_id) /* Transmit FIFO 3/4 empty */ if (status & SUN4I_INT_CTL_TF_E34) { - sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH); + sun4i_spi_fill_fifo(sspi); if (!sspi->len) /* nothing left to transmit */