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(usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 44D413F86F; Thu, 17 Sep 2026 15:39:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789684785; bh=7PwcNklDq+/rSBxB6NyGSWTpTGQwENPQUKSvnXRLeaY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LbH9vLYAqfMhaX9JFjV8xQxygMe905mRBwjZX8wYbpLjBLATwOFRwpmKshyYhnDL1 xjZJyFioN1CKKM/DyM+7b0ckA4U842mLs1kTsEuUnTKm/rcqgGD+6iYCYQXzydW0zQ B4WC6tPb+Z5IVeE2dsebLYsKKS8WRzD+mU20Ukg0= From: Andre Przywara To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [PATCH v2 5/5] arm64: dts: allwinner: a523: add CPU clocks Date: Fri, 18 Sep 2026 00:39:13 +0200 Message-ID: <20260917223913.1855301-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260917223913.1855301-1-andre.przywara@arm.com> References: <20260917223913.1855301-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [4.84 / 15.00]; RBL_SENDERSCORE(2.00)[172.234.253.10:from]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; MAILLIST(-0.15)[generic]; BAD_REP_POLICIES(0.10)[]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; TAGGED_RCPT(0.00)[clk,dt]; FROM_HAS_DN(0.00)[]; PRECEDENCE_BULK(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; DBL_PROHIBIT(0.00)[0.108.172.80:email,0.0.0.100:email,0.0.0.200:email]; DBL_BLOCKED_OPENRESOLVER(0.00)[arm.com:email,arm.com:dkim,0.0.1.144:email,0.0.1.44:email,sea.lore.kernel.org:rdns,sea.lore.kernel.org:helo,0.0.0.0:email,0.0.2.88:email,0.134.137.104:email,0.0.2.188:email,0.0.1.244:email]; RCPT_COUNT_TWELVE(0.00)[13]; FORGED_SENDER_MAILLIST(0.00)[]; R_DKIM_ALLOW(0.00)[arm.com:s=foss]; FROM_NEQ_ENVFROM(0.00)[andre.przywara@arm.com,linux-sunxi@lists.linux.dev]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; DKIM_TRACE(0.00)[arm.com:+]; DMARC_POLICY_ALLOW(0.00)[arm.com,none]; R_SPF_ALLOW(0.00)[+ip4:172.234.253.10]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[100.90.174.1:received]; TO_DN_SOME(0.00)[]; RCVD_COUNT_FIVE(0.00)[6]; FREEMAIL_TO(0.00)[kernel.org,redhat.com,baylibre.com,gmail.com,sholland.org]; MIME_TRACE(0.00)[0:+]; TAGGED_FROM(0.00)[bounces-26026-noreply=patchwork.local]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; RCVD_TLS_LAST(0.00)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.234.253.10:from] X-Rspamd-Queue-Id: 9A1001C1406 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The Allwinner A523 family of SoCs feature a separate clock unit for the CPU PLLs and muxes, including one for the DSU interconnect. Add a DT node for the CPU clock controller, and list all the clocks from the other CCUs that this controller needs. Also list the clock source for each CPU: there is one clock for each cluster of four cores, suffixed L and B, for little and big (although all cores are of the same Cortex-A55 type). Signed-off-by: Andre Przywara --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index 85ef492ffeae7..29af21372aba2 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -25,6 +26,7 @@ cpu0: cpu@0 { compatible = "arm,cortex-a55"; device_type = "cpu"; reg = <0x000>; + clocks = <&cpu_ccu CLK_CPU_L>; enable-method = "psci"; }; @@ -32,6 +34,7 @@ cpu1: cpu@100 { compatible = "arm,cortex-a55"; device_type = "cpu"; reg = <0x100>; + clocks = <&cpu_ccu CLK_CPU_L>; enable-method = "psci"; }; @@ -39,6 +42,7 @@ cpu2: cpu@200 { compatible = "arm,cortex-a55"; device_type = "cpu"; reg = <0x200>; + clocks = <&cpu_ccu CLK_CPU_L>; enable-method = "psci"; }; @@ -46,6 +50,7 @@ cpu3: cpu@300 { compatible = "arm,cortex-a55"; device_type = "cpu"; reg = <0x300>; + clocks = <&cpu_ccu CLK_CPU_L>; enable-method = "psci"; }; @@ -53,6 +58,7 @@ cpu4: cpu@400 { compatible = "arm,cortex-a55"; device_type = "cpu"; reg = <0x400>; + clocks = <&cpu_ccu CLK_CPU_B>; enable-method = "psci"; }; @@ -60,6 +66,7 @@ cpu5: cpu@500 { compatible = "arm,cortex-a55"; device_type = "cpu"; reg = <0x500>; + clocks = <&cpu_ccu CLK_CPU_B>; enable-method = "psci"; }; @@ -67,6 +74,7 @@ cpu6: cpu@600 { compatible = "arm,cortex-a55"; device_type = "cpu"; reg = <0x600>; + clocks = <&cpu_ccu CLK_CPU_B>; enable-method = "psci"; }; @@ -74,6 +82,7 @@ cpu7: cpu@700 { compatible = "arm,cortex-a55"; device_type = "cpu"; reg = <0x700>; + clocks = <&cpu_ccu CLK_CPU_B>; enable-method = "psci"; }; }; @@ -1144,5 +1153,18 @@ npu: npu@7122000 { resets = <&mcu_ccu RST_BUS_MCU_NPU>; power-domains = <&ppu PD_NPU>; }; + + cpu_ccu: clock-controller@8817000 { + compatible = "allwinner,sun55i-a523-cpu-ccu"; + reg = <0x08817000 0x80>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, <&ccu CLK_PLL_PERIPH0_2X>, + <&ccu CLK_PLL_PERIPH0_600M>; + clock-names = "hosc", "losc", + "iosc", "pll-periph0-2x", + "pll-periph0-600M"; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; };