From patchwork Mon Sep 21 15:38:00 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junhui Liu X-Patchwork-Id: 3399 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sin.lore.kernel.org (sin.lore.kernel.org [104.64.211.4]) by mxe881.netcup.net (Postfix) with ESMTPS id 381011C0311 for ; Mon, 21 Sep 2026 19:05:31 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=pigmoral.tech; spf=pass (sender IP is 104.64.211.4) smtp.mailfrom=linux-sunxi+bounces-26081-noreply=patchwork.local@lists.linux.dev smtp.helo=sin.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 104.64.211.4 as permitted sender) client-ip=104.64.211.4; envelope-from=linux-sunxi+bounces-26081-noreply=patchwork.local@lists.linux.dev; helo=sin.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sin.lore.kernel.org (Postfix) with ESMTP id 7098787906 for ; Mon, 21 Sep 2026 15:42:34 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4BE034D17A9; Mon, 21 Sep 2026 15:39:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="fpYtcEeH" X-Original-To: linux-sunxi@lists.linux.dev Received: from sender5-op-o15.zoho.com (sender5-op-o15.zoho.com [165.173.182.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E88A54CE691 for ; Mon, 21 Sep 2026 15:39:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=165.173.182.15 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790005186; cv=pass; b=pZm7TWPFe6L2QpkEhCpUYbkugBgFM2opO58r65Yh7M29RTgWb4pmr1nUWjrunopPuuDmUrWZX8cikD84btMKyP2Y5qdUMkaHRCxR9YFIbQUeZQ7zIvR5uFsKtAvXriiV7KHlpX10ucs2NvTOyd5x14z0mD88h6p1yyMR2LbxA58= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790005186; c=relaxed/simple; bh=VJaKDsY2wNXh9jcfEAVgeUkR8XziO8+1SsD0dyIaS04=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UJ7YhSo6D8EniX3cjy32gMNudoZB3v/od0Czqw+7NuMPaUJiGIHrTTCCtvowOBN8mpybEzLWgdMa7uCV6XSFpb1M1Tnkm6uACmE/rdP9cZCuCVD4/quhwRNcWyGGYMviHfJzBnq+bXBX10EjFrPGwtUjCsAIjD4ygmVJTdiKqss= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=fpYtcEeH; arc=pass smtp.client-ip=165.173.182.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech ARC-Seal: i=1; a=rsa-sha256; t=1790005161; cv=none; d=zohomail.com; s=zohoarc; b=dWnl/bhd59hbNrjXwloKhgHkDU70R2IFLrEGeQbRp+Ya8BSnFuioyK4lZ3gM49x45f68I2JbctY1tf0Nl0sg5wYrPeTUSyN6w2ljSlnLztfGLeNVg7twgNqlA9LkkYT06Qbmy/c7dsDmNiebnIcsVVKLqb2/Zm6u1ijHwBaSe7g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790005161; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:Subject:Subject:To:To:Message-Id:Reply-To; bh=GyqoFNSanEeBxdsQdbMl1XUDGrCiYm9GRKaNInNkFHs=; b=JKuYVKlglZAsfDc6wkKazi8JvMl5gbqMhGkk3p4Ya8YdS7DvhWD346hlF8xNuTfSJx4UceVsTZj+NHI5TS+2TDW4w2oJbjgL++7FYvevl7VNIpcmJdmo/uEHAEXSRnbVCbnPXFVPwfJqM9FbANAKWXFIHSUzOMFQoXFvS2ZaQFA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1790005161; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=GyqoFNSanEeBxdsQdbMl1XUDGrCiYm9GRKaNInNkFHs=; b=fpYtcEeHGUwSp/jOJ4aAP/3PJ2KSzPRT8ZIhwTuSYFfLe5n+u8aXDI94jqIPNX8a vABFzUzxpijELHM5WMfIqMsKJbhdyonm5WFW694di2mahFyJsSm83tCTqjtVgNNV9v+ IVN28+szHg3e40nixrbWv3qPjpmiKfsWkW/XFRYI= Received: by smtp.zohomail.com with SMTPS id 1790005158049450.6589859179186; Mon, 21 Sep 2026 08:39:18 -0700 (PDT) From: Junhui Liu Date: Mon, 21 Sep 2026 23:38:00 +0800 Subject: [PATCH v4 2/8] clk: sunxi-ng: sdm: Add dual patterns support Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260921-a733-clk-v4-2-9c184ebe9ac1@pigmoral.tech> References: <20260921-a733-clk-v4-0-9c184ebe9ac1@pigmoral.tech> In-Reply-To: <20260921-a733-clk-v4-0-9c184ebe9ac1@pigmoral.tech> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org, Jerome Brunet , Enzo Adriano , Andre Przywara X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5946; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=VJaKDsY2wNXh9jcfEAVgeUkR8XziO8+1SsD0dyIaS04=; b=owGbwMvMwCWWvDb1VEXc8j+Mp9WSGLI2+udf9Njw0GvmhleVb/S/OZ379+Zh4Yxlz7dXGl91T T9vWxJyrqOUhUGMi0FWTJGFy1/8n7UOz7cjAq33YeawMoEMYeDiFICJ1Now/GbVs7n3cr/3nB6e hpRfDq0qTw7sS2D5aiZ8ovPD023bL2QzMswNdfDKEukzPbQg9cUTdy6ZmzrX5BmYP39W+j79grP 0Km4A X-Developer-Key: i=junhui.liu@pigmoral.tech; a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-2.16 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[104.64.211.4:from]; SUSPICIOUS_RECIPS(1.50)[]; MAILLIST(-0.15)[generic]; MIME_GOOD(-0.10)[text/plain]; BAD_REP_POLICIES(0.10)[]; HAS_LIST_UNSUB(-0.01)[]; RCPT_COUNT_TWELVE(0.00)[26]; TAGGED_RCPT(0.00)[clk,dt]; PRECEDENCE_BULK(0.00)[]; FORGED_SENDER_MAILLIST(0.00)[]; DMARC_NA(0.00)[pigmoral.tech]; FREEMAIL_CC(0.00)[vger.kernel.org,lists.infradead.org,lists.linux.dev,baylibre.com,gmail.com,arm.com]; DBL_BLOCKED_OPENRESOLVER(0.00)[pigmoral.tech:email,pigmoral.tech:dkim,baylibre.com:email,sin.lore.kernel.org:rdns,sin.lore.kernel.org:helo]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=2]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[100.90.174.1:received]; FROM_HAS_DN(0.00)[]; R_DKIM_ALLOW(0.00)[pigmoral.tech:s=zmail]; FREEMAIL_TO(0.00)[kernel.org,redhat.com,baylibre.com,gmail.com,sholland.org,pengutronix.de,pigmoral.tech,dabbelt.com,eecs.berkeley.edu,ghiti.fr]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; DKIM_TRACE(0.00)[pigmoral.tech:+]; TO_DN_SOME(0.00)[]; R_SPF_ALLOW(0.00)[+ip4:104.64.211.4]; RCVD_COUNT_FIVE(0.00)[5]; MIME_TRACE(0.00)[0:+]; MID_RHS_MATCH_FROM(0.00)[]; FROM_NEQ_ENVFROM(0.00)[junhui.liu@pigmoral.tech,linux-sunxi@lists.linux.dev]; RCVD_TLS_LAST(0.00)[]; ASN(0.00)[asn:63949, ipnet:104.64.192.0/19, country:SG]; TAGGED_FROM(0.00)[bounces-26081-noreply=patchwork.local]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[104.64.211.4:from] X-Rspamd-Queue-Id: 381011C0311 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= On newer Allwinner platforms like the A733, the Sigma-Delta Modulation (SDM) control logic is more complex. The SDM enable bit, which was previously located in the PLL register, is now moved to a second pattern register (PATTERN1). To support this, rename the existing "tuning" members to "pattern0" to align with the datasheet, and introduce the _SUNXI_CCU_SDM_DUAL_PAT macro to provide pattern1 register support. Related operations are also updated. Tested-by: Jerome Brunet Signed-off-by: Junhui Liu Reviewed-by: Chen-Yu Tsai --- drivers/clk/sunxi-ng/ccu_sdm.c | 52 ++++++++++++++++++++++++++++++------------ drivers/clk/sunxi-ng/ccu_sdm.h | 29 ++++++++++++++--------- 2 files changed, 55 insertions(+), 26 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu_sdm.c b/drivers/clk/sunxi-ng/ccu_sdm.c index c564e5f9e610..7e13ffd246d3 100644 --- a/drivers/clk/sunxi-ng/ccu_sdm.c +++ b/drivers/clk/sunxi-ng/ccu_sdm.c @@ -18,7 +18,11 @@ bool ccu_sdm_helper_is_enabled(struct ccu_common *common, if (sdm->enable && !(readl(common->base + common->reg) & sdm->enable)) return false; - return !!(readl(common->base + sdm->tuning_reg) & sdm->tuning_enable); + if (sdm->pat1_enable && + (readl(common->base + sdm->pat1_reg) & sdm->pat1_enable) != sdm->pat1_enable) + return false; + + return !!(readl(common->base + sdm->pat0_reg) & sdm->pat0_enable); } EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_is_enabled, "SUNXI_CCU"); @@ -37,18 +41,27 @@ void ccu_sdm_helper_enable(struct ccu_common *common, for (i = 0; i < sdm->table_size; i++) if (sdm->table[i].rate == rate) writel(sdm->table[i].pattern, - common->base + sdm->tuning_reg); + common->base + sdm->pat0_reg); /* Make sure SDM is enabled */ spin_lock_irqsave(common->lock, flags); - reg = readl(common->base + sdm->tuning_reg); - writel(reg | sdm->tuning_enable, common->base + sdm->tuning_reg); + reg = readl(common->base + sdm->pat0_reg); + writel(reg | sdm->pat0_enable, common->base + sdm->pat0_reg); spin_unlock_irqrestore(common->lock, flags); - spin_lock_irqsave(common->lock, flags); - reg = readl(common->base + common->reg); - writel(reg | sdm->enable, common->base + common->reg); - spin_unlock_irqrestore(common->lock, flags); + if (sdm->enable) { + spin_lock_irqsave(common->lock, flags); + reg = readl(common->base + common->reg); + writel(reg | sdm->enable, common->base + common->reg); + spin_unlock_irqrestore(common->lock, flags); + } + + if (sdm->pat1_enable) { + spin_lock_irqsave(common->lock, flags); + reg = readl(common->base + sdm->pat1_reg); + writel(reg | sdm->pat1_enable, common->base + sdm->pat1_reg); + spin_unlock_irqrestore(common->lock, flags); + } } EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_enable, "SUNXI_CCU"); @@ -61,14 +74,23 @@ void ccu_sdm_helper_disable(struct ccu_common *common, if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD)) return; - spin_lock_irqsave(common->lock, flags); - reg = readl(common->base + common->reg); - writel(reg & ~sdm->enable, common->base + common->reg); - spin_unlock_irqrestore(common->lock, flags); + if (sdm->enable) { + spin_lock_irqsave(common->lock, flags); + reg = readl(common->base + common->reg); + writel(reg & ~sdm->enable, common->base + common->reg); + spin_unlock_irqrestore(common->lock, flags); + } + + if (sdm->pat1_enable) { + spin_lock_irqsave(common->lock, flags); + reg = readl(common->base + sdm->pat1_reg); + writel(reg & ~sdm->pat1_enable, common->base + sdm->pat1_reg); + spin_unlock_irqrestore(common->lock, flags); + } spin_lock_irqsave(common->lock, flags); - reg = readl(common->base + sdm->tuning_reg); - writel(reg & ~sdm->tuning_enable, common->base + sdm->tuning_reg); + reg = readl(common->base + sdm->pat0_reg); + writel(reg & ~sdm->pat0_enable, common->base + sdm->pat0_reg); spin_unlock_irqrestore(common->lock, flags); } EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_disable, "SUNXI_CCU"); @@ -123,7 +145,7 @@ unsigned long ccu_sdm_helper_read_rate(struct ccu_common *common, pr_debug("%s: clock is sigma-delta modulated\n", clk_hw_get_name(&common->hw)); - reg = readl(common->base + sdm->tuning_reg); + reg = readl(common->base + sdm->pat0_reg); pr_debug("%s: pattern reg is 0x%x", clk_hw_get_name(&common->hw), reg); diff --git a/drivers/clk/sunxi-ng/ccu_sdm.h b/drivers/clk/sunxi-ng/ccu_sdm.h index c1a7159b89c3..e94cef141c7d 100644 --- a/drivers/clk/sunxi-ng/ccu_sdm.h +++ b/drivers/clk/sunxi-ng/ccu_sdm.h @@ -33,21 +33,28 @@ struct ccu_sdm_internal { u32 table_size; /* early SoCs don't have the SDM enable bit in the PLL register */ u32 enable; - /* second enable bit in tuning register */ - u32 tuning_enable; - u16 tuning_reg; + /* second enable bit in pattern0 register */ + u32 pat0_enable; + u16 pat0_reg; + /* on some platforms, the sdm enable bit in pattern1 register */ + u32 pat1_enable; + u16 pat1_reg; }; -#define _SUNXI_CCU_SDM(_table, _enable, \ - _reg, _reg_enable) \ - { \ - .table = _table, \ - .table_size = ARRAY_SIZE(_table), \ - .enable = _enable, \ - .tuning_enable = _reg_enable, \ - .tuning_reg = _reg, \ +#define _SUNXI_CCU_SDM_DUAL_PAT(_table, _enable, _pat0, _pat0_enable, _pat1, _pat1_enable) \ + { \ + .table = _table, \ + .table_size = ARRAY_SIZE(_table), \ + .enable = _enable, \ + .pat0_enable = _pat0_enable, \ + .pat0_reg = _pat0, \ + .pat1_enable = _pat1_enable, \ + .pat1_reg = _pat1, \ } +#define _SUNXI_CCU_SDM(_table, _enable, _pat0, _pat0_enable) \ + _SUNXI_CCU_SDM_DUAL_PAT(_table, _enable, _pat0, _pat0_enable, 0, 0) + bool ccu_sdm_helper_is_enabled(struct ccu_common *common, struct ccu_sdm_internal *sdm); void ccu_sdm_helper_enable(struct ccu_common *common,