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DKIM_TRACE(0.00)[qualcomm.com:+]; FREEMAIL_TO(0.00)[kernel.org,lunn.ch,davemloft.net,google.com,redhat.com,gmail.com,foss.st.com,st.com,linaro.org,baylibre.com,oss.nxp.com,nxp.com,oss.qualcomm.com,bootlin.com,glider.be,rendec.net]; RCVD_TLS_LAST(0.00)[]; DMARC_POLICY_ALLOW(0.00)[qualcomm.com,reject]; MIME_TRACE(0.00)[0:+]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.232.135.74:from] X-Rspamd-Queue-Id: DE0311C1959 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Implement support for the firmware-managed SGMII/SerDes PHY present on Qualcomm platforms. Do this as a separate driver from the HLOS-managed variant as they don't share almost any code. Signed-off-by: Bartosz Golaszewski --- drivers/phy/qualcomm/Kconfig | 10 +++ drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-sgmii-eth-scmi.c | 117 +++++++++++++++++++++++++ 3 files changed, 128 insertions(+) diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index d910a5d1a1ac3ad77599e72c3f4a3b2aebd02dbf..915859ffc95b58504cb3671e8a3d866d9b305c9e 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -242,3 +242,13 @@ config PHY_QCOM_SGMII_ETH help Enable this to support the internal SerDes/SGMII PHY on various Qualcomm chipsets. + +config PHY_QCOM_SGMII_ETH_SCMI + tristate "Qualcomm DWMAC SGMII SerDes/PHY driver (firmware managed)" + depends on OF && (ARCH_QCOM || COMPILE_TEST) + depends on PM_GENERIC_DOMAINS + select GENERIC_PHY + help + Enable this to support the internal SerDes/SGMII PHY on Qualcomm + chipsets where the SerDes hardware (clocks and registers) is owned + by the firmware. diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index 8bf887d58ee4a65687216dd91a6592da7941ace2..4972009b217e39ad3d19300e5b7dede4e88feca4 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -26,3 +26,4 @@ obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2)+= phy-qcom-snps-femto-v2.o obj-$(CONFIG_PHY_QCOM_IPQ806X_USB) += phy-qcom-ipq806x-usb.o obj-$(CONFIG_PHY_QCOM_SGMII_ETH) += phy-qcom-sgmii-eth.o +obj-$(CONFIG_PHY_QCOM_SGMII_ETH_SCMI) += phy-qcom-sgmii-eth-scmi.o diff --git a/drivers/phy/qualcomm/phy-qcom-sgmii-eth-scmi.c b/drivers/phy/qualcomm/phy-qcom-sgmii-eth-scmi.c new file mode 100644 index 0000000000000000000000000000000000000000..c726a414eb6a41fe6937b0c73ed5cfe3bd0115cd --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-sgmii-eth-scmi.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Firmware-managed variant of the Qualcomm DWMAC SGMII SerDes/PHY driver. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int qcom_dwmac_sgmii_phy_scmi_validate(struct phy *phy, enum phy_mode mode, + int submode, + union phy_configure_opts *opts) +{ + if (mode != PHY_MODE_ETHERNET) + return -EINVAL; + + switch (submode) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + return 0; + default: + return -EINVAL; + } +} + +static int qcom_dwmac_sgmii_phy_scmi_set_mode(struct phy *phy, enum phy_mode mode, + int submode) +{ + struct device *dev = phy->dev.parent; + unsigned int perf_state; + int ret; + + ret = qcom_dwmac_sgmii_phy_scmi_validate(phy, mode, submode, NULL); + if (ret) + return ret; + + perf_state = (submode == PHY_INTERFACE_MODE_2500BASEX) ? + SPEED_2500 : SPEED_1000; + + return dev_pm_genpd_set_performance_state(dev, perf_state); +} + +static const struct phy_ops qcom_dwmac_sgmii_phy_scmi_ops = { + .set_mode = qcom_dwmac_sgmii_phy_scmi_set_mode, + .validate = qcom_dwmac_sgmii_phy_scmi_validate, + .owner = THIS_MODULE, +}; + +static void qcom_dwmac_sgmii_phy_scmi_reset_perf_state(void *data) +{ + struct device *dev = data; + + dev_pm_genpd_set_performance_state(dev, 0); +} + +static int qcom_dwmac_sgmii_phy_scmi_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy_provider *provider; + struct phy *phy; + int ret; + + ret = devm_add_action_or_reset(dev, qcom_dwmac_sgmii_phy_scmi_reset_perf_state, dev); + if (ret) + return ret; + + /* + * Enable runtime PM on the provider before creating the PHY so that the + * PHY core enables runtime PM on the PHY device too. The single SCMI + * power domain has already been attached to this device by the driver + * core, so runtime PM votes propagate to firmware through the genpd + * device link. No register or clock access is done here - firmware owns + * the SerDes. + */ + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + + phy = devm_phy_create(dev, NULL, &qcom_dwmac_sgmii_phy_scmi_ops); + if (IS_ERR(phy)) + return dev_err_probe(dev, PTR_ERR(phy), "failed to create the phy\n"); + + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(provider)) + return dev_err_probe(dev, PTR_ERR(provider), + "failed to register the PHY provider\n"); + + return 0; +} + +static const struct of_device_id qcom_dwmac_sgmii_phy_scmi_of_match[] = { + { .compatible = "qcom,sa8255p-dwmac-sgmii-phy" }, + { } +}; +MODULE_DEVICE_TABLE(of, qcom_dwmac_sgmii_phy_scmi_of_match); + +static struct platform_driver qcom_dwmac_sgmii_phy_scmi_driver = { + .probe = qcom_dwmac_sgmii_phy_scmi_probe, + .driver = { + .name = "qcom-dwmac-sgmii-phy-scmi", + .of_match_table = qcom_dwmac_sgmii_phy_scmi_of_match, + }, +}; +module_platform_driver(qcom_dwmac_sgmii_phy_scmi_driver); + +MODULE_DESCRIPTION("Qualcomm DWMAC SGMII PHY driver (firmware managed)"); +MODULE_AUTHOR("Bartosz Golaszewski "); +MODULE_LICENSE("GPL");