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Signed-off-by: Bartosz Golaszewski --- .../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 99 +++++++++++++++------- 1 file changed, 68 insertions(+), 31 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index ab1bcb7eb18e22f01556c190f7d8cd8eeba4d0c9..509a5368e69a8fa440bf3b4f58f7b09a683558f3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include @@ -81,6 +82,8 @@ #define SGMII_10M_RX_CLK_DVDR 0x31 +struct qcom_ethqos; + struct ethqos_emac_por { unsigned int offset; unsigned int value; @@ -95,6 +98,8 @@ struct ethqos_emac_driver_data { const char *link_clk_name; struct dwmac4_addrs dwmac4_addrs; bool needs_sgmii_loopback; + int (*setup)(struct qcom_ethqos *ethqos, + struct plat_stmmacenet_data *plat_dat); }; struct qcom_ethqos { @@ -200,6 +205,9 @@ static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos) rgmii_setmask(ethqos, RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG); } +static int ethqos_hlos_setup(struct qcom_ethqos *ethqos, + struct plat_stmmacenet_data *plat_dat); + static const struct ethqos_emac_por emac_v2_3_0_por[] = { { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 }, { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C }, @@ -214,6 +222,7 @@ static const struct ethqos_emac_driver_data emac_v2_3_0_data = { .num_rgmii_por = ARRAY_SIZE(emac_v2_3_0_por), .rgmii_config_loopback_en = true, .has_emac_ge_3 = false, + .setup = ethqos_hlos_setup, }; static const struct ethqos_emac_por emac_v2_1_0_por[] = { @@ -230,6 +239,7 @@ static const struct ethqos_emac_driver_data emac_v2_1_0_data = { .num_rgmii_por = ARRAY_SIZE(emac_v2_1_0_por), .rgmii_config_loopback_en = false, .has_emac_ge_3 = false, + .setup = ethqos_hlos_setup, }; static const struct ethqos_emac_por emac_v3_0_0_por[] = { @@ -262,6 +272,7 @@ static const struct ethqos_emac_driver_data emac_v3_0_0_data = { .mtl_low_cred = 0x00008024, .mtl_low_cred_offset = 0x1000, }, + .setup = ethqos_hlos_setup, }; static const struct ethqos_emac_por emac_v4_0_0_por[] = { @@ -297,6 +308,7 @@ static const struct ethqos_emac_driver_data emac_v4_0_0_data = { .mtl_low_cred = 0x00008024, .mtl_low_cred_offset = 0x1000, }, + .setup = ethqos_hlos_setup, }; static int ethqos_dll_configure(struct qcom_ethqos *ethqos) @@ -692,6 +704,58 @@ static void ethqos_ptp_clk_freq_config(struct stmmac_priv *priv) netdev_dbg(priv->dev, "PTP rate %lu\n", plat_dat->clk_ptp_rate); } +static int ethqos_hlos_setup(struct qcom_ethqos *ethqos, + struct plat_stmmacenet_data *plat_dat) +{ + struct platform_device *pdev = ethqos->pdev; + struct device *dev = &pdev->dev; + int ret; + + ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii"); + if (IS_ERR(ethqos->rgmii_base)) + return dev_err_probe(dev, PTR_ERR(ethqos->rgmii_base), + "Failed to map rgmii resource\n"); + + ethqos->link_clk = devm_clk_get(dev, ethqos->data->link_clk_name ?: "rgmii"); + if (IS_ERR(ethqos->link_clk)) + return dev_err_probe(dev, PTR_ERR(ethqos->link_clk), + "Failed to get link_clk\n"); + + plat_dat->clks_config = ethqos_clks_config; + + ret = ethqos_clks_config(ethqos, true); + if (ret) + return ret; + + ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos); + if (ret) + return ret; + + ethqos_set_clk_tx_rate(ethqos, NULL, plat_dat->phy_interface, SPEED_1000); + qcom_ethqos_set_sgmii_loopback(ethqos, true); + ethqos_set_func_clk_en(ethqos); + + switch (ethqos->phy_mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + plat_dat->fix_mac_speed = ethqos_fix_mac_speed_rgmii; + break; + case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_SGMII: + plat_dat->fix_mac_speed = ethqos_fix_mac_speed_sgmii; + break; + default: + break; + } + + plat_dat->set_clk_tx_rate = ethqos_set_clk_tx_rate; + plat_dat->dump_debug_regs = rgmii_dump; + + return 0; +} + static int qcom_ethqos_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -713,23 +777,20 @@ static int qcom_ethqos_probe(struct platform_device *pdev) "dt configuration failed\n"); } - plat_dat->clks_config = ethqos_clks_config; - ethqos = devm_kzalloc(dev, sizeof(*ethqos), GFP_KERNEL); if (!ethqos) return -ENOMEM; ethqos->phy_mode = plat_dat->phy_interface; + switch (ethqos->phy_mode) { case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_TXID: - plat_dat->fix_mac_speed = ethqos_fix_mac_speed_rgmii; break; case PHY_INTERFACE_MODE_2500BASEX: case PHY_INTERFACE_MODE_SGMII: - plat_dat->fix_mac_speed = ethqos_fix_mac_speed_sgmii; plat_dat->mac_finish = ethqos_mac_finish_serdes; break; default: @@ -739,24 +800,13 @@ static int qcom_ethqos_probe(struct platform_device *pdev) } ethqos->pdev = pdev; - ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii"); - if (IS_ERR(ethqos->rgmii_base)) - return dev_err_probe(dev, PTR_ERR(ethqos->rgmii_base), - "Failed to map rgmii resource\n"); - data = of_device_get_match_data(dev); ethqos->data = data; - ethqos->link_clk = devm_clk_get(dev, data->link_clk_name ?: "rgmii"); - if (IS_ERR(ethqos->link_clk)) - return dev_err_probe(dev, PTR_ERR(ethqos->link_clk), - "Failed to get link_clk\n"); - - ret = ethqos_clks_config(ethqos, true); - if (ret) - return ret; + if (WARN_ON(!data->setup)) + return -EINVAL; - ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos); + ret = data->setup(ethqos, plat_dat); if (ret) return ret; @@ -765,21 +815,8 @@ static int qcom_ethqos_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(ethqos->serdes_phy), "Failed to get serdes phy\n"); - ethqos_set_clk_tx_rate(ethqos, NULL, plat_dat->phy_interface, - SPEED_1000); - - qcom_ethqos_set_sgmii_loopback(ethqos, true); - ethqos_set_func_clk_en(ethqos); - - /* The clocks are controlled by firmware, so we don't know for certain - * what clock rate is being used. Hardware documentation mentions that - * the AHB slave clock will be in the range of 50 to 100MHz, which - * equates to a MDC between 1.19 and 2.38MHz. - */ plat_dat->clk_csr = STMMAC_CSR_60_100M; plat_dat->bsp_priv = ethqos; - plat_dat->set_clk_tx_rate = ethqos_set_clk_tx_rate; - plat_dat->dump_debug_regs = rgmii_dump; plat_dat->ptp_clk_freq_config = ethqos_ptp_clk_freq_config; plat_dat->core_type = DWMAC_CORE_GMAC4; if (data->has_emac_ge_3)