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Unlike the previously supported variants, this one's power management is done in the firmware over SCMI. This is modeled in linux using power domains so add a new emac data variant and a separate setup callback. Signed-off-by: Bartosz Golaszewski --- .../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 107 +++++++++++++++++++++ 1 file changed, 107 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index 509a5368e69a8fa440bf3b4f58f7b09a683558f3..3d4bc950a72ac0d0d9515bf9148e865463ddc0a3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -98,6 +98,11 @@ struct ethqos_emac_driver_data { const char *link_clk_name; struct dwmac4_addrs dwmac4_addrs; bool needs_sgmii_loopback; + /* Fixed PTP reference clock rate, used on SCMI platforms where + * firmware does not implement the clock protocol allowing linux to + * query it. + */ + unsigned long ptp_clk_rate; int (*setup)(struct qcom_ethqos *ethqos, struct plat_stmmacenet_data *plat_dat); }; @@ -108,6 +113,7 @@ struct qcom_ethqos { struct clk *link_clk; struct phy *serdes_phy; phy_interface_t phy_mode; + struct dev_pm_domain_list *pds; const struct ethqos_emac_driver_data *data; }; @@ -207,6 +213,8 @@ static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos) static int ethqos_hlos_setup(struct qcom_ethqos *ethqos, struct plat_stmmacenet_data *plat_dat); +static int ethqos_scmi_setup(struct qcom_ethqos *ethqos, + struct plat_stmmacenet_data *plat_dat); static const struct ethqos_emac_por emac_v2_3_0_por[] = { { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 }, @@ -311,6 +319,30 @@ static const struct ethqos_emac_driver_data emac_v4_0_0_data = { .setup = ethqos_hlos_setup, }; +static const struct ethqos_emac_driver_data emac_v4_0_0_scmi_data = { + .has_emac_ge_3 = true, + .needs_sgmii_loopback = true, + .dma_addr_width = 36, + .ptp_clk_rate = 230400000, + .dwmac4_addrs = { + .dma_chan = 0x00008100, + .dma_chan_offset = 0x1000, + .mtl_chan = 0x00008000, + .mtl_chan_offset = 0x1000, + .mtl_ets_ctrl = 0x00008010, + .mtl_ets_ctrl_offset = 0x1000, + .mtl_txq_weight = 0x00008018, + .mtl_txq_weight_offset = 0x1000, + .mtl_send_slp_cred = 0x0000801c, + .mtl_send_slp_cred_offset = 0x1000, + .mtl_high_cred = 0x00008020, + .mtl_high_cred_offset = 0x1000, + .mtl_low_cred = 0x00008024, + .mtl_low_cred_offset = 0x1000, + }, + .setup = ethqos_scmi_setup, +}; + static int ethqos_dll_configure(struct qcom_ethqos *ethqos) { struct device *dev = ðqos->pdev->dev; @@ -756,6 +788,80 @@ static int ethqos_hlos_setup(struct qcom_ethqos *ethqos, return 0; } +static const char *const ethqos_scmi_pd_names[] = { "core", "mdio" }; + +static int ethqos_scmi_setup(struct qcom_ethqos *ethqos, + struct plat_stmmacenet_data *plat_dat) +{ + const struct dev_pm_domain_attach_data pd_data = { + .pd_names = ethqos_scmi_pd_names, + .num_pd_names = ARRAY_SIZE(ethqos_scmi_pd_names), + .pd_flags = PD_FLAG_DEV_LINK_ON, + }; + + struct platform_device *pdev = ethqos->pdev; + struct device *dev = &pdev->dev; + int ret; + + ret = devm_pm_domain_attach_list(dev, &pd_data, ðqos->pds); + if (ret < 0) + return dev_err_probe(dev, ret, + "Failed to attach power domains\n"); + + /* + * The SerDes lane, its clocks and the MAC AXI/AHB clocks are owned by + * firmware and brought up through the SCMI power domains above. The + * MAC wrapper itself, however is in the kernel's register space: the + * wrapper bit that loops the PHY TX clock into the MAC's clk_rx_i - + * needed because no recovered RX clock exists yet - is not + * configured by firmware. Without it, clk_rx_i never toggles and the + * DMA SW-reset polled in dwmac4_dma_reset() never completes. + * + * Map the wrapper and program the same loopback/functional clock bits + * the non-firmware platforms rely on (see ethqos_clks_config) so the + * RX clock is present by the time the DMA engine is reset. + */ + ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii"); + if (IS_ERR(ethqos->rgmii_base)) + return dev_err_probe(dev, PTR_ERR(ethqos->rgmii_base), + "Failed to map rgmii resource\n"); + + /* + * Register clks_config to run on every subsequent runtime resume, + * which stmmac performs after the power domains are on but before + * serdes_powerup() and the DMA reset. This alone isn't enough for + * the very first reset done from stmmac_open(), though: probe() + * fakes the device into RPM_ACTIVE without invoking the resume + * callback, so whether clks_config() has run by then depends on + * whether the device has already gone through one real suspend/resume + * cycle in the meantime. Call it here explicitly so the wrapper is + * always configured before the first DMA reset regardless of that + * timing. + */ + plat_dat->clks_config = ethqos_clks_config; + + ret = ethqos_clks_config(ethqos, true); + if (ret) + return ret; + + ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos); + if (ret) + return ret; + + plat_dat->clk_ptp_rate = ethqos->data->ptp_clk_rate; + + switch (ethqos->phy_mode) { + case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_SGMII: + plat_dat->fix_mac_speed = ethqos_fix_mac_speed_sgmii; + break; + default: + break; + } + + return 0; +} + static int qcom_ethqos_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -843,6 +949,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev) static const struct of_device_id qcom_ethqos_match[] = { { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data}, + { .compatible = "qcom,sa8255p-ethqos", .data = &emac_v4_0_0_scmi_data}, { .compatible = "qcom,sa8775p-ethqos", .data = &emac_v4_0_0_data}, { .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data}, { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data},