From patchwork Fri Aug 21 08:53:42 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 3041 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 3B1421C056C for ; Fri, 21 Aug 2026 11:32:21 +0200 (CEST) Authentication-Results: mxe881; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-25276-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; envelope-from=linux-sunxi+bounces-25276-noreply=patchwork.local@lists.linux.dev; helo=sea.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sea.lore.kernel.org (Postfix) with ESMTP id 432C332E14AA for ; Fri, 21 Aug 2026 09:03:55 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 574AB46D2AC; Fri, 21 Aug 2026 09:02:45 +0000 (UTC) X-Original-To: linux-sunxi@lists.linux.dev Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35A6E3CF680; Fri, 21 Aug 2026 09:02:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787302963; cv=none; b=ik5XYX0jnDe0QQZ9VWjiUToxJWTw+O3e7O3hfZiCNVkqJ+AMfESmeeqiN4MoD3qU0B4AL7r+fguJTGAuYhbQ++sY2e8wBgp56KG0GZmLkaOpXsURJuJxshS+gosh4EFqlRjb4jVfVe15ZquTopujp9rZnlLnchppPU8sonqi1ag= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787302963; c=relaxed/simple; bh=hkuwbAfuTx68NodqaDMZbswYScgLXtNCq4mND9danAs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mwVxF/omxCiumIOSxk8ZjxsOgNC+GIXSUi3mdoPrkr+HdeWUAKua4UYvNL3HWlLuSrC1qoT9YsxLC+9pYcTg7z/cmlRWUHDsZQCjn3QFFXTFLOwsoQY+Jt8yjOgyy+xMMb62xxVaP2EW+kYepsTDhvLReu+RyX3mWw3bfSamDxs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7315D1F000E9; Fri, 21 Aug 2026 09:02:14 +0000 (UTC) From: Geert Uytterhoeven To: Ryan Chen , Joel Stanley , Stephen Boyd , Brian Masney , Jerome Brunet , Andrew Jeffery , Billy Tsai , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Ray Jui , Scott Branden , Broadcom internal kernel review list , Taichi Sugaya , Takao Orito , Linus Walleij , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Sudeep Holla , Cristian Marussi , David Lechner , Abel Vesa , Peng Fan , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Paul Cercueil , Santosh Shilimkar , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Vladimir Zapolskiy , Heiko Stuebner , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Peter Griffin , Alim Akhtar , Dinh Nguyen , Viresh Kumar , Maxime Coquelin , Alexandre Torgue , =?utf-8?q?Emilio_L=C3=B3pe?= =?utf-8?q?z?= , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Kunihiko Hayashi , Masami Hiramatsu , Ulf Hansson , Liviu Dudau , Lorenzo Pieralisi , Michal Simek , Matthias Brugger Cc: linux-clk@vger.kernel.org, linux-aspeed@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, arm-scmi@vger.kernel.org, imx@lists.linux.dev, linux-mips@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, soc@lists.linux.dev, linux-stm32@st-md-mailman.stormreply.com, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, linux-mediatek@lists.infradead.org, Geert Uytterhoeven Subject: [PATCH 32/45] clk: socfpga: Make sure clk_init_data is fully initialized Date: Fri, 21 Aug 2026 10:53:42 +0200 Message-ID: <2d38d78f8d59583e29778bebc65eaab911d8a120.1787239813.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The clk_init_data structure contains several mutually-exclusive members for different methods to specify the possible parents of a clock, prompting drivers to initialize only the members they need. However, not initializing all members may cause subtle issues, which are only exposed when CONFIG_INIT_STACK_ALL_PATTERN or CONFIG_INIT_STACK_NONE is enabled. Make sure all members are fully initialized, to avoid such bugs, and to prevent future breakage when converting drivers to a different method for specifying the parents. Signed-off-by: Geert Uytterhoeven Acked-by: Dinh Nguyen --- Compile-tested only. --- drivers/clk/socfpga/clk-gate-a10.c | 2 +- drivers/clk/socfpga/clk-gate-s10.c | 6 +++--- drivers/clk/socfpga/clk-gate.c | 2 +- drivers/clk/socfpga/clk-periph-a10.c | 2 +- drivers/clk/socfpga/clk-periph-s10.c | 8 ++++---- drivers/clk/socfpga/clk-periph.c | 2 +- drivers/clk/socfpga/clk-pll-a10.c | 2 +- drivers/clk/socfpga/clk-pll-s10.c | 8 ++++---- drivers/clk/socfpga/clk-pll.c | 2 +- 9 files changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c index dd8d1713aaff7639..ba12179061b3fe9d 100644 --- a/drivers/clk/socfpga/clk-gate-a10.c +++ b/drivers/clk/socfpga/clk-gate-a10.c @@ -49,7 +49,7 @@ static void __init __socfpga_gate_init(struct device_node *node, struct socfpga_gate_clk *socfpga_clk; const char *clk_name = node->name; const char *parent_name[SOCFPGA_MAX_PARENTS]; - struct clk_init_data init; + struct clk_init_data init = {}; int rc; socfpga_clk = kzalloc_obj(*socfpga_clk); diff --git a/drivers/clk/socfpga/clk-gate-s10.c b/drivers/clk/socfpga/clk-gate-s10.c index 24f56a9edc44e528..4b23909c58106599 100644 --- a/drivers/clk/socfpga/clk-gate-s10.c +++ b/drivers/clk/socfpga/clk-gate-s10.c @@ -128,7 +128,7 @@ struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks, void _ { struct clk_hw *hw_clk; struct socfpga_gate_clk *socfpga_clk; - struct clk_init_data init; + struct clk_init_data init = {}; const char *parent_name = clks->parent_name; int ret; @@ -186,7 +186,7 @@ struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks, voi { struct clk_hw *hw_clk; struct socfpga_gate_clk *socfpga_clk; - struct clk_init_data init; + struct clk_init_data init = {}; const char *parent_name = clks->parent_name; int ret; @@ -244,7 +244,7 @@ struct clk_hw *agilex5_register_gate(const struct agilex5_gate_clock *clks, void { struct clk_hw *hw_clk; struct socfpga_gate_clk *socfpga_clk; - struct clk_init_data init; + struct clk_init_data init = {}; int ret; socfpga_clk = kzalloc_obj(*socfpga_clk); diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index ced8e09884068a26..d0f9fa44ad182520 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -143,7 +143,7 @@ void __init socfpga_gate_init(struct device_node *node) struct socfpga_gate_clk *socfpga_clk; const char *clk_name = node->name; const char *parent_name[SOCFPGA_MAX_PARENTS]; - struct clk_init_data init; + struct clk_init_data init = {}; struct clk_ops *ops; int rc; diff --git a/drivers/clk/socfpga/clk-periph-a10.c b/drivers/clk/socfpga/clk-periph-a10.c index 4eb5787f0dea3f8e..8aefc58ba4ec3944 100644 --- a/drivers/clk/socfpga/clk-periph-a10.c +++ b/drivers/clk/socfpga/clk-periph-a10.c @@ -65,7 +65,7 @@ static void __init __socfpga_periph_init(struct device_node *node, struct socfpga_periph_clk *periph_clk; const char *clk_name = node->name; const char *parent_name[SOCFPGA_MAX_PARENTS]; - struct clk_init_data init; + struct clk_init_data init = {}; int rc; u32 fixed_div; u32 div_reg[3]; diff --git a/drivers/clk/socfpga/clk-periph-s10.c b/drivers/clk/socfpga/clk-periph-s10.c index 5195b9476da16977..dc923d0d87869743 100644 --- a/drivers/clk/socfpga/clk-periph-s10.c +++ b/drivers/clk/socfpga/clk-periph-s10.c @@ -103,7 +103,7 @@ struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks, { struct clk_hw *hw_clk; struct socfpga_periph_clk *periph_clk; - struct clk_init_data init; + struct clk_init_data init = {}; const char *name = clks->name; const char *parent_name = clks->parent_name; int ret; @@ -139,7 +139,7 @@ struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks, { struct clk_hw *hw_clk; struct socfpga_periph_clk *periph_clk; - struct clk_init_data init; + struct clk_init_data init = {}; const char *name = clks->name; const char *parent_name = clks->parent_name; int ret; @@ -174,7 +174,7 @@ struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *c { struct clk_hw *hw_clk; struct socfpga_periph_clk *periph_clk; - struct clk_init_data init; + struct clk_init_data init = {}; const char *name = clks->name; const char *parent_name = clks->parent_name; int ret; @@ -220,7 +220,7 @@ struct clk_hw *agilex5_register_cnt_periph(const struct agilex5_perip_cnt_clock { struct clk_hw *hw_clk; struct socfpga_periph_clk *periph_clk; - struct clk_init_data init; + struct clk_init_data init = {}; const char *name = clks->name; int ret; diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c index 3821db6777e75413..8fa3d8e20042d731 100644 --- a/drivers/clk/socfpga/clk-periph.c +++ b/drivers/clk/socfpga/clk-periph.c @@ -55,7 +55,7 @@ static void __init __socfpga_periph_init(struct device_node *node, struct socfpga_periph_clk *periph_clk; const char *clk_name = node->name; const char *parent_name[SOCFPGA_MAX_PARENTS]; - struct clk_init_data init; + struct clk_init_data init = {}; int rc; u32 fixed_div; u32 div_reg[3]; diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c index c56f276e8d51e00f..63b8b75045aead8d 100644 --- a/drivers/clk/socfpga/clk-pll-a10.c +++ b/drivers/clk/socfpga/clk-pll-a10.c @@ -71,7 +71,7 @@ static void __init __socfpga_pll_init(struct device_node *node, struct socfpga_pll *pll_clk; const char *clk_name = node->name; const char *parent_name[SOCFGPA_MAX_PARENTS]; - struct clk_init_data init; + struct clk_init_data init = {}; struct device_node *clkmgr_np; int rc; int i = 0; diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c index ee236e87da33c020..1dca54b48375b168 100644 --- a/drivers/clk/socfpga/clk-pll-s10.c +++ b/drivers/clk/socfpga/clk-pll-s10.c @@ -192,7 +192,7 @@ struct clk_hw *s10_register_pll(const struct stratix10_pll_clock *clks, { struct clk_hw *hw_clk; struct socfpga_pll *pll_clk; - struct clk_init_data init; + struct clk_init_data init = {}; const char *name = clks->name; int ret; @@ -232,7 +232,7 @@ struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks, { struct clk_hw *hw_clk; struct socfpga_pll *pll_clk; - struct clk_init_data init; + struct clk_init_data init = {}; const char *name = clks->name; int ret; @@ -271,7 +271,7 @@ struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks, { struct clk_hw *hw_clk; struct socfpga_pll *pll_clk; - struct clk_init_data init; + struct clk_init_data init = {}; const char *name = clks->name; int ret; @@ -310,7 +310,7 @@ struct clk_hw *agilex5_register_pll(const struct agilex5_pll_clock *clks, { struct clk_hw *hw_clk; struct socfpga_pll *pll_clk; - struct clk_init_data init; + struct clk_init_data init = {}; const char *name = clks->name; int ret; diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c index f85adb16d414040f..aa13cc9d6db115fe 100644 --- a/drivers/clk/socfpga/clk-pll.c +++ b/drivers/clk/socfpga/clk-pll.c @@ -78,7 +78,7 @@ static void __init __socfpga_pll_init(struct device_node *node, struct socfpga_pll *pll_clk; const char *clk_name = node->name; const char *parent_name[SOCFPGA_MAX_PARENTS]; - struct clk_init_data init; + struct clk_init_data init = {}; struct device_node *clkmgr_np; int rc;