From patchwork Wed Sep 17 15:12:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Russell King (Oracle)" X-Patchwork-Id: 1003 Received: from pandora.armlinux.org.uk (pandora.armlinux.org.uk [78.32.30.218]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8366527EFFF for ; Wed, 17 Sep 2025 15:13:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=78.32.30.218 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758121987; cv=none; b=aohyea3y3r73hfaJqq90FnWUf910CB0serTj5hxuWZYyocuZVp6wlkmRYIYfDyKBZ5bnB+ZGOiaDEtgRCmzscFBWKKL0ybCUh/8dWpPneAUBM3wo3E5dIRtaCKriVSs+bU+H3sLMTtwyNFSaKfTFXReiAV/eJ6Fa9WmnmZpcGTI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758121987; c=relaxed/simple; bh=2o4jP5pOMc4mAfDOReHTE+0fpmXU6ZL9807Bimuu3y0=; h=In-Reply-To:References:From:To:Cc:Subject:MIME-Version: Content-Disposition:Content-Type:Message-Id:Date; b=PbVATGfluAjzz/HZhssomsiwVBt1+i0/q8Ebd66OQnC4U06deu+dA2yMAJNjfK0yiTtzFEN8ZvGCwxjxZ3gqsfiEU6HqUKkGqKx0WmD0KRf1Kw4CxBpKVXXDLrk358Y9PV+EKH3CmSICmA5+1RBCM3VyIpxO/HTb05Kh/fsJaAc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=armlinux.org.uk; spf=none smtp.mailfrom=armlinux.org.uk; dkim=pass (2048-bit key) header.d=armlinux.org.uk header.i=@armlinux.org.uk header.b=Ky4aasfZ; arc=none smtp.client-ip=78.32.30.218 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=armlinux.org.uk Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=armlinux.org.uk Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=armlinux.org.uk header.i=@armlinux.org.uk header.b="Ky4aasfZ" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=armlinux.org.uk; s=pandora-2019; h=Date:Sender:Message-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:Subject:Cc:To:From:References: In-Reply-To:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=PLGSCkhJYkYCcobuSQ5Oyaf1uTdDzYldkQNkhdDB1IA=; b=Ky4aasfZomTPEs8qJrkEO+3qSW R+FEbkZwUTF3AVeo4jl+6lmcokTr3ASdPmX3cAoDOnIzqYLLYIVHLDSQ+rG7DxOkiJiKXq9GJyC5X 8h5tF0n2ewXaLazmDSEpe+y1ae24MT3D60FIsCPBiH41ERffhxDePikqTk3P4PYqU+G1Nj6FgLBlh qTb1fnO0wDSjezlqtu++O4VmGYgHDQzkYkxW/CIxn4YBuhvkBaDw+/apGHqaI9uHFYheS+QjW0Bm5 5GTeaDgY8ynejLytv4jFUYvtq2HE/b7WVgfdoAnvrJb27nHkBC7kvUt9K6EoGDEJE77TQKP3dc19o 3skCHiuA==; Received: from e0022681537dd.dyn.armlinux.org.uk ([fd8f:7570:feb6:1:222:68ff:fe15:37dd]:60996 helo=rmk-PC.armlinux.org.uk) by pandora.armlinux.org.uk with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1uytpl-000000004m2-0fIP; Wed, 17 Sep 2025 16:12:37 +0100 Received: from rmk by rmk-PC.armlinux.org.uk with local (Exim 4.98.2) (envelope-from ) id 1uytpf-00000006H2c-3hiU; Wed, 17 Sep 2025 16:12:31 +0100 In-Reply-To: References: From: "Russell King (Oracle)" To: Andrew Lunn , Heiner Kallweit Cc: Alexandre Torgue , Andrew Lunn , Chen-Yu Tsai , "David S. Miller" , Drew Fustini , Emil Renner Berthing , Eric Dumazet , Fabio Estevam , Fu Wei , Guo Ren , imx@lists.linux.dev, Jakub Kicinski , Jernej Skrabec , linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-sunxi@lists.linux.dev, Maxime Chevallier , Maxime Coquelin , Minda Chen , Mohd Ayaan Anwar , netdev@vger.kernel.org, Paolo Abeni , Pengutronix Kernel Team , Samuel Holland , Sascha Hauer , Shawn Guo , Vladimir Zapolskiy Subject: [PATCH net-next 07/10] net: stmmac: stm32: convert to use phy_interface Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline Message-Id: Sender: Russell King Date: Wed, 17 Sep 2025 16:12:31 +0100 Status: O dwmac-stm32 supports MII, RMII, GMII and RGMII interface modes, selecting the dwmac core interface mode via bits 23:21 of the SYSCFG register. The bit combinations are identical to the dwmac phy_intf_sel_i signals. None of the DTS files set "mac-mode", so mac_interface will be identical to phy_interface. Convert dwmac-stm32 to use phy_interface when determining the interface mode rather than mac_interface. Signed-off-by: Russell King (Oracle) --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index 77a04c4579c9..6c179911ef3f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -171,7 +171,7 @@ static int stm32mp1_select_ethck_external(struct plat_stmmacenet_data *plat_dat) { struct stm32_dwmac *dwmac = plat_dat->bsp_priv; - switch (plat_dat->mac_interface) { + switch (plat_dat->phy_interface) { case PHY_INTERFACE_MODE_MII: dwmac->enable_eth_ck = dwmac->ext_phyclk; return 0; @@ -193,7 +193,7 @@ static int stm32mp1_select_ethck_external(struct plat_stmmacenet_data *plat_dat) default: dwmac->enable_eth_ck = false; dev_err(dwmac->dev, "Mode %s not supported", - phy_modes(plat_dat->mac_interface)); + phy_modes(plat_dat->phy_interface)); return -EINVAL; } } @@ -206,7 +206,7 @@ static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat) if (!dwmac->enable_eth_ck) return 0; - switch (plat_dat->mac_interface) { + switch (plat_dat->phy_interface) { case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII: if (clk_rate == ETH_CK_F_25M) @@ -228,7 +228,7 @@ static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat) } dev_err(dwmac->dev, "Mode %s does not match eth-ck frequency %d Hz", - phy_modes(plat_dat->mac_interface), clk_rate); + phy_modes(plat_dat->phy_interface), clk_rate); return -EINVAL; } @@ -238,7 +238,7 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat) u32 reg = dwmac->mode_reg; int val = 0; - switch (plat_dat->mac_interface) { + switch (plat_dat->phy_interface) { case PHY_INTERFACE_MODE_MII: /* * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only. @@ -269,12 +269,12 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat) break; default: dev_err(dwmac->dev, "Mode %s not supported", - phy_modes(plat_dat->mac_interface)); + phy_modes(plat_dat->phy_interface)); /* Do not manage others interfaces */ return -EINVAL; } - dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); + dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->phy_interface)); /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */ val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK); @@ -294,7 +294,7 @@ static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data *plat_dat) u32 reg = dwmac->mode_reg; int val = 0; - switch (plat_dat->mac_interface) { + switch (plat_dat->phy_interface) { case PHY_INTERFACE_MODE_MII: /* ETH_REF_CLK_SEL bit in SYSCFG register is not applicable in MII mode */ break; @@ -319,12 +319,12 @@ static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data *plat_dat) break; default: dev_err(dwmac->dev, "Mode %s not supported", - phy_modes(plat_dat->mac_interface)); + phy_modes(plat_dat->phy_interface)); /* Do not manage others interfaces */ return -EINVAL; } - dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); + dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->phy_interface)); /* Select PTP (IEEE1588) clock selection from RCC (ck_ker_ethxptp) */ val |= SYSCFG_ETHCR_ETH_PTP_CLK_SEL; @@ -359,7 +359,7 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat) u32 reg = dwmac->mode_reg; int val; - switch (plat_dat->mac_interface) { + switch (plat_dat->phy_interface) { case PHY_INTERFACE_MODE_MII: val = SYSCFG_MCU_ETH_SEL_MII; break; @@ -368,12 +368,12 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat) break; default: dev_err(dwmac->dev, "Mode %s not supported", - phy_modes(plat_dat->mac_interface)); + phy_modes(plat_dat->phy_interface)); /* Do not manage others interfaces */ return -EINVAL; } - dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); + dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->phy_interface)); return regmap_update_bits(dwmac->regmap, reg, SYSCFG_MCU_ETH_MASK, val << 23);