From patchwork Sat Sep 13 10:24:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 1013 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0C372E8DF1; Sat, 13 Sep 2025 10:25:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757759101; cv=none; b=jEPotKY4i7NgaxFTfR3Ky00WSRXQxpkHb/fPKXG0vwV7EjmAP33dN4A151sb++Gjflb4kJxJJ3i/QyahmQNQvMPUCZlE42M7ZuW7p9xoUeUmtevwOWylZoeU+vxy2KNbuyaGLovCs/KksIh06nqcxxRjHnuIL5j9MAAuk5086n4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757759101; c=relaxed/simple; bh=F1Bd2arcxbTkCF48WNm4VUaJPRpk9xfWUd6LNWgngaA=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=lpg5hbscj6XfLFti4PBcqbhpurrUBPzw+wJy+jyBZv9jozWD/4J512/EJVszuI/kAiKTL1mtmgKequCclJs2Vg0Ru6X9BFIMtBRbVYQV2A2OEJ6mKcpKRNRhIqZTYZPtPKRLaG7+iMPciFW8wOvAWNt1jwYfL6aHY4Ja0Ks9kX4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=txXKhMAA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="txXKhMAA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 05A6FC4AF0B; Sat, 13 Sep 2025 10:25:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757759101; bh=F1Bd2arcxbTkCF48WNm4VUaJPRpk9xfWUd6LNWgngaA=; h=From:To:Cc:Subject:Date:From; b=txXKhMAAMyPNO2QN8sEOlhqm/B0jycwB+TpbbHXDCOAHEF1XJ2hpharCoYFO223kx nNUDHubMapubYHp9/sme7sUiS43RtYSBfFYqIXSpcI+vgfwAfVjJG3/SNDXgN3JnRR Q1v3L6u+Pt+9eVCQxkpgR2CXl0NXn3R2ZUQZqSUHegNeN8XnqrM11BzGgYLEBqK1d7 ODfsqR6ojyC3nXmXeTOeW2vg+l4bP97f3BL9eEsrXGQCxymtzQUJ9yvn0qPsm3aCEb AcQjmGdl1QErVvN1vreOykTbur2X6KUMsjXoECz5AIbHDBk3Yhwg6sRYZvuuQwxnmu VT6+12u0MmMCQ== Received: by wens.tw (Postfix, from userid 1000) id A193C5FC8D; Sat, 13 Sep 2025 18:24:58 +0800 (CST) From: Chen-Yu Tsai To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara Cc: linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] arm64: dts: allwinner: a527: cubie-a5e: Drop external 32.768 KHz crystal Date: Sat, 13 Sep 2025 18:24:48 +0800 Message-Id: <20250913102450.3935943-1-wens@kernel.org> X-Mailer: git-send-email 2.39.5 Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O From: Chen-Yu Tsai The Radxa Cubie A5E has empty pads for a 32.768 KHz crystal, but it is left unpopulated, as per the schematics and seen on board images. A dead give away is the RTC's LOSC auto switch register showing the external OSC to be abnormal. Drop the external crystal from the device tree. It was not referenced anyway. Fixes: c2520cd032ae ("arm64: dts: allwinner: a523: add Radxa A5E support") Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index 71074b072184..e333bbaf01d3 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -24,13 +24,6 @@ chosen { stdout-path = "serial0:115200n8"; }; - ext_osc32k: ext-osc32k-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "ext_osc32k"; - }; - leds { compatible = "gpio-leds"; From patchwork Sat Sep 13 10:24:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 1015 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A5EB221F06; Sat, 13 Sep 2025 10:25:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757759101; cv=none; b=PhTlLuFOw54zlp1XXVdi2St1nlNkYUxabMIIYbi9vOusw7M2K4CLhfaouA34SBWKVFEbXpW1kweO85rizO7irAKBY0nvHgxn1gwmSHm5Nea5s8O6hmF/TEHz3VwbTt4XV14yXsZySo8JjOxhGuX6J0+wezxNCcQncIt4WKIfVFo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757759101; c=relaxed/simple; bh=9RmNGj7Z6j23AVn/GaYxlJV8TZ+lS7l5OuBjWd83A1Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CdXzHCbJOZDfsjk9LbyP4u2soi9g5++69ZAFneYBgbN7C1ul8EdCngFdGOTeEKJXmorB2QkwhnV8uXas1EUa0emzMTD9ojYDRWyKC1TRKPvcV1hNkAw7uX7iIN6L06vxoRk5dKl1BJyFZyYSzPJUGBenAXaEuniH8yUFkII3r9Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KuyQHpjT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KuyQHpjT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E3E38C4CEEB; Sat, 13 Sep 2025 10:25:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757759101; bh=9RmNGj7Z6j23AVn/GaYxlJV8TZ+lS7l5OuBjWd83A1Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KuyQHpjTCUOj0kl9bp7+z5S4WUK9QXtWV7aVEwTQDI8yFzgKvJo1ZSlCt+LtreOVb FrwFZB9anGfujIdemPpT++KG9bMBpeZ7i50Z3RCAAq3vpo7cRjwRWI9GqGLW3Cms4J GehctK5/bjygz/ce9u4XUekW2OaZg6UK6m4bfBW9wwKU6HzLu40h9rec8sF8ZuvQPf 2f8k/Cut+U9KPhA7hTZb5iiYJxfXKzbMrOviM2z4gadShg8cnXCk0tTdMKOuDYOCY+ bJXeolz6R/WsykGm6lJJsrliU8KszK5l9kPq/0Rh95VZmH/5cF3K3S/IOCOZEvQxIS zoIFFHXDxepgQ== Received: by wens.tw (Postfix, from userid 1000) id B173B5F752; Sat, 13 Sep 2025 18:24:58 +0800 (CST) From: Chen-Yu Tsai To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara Cc: linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] arm64: dts: allwinner: t527: avaota-a1: hook up external 32k crystal Date: Sat, 13 Sep 2025 18:24:49 +0800 Message-Id: <20250913102450.3935943-2-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250913102450.3935943-1-wens@kernel.org> References: <20250913102450.3935943-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O From: Chen-Yu Tsai When the board was added, its external 32.768 KHz crystal was described but not hooked up correctly. This meant the device had to fall back to the SoC's internal oscillator or divide a 32 KHz clock from the main oscillator, neither of which are accurate for the RTC. As a result the RTC clock will drift badly. Hook the crystal up to the RTC block and request the correct clock rate. Fixes: dbe54efa32af ("arm64: dts: allwinner: a523: add Avaota-A1 router support") Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index 535387912d9b..054d0357c139 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -354,6 +354,14 @@ &r_pio { vcc-pm-supply = <®_aldo3>; }; +&rtc { + clocks = <&r_ccu CLK_BUS_R_RTC>, <&osc24M>, + <&r_ccu CLK_R_AHB>, <&ext_osc32k>; + clock-names = "bus", "hosc", "ahb", "ext-osc32k"; + assigned-clocks = <&rtc CLK_OSC32K>; + assigned-clock-rates = <32768>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; From patchwork Sat Sep 13 10:24:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 1014 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A58521A421; Sat, 13 Sep 2025 10:25:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757759101; cv=none; b=dNxagTQSmHGKbaoAqu4LQE9trWFc/kjL7EFATbvwIwnIkJDJBmrRhG4EhDd5SPlAruAqYwnMqsp0Uzvjwd6DLX4eTVqFQyi+m2Q+LDiF6XIqHKaP1sb+URtN/wAscgR8OZ2NMYyNJkkTBou6mZDniQ4MN1H/ZoHu4oAHkDP7xrY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757759101; c=relaxed/simple; bh=7AISgck/ZfKlMuH4s1xfIjU+tBk3KnXivPq4YLbqruY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Pu7hBp8bQQx2+BWXytXXD4kLexAZnnYGZnc2uuDA4ei5Ky9jgRYJGe/8n557zZrrAp03iwZzz5vnf3VCue5lQ0GDv6okuTv0SMOc/Sni5aDZQD+RWch1jlrl2djs/RmXm7DGRBvphWz6VDybBSLVEv9mKfwSvEGD3C5Y0zOdisw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tyj2oI2R; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tyj2oI2R" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EA168C4CEF4; Sat, 13 Sep 2025 10:25:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757759101; bh=7AISgck/ZfKlMuH4s1xfIjU+tBk3KnXivPq4YLbqruY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tyj2oI2RMRQskhiT81MTqum2l6GhYqY0PwIRVt4nqfJRTrm3cfoNVuhHJKl17KV3B 4iRQvig9nVX+PBxa4lq9SpVAWPSzIwAZHRWHzrbfOXELt/o1uBDgzYAPLXuesKqYQa LF6B8O+C02ZS5EuLrVyhNC4NmzHGVbgd4dZdz53VUiqJzvABTQgZOtmaQZ4m37oPlF pQg969k78J4vJtPSlKvNL3IjKTKh+7uGupXQDJMTNfRschgeQKaTYEwpt9WQB7joQz hNXN7batDHUgvVlZvZS+wxX0tYSqIoQ18SQhW5V7kgNYLOUH9B7wukwGU7AHTHONlw TtM6J9DZrq7dQ== Received: by wens.tw (Postfix, from userid 1000) id BAADB5FE35; Sat, 13 Sep 2025 18:24:58 +0800 (CST) From: Chen-Yu Tsai To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara Cc: linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] arm64: dts: allwinner: t527: orangepi-4a: hook up external 32k crystal Date: Sat, 13 Sep 2025 18:24:50 +0800 Message-Id: <20250913102450.3935943-3-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250913102450.3935943-1-wens@kernel.org> References: <20250913102450.3935943-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O From: Chen-Yu Tsai When the board was added, its external 32.768 KHz crystal was described but not hooked up correctly. This meant the device had to fall back to the SoC's internal oscillator or divide a 32 KHz clock from the main oscillator, neither of which are accurate for the RTC. As a result the RTC clock will drift badly. Hook the crystal up to the RTC block and request the correct clock rate. Fixes: de713ccb9934 ("arm64: dts: allwinner: t527: Add OrangePi 4A board") Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index fb5311a46c2e..f71860db83d3 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -393,6 +393,14 @@ &r_pio { vcc-pm-supply = <®_bldo2>; }; +&rtc { + clocks = <&r_ccu CLK_BUS_R_RTC>, <&osc24M>, + <&r_ccu CLK_R_AHB>, <&ext_osc32k>; + clock-names = "bus", "hosc", "ahb", "ext-osc32k"; + assigned-clocks = <&rtc CLK_OSC32K>; + assigned-clock-rates = <32768>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>;