From patchwork Fri Aug 1 23:49:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1351 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4493FEAF1 for ; Fri, 1 Aug 2025 23:51:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754092306; cv=none; b=izfuMt7hBAUTeXki1SvEGUXZ3IEKO6paOaSRGDLgE/T5PdYwSJAAUZ9oNJgT05gmXvh/lXvZm//ROqxZylvRCDZg/rv8KAhn7NwyVHGyHtHrHiZZZ88QUxSKeMaeIo41ovy8SBUAZ+qPRuV4AtA+Ax5bSYAHpWNDq2v21Pp/alA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754092306; c=relaxed/simple; bh=8erzWeX3W5yF9GoTHi2946C64Fdjb1scwmkoB3lMEoQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lywV6plJODp4Kc9W4vu2rfrIcO30QP9p5QyEKQND3Cij5ENqOyiAEsLNDhHCFllToFQCPTdXd/EAzqwHXu1V8mfvHdvEZpcQuKu72nIR6JRrhP7vaSp1JWZV2iewrvHBu99ZoWuLASYbb21UCgSV6IacaMiehudIHzMj9S8XSpg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8C84D16A3; Fri, 1 Aug 2025 16:51:35 -0700 (PDT) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AA6A83F673; Fri, 1 Aug 2025 16:51:42 -0700 (PDT) From: Andre Przywara To: u-boot@lists.denx.de Cc: Tom Rini , Jernej Skrabec , Cody Eksal , Chris Morgan , linux-sunxi@lists.linux.dev Subject: [PATCH 1/3] sunxi: a133: dram: fix data type for address variable Date: Sat, 2 Aug 2025 00:49:16 +0100 Message-ID: <20250801234918.19176-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250801234918.19176-1-andre.przywara@arm.com> References: <20250801234918.19176-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O Variables holding addresses are typically using the "long" C type in U-Boot, to be easily compatible with both 32-bit and 64-bit builds. The A133 DRAM driver is typically compiled for AArch64, so u64 is the same type as unsigned long, but that breaks when compiling the DRAM driver in AArch32 (for some experiments). Fix the type to make the code more portable. Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/dram_sun50i_a133.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/dram_sun50i_a133.c b/arch/arm/mach-sunxi/dram_sun50i_a133.c index 3a231141168..1496f99624d 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_a133.c +++ b/arch/arm/mach-sunxi/dram_sun50i_a133.c @@ -416,7 +416,7 @@ static void mctl_com_init(const struct dram_para *para, static void mctl_drive_odt_config(const struct dram_para *para) { u32 val; - u64 base; + ulong base; u32 i; /* DX drive */ From patchwork Fri Aug 1 23:49:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1350 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 63197EAF1 for ; Fri, 1 Aug 2025 23:51:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754092308; cv=none; b=t7CeZNNPS973kCRmSxDUeLhqbfo3CwbaPzj+YZCBQyZiK25t24oBjGSkd5cXY1OvLO9djLXopvHXPUMjvyhv2xXQcQlB/t9jKFLxIPivBm7sUuQiyfWRuOMiu1uopM7VkPm80SGREXNWcTs2b7pEJq74t0U+ycsAsQT3d3PFuuo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754092308; c=relaxed/simple; bh=oYy5tomYRmgdnR6L9W5bBuc2BokkVazmSHhJ4DbLmtY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dVWoSq9eURJSfTZuM9GZTjXldsWqEcFRj79LNEi9tw1oKecgiwl2TmDB9gebAtilOuXrV3Sb/X1VvtQXy+766gCxt2W5qdUGxZDy//nt2hSg8xwIZmaQAw/QtkGj0mN6pYTD3/Mkr4d4HftdJkqUR9M8fmlBS00MJcr12VSfxsU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id ABC62237B; Fri, 1 Aug 2025 16:51:36 -0700 (PDT) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C9ABF3F673; Fri, 1 Aug 2025 16:51:43 -0700 (PDT) From: Andre Przywara To: u-boot@lists.denx.de Cc: Tom Rini , Jernej Skrabec , Cody Eksal , Chris Morgan , linux-sunxi@lists.linux.dev Subject: [PATCH 2/3] sunxi: spl: initialise timer before clocks Date: Sat, 2 Aug 2025 00:49:17 +0100 Message-ID: <20250801234918.19176-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250801234918.19176-1-andre.przywara@arm.com> References: <20250801234918.19176-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O Recent changes in the H6 clock code added delay() calls into the SPL clock setup routine, which requires the timers to work. When compiling for AArch64, we are always using the Arm Generic Timer (aka. arch timer), which does not require further setup, hence having an empty timer_init() routine. However for 32-bit SoCs we use the Allwinner timers, which require some setup routine, and hence we need timer_init() to be called before clock_init(). Swap the order of the two calls, to be more robust when compiling the H6 clock code for AArch32 or when using the Allwinner timers for whatever reason. Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index fb4837c2082..432b1c10f92 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -476,8 +476,8 @@ void board_init_f(ulong dummy) /* Enable non-secure access to some peripherals */ tzpc_init(); - clock_init(); timer_init(); + clock_init(); gpio_init(); spl_init(); From patchwork Fri Aug 1 23:49:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1349 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8E5CD23A9A3 for ; Fri, 1 Aug 2025 23:51:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754092308; cv=none; b=I1FubWg/nW1abVHNX6HA0Z18ZlMMsbJ2+hTdsTsU76G5sx+aZrjVD83GUEeoTakPv6T7g1U+WUmzW+JcYJBYk6WDS8n+wxCHipUAvsqksDjol3bVfb06Q6NSF7wUPt2nS8L0shJD5GEUVLTbMkazNB476cT52ZFsyXNXgUTg/vU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754092308; c=relaxed/simple; bh=U0ocPAT73F2+6pE4rYZsDzKyo40kQGtLDL9npKOHpCc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=d81nq8rL6yNRJ9UFXvGFZ6t3vG6rh6M5EmIlXSheIxfbAaW3hfFI7MS88/Mu0L0Zwv1p55AcGS7xHBuJRQCHHl/4yTawbIE42zMXtvdLiI/8IWYHXwsMb1mwZEJaHuHa7gbRhM5xpwRrVWiDJwsJjsMGIc3NM53KvqzmVZihswk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C934B25E1; Fri, 1 Aug 2025 16:51:37 -0700 (PDT) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E8BA93F673; Fri, 1 Aug 2025 16:51:44 -0700 (PDT) From: Andre Przywara To: u-boot@lists.denx.de Cc: Tom Rini , Jernej Skrabec , Cody Eksal , Chris Morgan , linux-sunxi@lists.linux.dev Subject: [PATCH 3/3] sunxi: H616: dram: fix LPDDR3 mode register settings Date: Sat, 2 Aug 2025 00:49:18 +0100 Message-ID: <20250801234918.19176-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250801234918.19176-1-andre.przywara@arm.com> References: <20250801234918.19176-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O The JEDEC LPDDR3 spec defines mode register 0 (MR0) as being read-only, so there is no point in trying to set its value. Also the H616 memory controller encodes the mode register index to be written starting from bit 8 in MRCTRL1 (for LPDDR3 and LPDDR4 chips), so we need to OR in that number to tell the controller which MR to program. On top of that, the mode registers between DDR3 and LPDDR3 are completely different, so writing values crafted for DDR3 into a LPDDR3 chip is just wrong. Due to the above mentioned bugs the writes for MR0-MR2 did not have any effect (as they were all trying to set the read-only MR0), so the mode registers just stayed unchanged. Looking at the LPDDR3 spec and the BSP code, let's write the proper MR values into LPDDR3 chips, using the proper addressing mode. Use the opportunity to document the LPDDR3 mode register bits written. Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/dram_sun50i_h616.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 877181016f3..3345c9b8e82 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -1078,18 +1078,18 @@ static bool mctl_phy_init(const struct dram_para *para, mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); break; case SUNXI_DRAM_TYPE_LPDDR3: - writel(mr0, &mctl_ctl->mrctrl1); - writel(0x800000f0, &mctl_ctl->mrctrl0); - mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); - - writel(4, &mctl_ctl->mrctrl1); + /* MR0 is read-only */ + /* MR1: nWR=14, BL8 */ + writel(0x183, &mctl_ctl->mrctrl1); writel(0x800000f0, &mctl_ctl->mrctrl0); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); - writel(mr2, &mctl_ctl->mrctrl1); + /* MR2: no WR leveling, WL set A, use nWR>9, nRL=14/nWL=8 */ + writel(0x21c, &mctl_ctl->mrctrl1); writel(0x800000f0, &mctl_ctl->mrctrl0); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + /* MR3: 34.3 Ohm pull-up/pull-down resistor */ writel(0x301, &mctl_ctl->mrctrl1); writel(0x800000f0, &mctl_ctl->mrctrl0); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);