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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Philipp Zabel , Maxime Ripard , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 1/8] dt-bindings: nvmem: SID: Add binding for A523 SID controller Date: Thu, 3 Jul 2025 23:11:25 +0800 Message-ID: <20250703151132.2642378-2-iuncuim@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250703151132.2642378-1-iuncuim@gmail.com> References: <20250703151132.2642378-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O From: Mikhail Kalashnikov The SID controller should be compatible with A64 and others SoC with 0x200 offset. Signed-off-by: Mikhail Kalashnikov --- .../devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml b/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml index 4424c3c5e..f67470b8a 100644 --- a/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml +++ b/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml @@ -27,6 +27,7 @@ properties: - enum: - allwinner,sun50i-a100-sid - allwinner,sun50i-h616-sid + - allwinner,sun55i-a523-sid - const: allwinner,sun50i-a64-sid - const: allwinner,sun50i-h5-sid - const: allwinner,sun50i-h6-sid From patchwork Thu Jul 3 15:11:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: iuncuim X-Patchwork-Id: 1488 Received: from mail-lj1-f176.google.com (mail-lj1-f176.google.com [209.85.208.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A36AF19F43A for ; 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Thu, 03 Jul 2025 08:12:42 -0700 (PDT) Received: from localhost.localdomain ([212.192.12.80]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-556384ae15esm725e87.178.2025.07.03.08.12.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jul 2025 08:12:42 -0700 (PDT) From: iuncuim To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Vasily Khoruzhick , Yangtao Li , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Philipp Zabel , Maxime Ripard , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 2/8] dt-bindings: thermal: sun8i: Add A523 THS0/1 controllers Date: Thu, 3 Jul 2025 23:11:26 +0800 Message-ID: <20250703151132.2642378-3-iuncuim@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250703151132.2642378-1-iuncuim@gmail.com> References: <20250703151132.2642378-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O From: Mikhail Kalashnikov Add a binding for D1/T113s thermal sensor controller. Add dt-bindings description of the thermal sensors in the A523 processor. The controllers require activation of the additional frequency of the associated gpadc controller, so a new clock property has been added. The calibration data is split into two cells that are in different areas of nvmem. Both controllers require access to both memory cell, so a new property nvmem-cells has been added. To maintain backward compatibility, the name of the old cell remains the same and the new nvmem-cell-names is called calibration-second-part Signed-off-by: Mikhail Kalashnikov --- .../thermal/allwinner,sun8i-a83t-ths.yaml | 49 +++++++++++++++++-- 1 file changed, 46 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml index 3e61689f6..80657435a 100644 --- a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml +++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml @@ -24,18 +24,22 @@ properties: - allwinner,sun50i-h5-ths - allwinner,sun50i-h6-ths - allwinner,sun50i-h616-ths + - allwinner,sun55i-a523-ths0 + - allwinner,sun55i-a523-ths1 clocks: minItems: 1 items: - description: Bus Clock - description: Module Clock + - description: GPADC Clock clock-names: minItems: 1 items: - const: bus - const: mod + - const: gpadc reg: maxItems: 1 @@ -47,11 +51,16 @@ properties: maxItems: 1 nvmem-cells: - maxItems: 1 - description: Calibration data for thermal sensors + minItems: 1 + items: + - description: Calibration data for thermal sensors + - description: Additional cell in case of separate calibration data nvmem-cell-names: - const: calibration + minItems: 1 + items: + - const: calibration + - const: calibration-second-part allwinner,sram: maxItems: 1 @@ -107,6 +116,7 @@ allOf: enum: - allwinner,sun8i-h3-ths - allwinner,sun20i-d1-ths + - allwinner,sun55i-a523-ths0 then: properties: @@ -132,6 +142,26 @@ allOf: - clock-names - resets + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun55i-a523-ths0 + - allwinner,sun55i-a523-ths1 + then: + properties: + clocks: + minItems: 2 + clock-names: + items: + - const: bus + - const: gpadc + nvmem-cells: + minItems: 2 + nvmem-cell-names: + minItems: 2 + required: - compatible - reg @@ -176,4 +206,17 @@ examples: #thermal-sensor-cells = <1>; }; + - | + thermal-sensor@2009400 { + compatible = "allwinner,sun55i-a523-ths1"; + reg = <0x02009400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC1>; + clock-names = "bus", "gpadc"; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration0>, <&ths_calibration1>; + nvmem-cell-names = "calibration", + "calibration-second-part"; + #thermal-sensor-cells = <1>; + }; ... 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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Philipp Zabel , Maxime Ripard , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 3/8] thermal/drivers/sun8i: add gpadc clock Date: Thu, 3 Jul 2025 23:11:27 +0800 Message-ID: <20250703151132.2642378-4-iuncuim@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250703151132.2642378-1-iuncuim@gmail.com> References: <20250703151132.2642378-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O From: Mikhail Kalashnikov Some processors (e.g. Allwinner A523) require GPADC clocking activation for temperature sensors to work. So let's add support for enabling it. Signed-off-by: Mikhail Kalashnikov --- drivers/thermal/sun8i_thermal.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c index 226747906..45aaf5348 100644 --- a/drivers/thermal/sun8i_thermal.c +++ b/drivers/thermal/sun8i_thermal.c @@ -66,8 +66,9 @@ struct tsensor { }; struct ths_thermal_chip { - bool has_mod_clk; - bool has_bus_clk_reset; + bool has_gpadc_clk; + bool has_mod_clk; + bool has_bus_clk_reset; bool needs_sram; int sensor_num; int offset; @@ -89,7 +90,8 @@ struct ths_device { struct regmap_field *sram_regmap_field; struct reset_control *reset; struct clk *bus_clk; - struct clk *mod_clk; + struct clk *mod_clk; + struct clk *gpadc_clk; struct tsensor sensor[MAX_SENSOR_NUM]; }; @@ -417,6 +419,12 @@ static int sun8i_ths_resource_init(struct ths_device *tmdev) if (ret) return ret; + if (tmdev->chip->has_gpadc_clk) { + tmdev->gpadc_clk = devm_clk_get_enabled(&pdev->dev, "gpadc"); + if (IS_ERR(tmdev->gpadc_clk)) + return PTR_ERR(tmdev->gpadc_clk); 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Thu, 03 Jul 2025 08:13:20 -0700 (PDT) From: iuncuim To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Vasily Khoruzhick , Yangtao Li , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Philipp Zabel , Maxime Ripard , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 4/8] thermal/drivers/sun8i: replace devm_reset_control_get to devm_reset_control_get_shared_deasserted Date: Thu, 3 Jul 2025 23:11:28 +0800 Message-ID: <20250703151132.2642378-5-iuncuim@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250703151132.2642378-1-iuncuim@gmail.com> References: <20250703151132.2642378-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O From: Mikhail Kalashnikov The A523 processor has two temperature controllers, but they share a common reset line. We can to use devm_reset_control_get_shared_deasserted() instead of devm_reset_control_get(). This will simplify the driver. Signed-off-by: Mikhail Kalashnikov --- drivers/thermal/sun8i_thermal.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c index 45aaf5348..bdd15ee45 100644 --- a/drivers/thermal/sun8i_thermal.c +++ b/drivers/thermal/sun8i_thermal.c @@ -344,11 +344,6 @@ static int sun8i_ths_calibrate(struct ths_device *tmdev) return ret; } -static void sun8i_ths_reset_control_assert(void *data) -{ - reset_control_assert(data); -} - static struct regmap *sun8i_ths_get_sram_regmap(struct device_node *node) { struct platform_device *sram_pdev; @@ -391,19 +386,10 @@ static int sun8i_ths_resource_init(struct ths_device *tmdev) return PTR_ERR(tmdev->regmap); if (tmdev->chip->has_bus_clk_reset) { - tmdev->reset = devm_reset_control_get(dev, NULL); + tmdev->reset = devm_reset_control_get_shared_deasserted(dev, NULL); if (IS_ERR(tmdev->reset)) return PTR_ERR(tmdev->reset); - ret = reset_control_deassert(tmdev->reset); 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Thu, 03 Jul 2025 08:13:40 -0700 (PDT) Received: from localhost.localdomain ([212.192.12.80]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-556384ae15esm725e87.178.2025.07.03.08.13.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jul 2025 08:13:40 -0700 (PDT) From: iuncuim To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Vasily Khoruzhick , Yangtao Li , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Philipp Zabel , Maxime Ripard , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 5/8] thermal/drivers/sun8i: get calibration data from two nvmem cells Date: Thu, 3 Jul 2025 23:11:29 +0800 Message-ID: <20250703151132.2642378-6-iuncuim@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250703151132.2642378-1-iuncuim@gmail.com> References: <20250703151132.2642378-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O From: Mikhail Kalashnikov The A523 processor has calibration data in two nvmem cell. To be able to add support, the ability to add data from two cells into one array must be added. Signed-off-by: Mikhail Kalashnikov --- drivers/thermal/sun8i_thermal.c | 77 ++++++++++++++++++++++----------- 1 file changed, 52 insertions(+), 25 deletions(-) diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c index bdd15ee45..3f57f1a6b 100644 --- a/drivers/thermal/sun8i_thermal.c +++ b/drivers/thermal/sun8i_thermal.c @@ -303,43 +303,70 @@ static int sun50i_h6_ths_calibrate(struct ths_device *tmdev, static int sun8i_ths_calibrate(struct ths_device *tmdev) { - struct nvmem_cell *calcell; + struct nvmem_cell *calcell = NULL; struct device *dev = tmdev->dev; - u16 *caldata; - size_t callen; + struct device_node *np = dev_of_node(dev); + struct property *prop; + const char *cellname; + u8 *caldata = NULL; + size_t callen = 0; int ret = 0; - calcell = nvmem_cell_get(dev, "calibration"); - if (IS_ERR(calcell)) { - if (PTR_ERR(calcell) == -EPROBE_DEFER) - return -EPROBE_DEFER; - /* - * Even if the external calibration data stored in sid is - * not accessible, the THS hardware can still work, although - * the data won't be so accurate. - * - * The default value of calibration register is 0x800 for - * every sensor, and the calibration value is usually 0x7xx - * or 0x8xx, so they won't be away from the default value - * for a lot. - * - * So here we do not return error if the calibration data is - * not available, except the probe needs deferring. - */ - goto out; + of_property_for_each_string(np, "nvmem-cell-names", prop, cellname) { + size_t len; + u8 *caldatapart; + + calcell = of_nvmem_cell_get(np, cellname); + if (IS_ERR(calcell)) { + if (PTR_ERR(calcell) == -EPROBE_DEFER) + return -EPROBE_DEFER; + /* + * Even if the external calibration data stored in sid is + * not accessible, the THS hardware can still work, although + * the data won't be so accurate. + * + * The default value of calibration register is 0x800 for + * every sensor, and the calibration value is usually 0x7xx + * or 0x8xx, so they won't be away from the default value + * for a lot. + * + * So here we do not return error if the calibration data is + * not available, except the probe needs deferring. + */ + goto out; + } + + caldatapart = nvmem_cell_read(calcell, &len); + nvmem_cell_put(calcell); + calcell = NULL; + if (IS_ERR(caldatapart)) { + ret = PTR_ERR(caldatapart); + goto out; + } + + caldata = devm_krealloc(dev, caldata, callen + len, GFP_KERNEL); + if (!caldata) { + kfree(caldatapart); + ret = -ENOMEM; + goto out; + } + + memcpy(caldata + callen, caldatapart, len); + callen += len; + kfree(caldatapart); } - caldata = nvmem_cell_read(calcell, &callen); if (IS_ERR(caldata)) { ret = PTR_ERR(caldata); goto out; } - tmdev->chip->calibrate(tmdev, caldata, callen); + tmdev->chip->calibrate(tmdev, (u16 *)caldata, callen); - kfree(caldata); + devm_kfree(dev, caldata); + caldata = NULL; out: - if (!IS_ERR(calcell)) + if (calcell && !IS_ERR(calcell)) nvmem_cell_put(calcell); return ret; } From patchwork Thu Jul 3 15:11:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: iuncuim X-Patchwork-Id: 1484 Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E64B2EFDAD for ; Thu, 3 Jul 2025 15:14:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 03 Jul 2025 08:14:00 -0700 (PDT) Received: from localhost.localdomain ([212.192.12.80]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-556384ae15esm725e87.178.2025.07.03.08.13.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jul 2025 08:14:00 -0700 (PDT) From: iuncuim To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Vasily Khoruzhick , Yangtao Li , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Philipp Zabel , Maxime Ripard , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 6/8] thermal/drivers/sun8i: Add support for A523 THS0/1 controllers Date: Thu, 3 Jul 2025 23:11:30 +0800 Message-ID: <20250703151132.2642378-7-iuncuim@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250703151132.2642378-1-iuncuim@gmail.com> References: <20250703151132.2642378-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O From: Mikhail Kalashnikov The A523 processor has two temperature controllers, THS0 and THS1. THS0 has only one temperature sensor, which is located in the DRAM. THS1 does have 3 sensors: ths1_0 - "big" cores ths1_1 - "little" cores ths1_2 - gpu The datasheet mentions a fourth sensor in the NPU, but lacks any registers for operation other than calibration registers. The vendor code reads the value from ths1_2, but uses separate calibration data, so we get two different values from real one. Signed-off-by: Mikhail Kalashnikov --- drivers/thermal/sun8i_thermal.c | 133 ++++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c index 3f57f1a6b..f74567cbf 100644 --- a/drivers/thermal/sun8i_thermal.c +++ b/drivers/thermal/sun8i_thermal.c @@ -59,6 +59,12 @@ #define SUN50I_H6_THS_PC_TEMP_PERIOD(x) ((GENMASK(19, 0) & (x)) << 12) #define SUN50I_H6_THS_DATA_IRQ_STS(x) BIT(x) +#define SUN55I_A523_DELIMITER 0x7c8 +#define SUN55I_A523_OFFSET_ABOVE 2736 +#define SUN55I_A523_OFFSET_BELOW 2825 +#define SUN55I_A523_SCALE_ABOVE 74 +#define SUN55I_A523_SCALE_BELOW 65 + struct tsensor { struct ths_device *tmdev; struct thermal_zone_device *tzd; @@ -116,6 +122,15 @@ static int sun50i_h5_calc_temp(struct ths_device *tmdev, return -1590 * reg / 10 + 276000; } +static int sun55i_a523_calc_temp(struct ths_device *tmdev, + int id, int reg) +{ + if (reg >= SUN55I_A523_DELIMITER) + return SUN55I_A523_SCALE_ABOVE * (SUN55I_A523_OFFSET_ABOVE - reg); + else + return SUN55I_A523_SCALE_BELOW * (SUN55I_A523_OFFSET_BELOW - reg); +} + static int sun8i_ths_get_temp(struct thermal_zone_device *tz, int *temp) { struct tsensor *s = thermal_zone_device_priv(tz); @@ -301,6 +316,97 @@ static int sun50i_h6_ths_calibrate(struct ths_device *tmdev, return 0; } +/* + * The A523 nvmem calibration values. The ths1_3 is not used as it + * doesn't have its own sensor and doesn't have any internal switch. + * Instead, the value from the ths1_2 sensor is used, which gives the + * illusion of an independent sensor for NPU and GPU when using + * different calibration values. + * + * efuse layout 0x38-0x3F (caldata[0..3]): + * caldata[0] caldata[1] caldata[2] caldata[3] + * 0 16 24 32 36 48 60 64 + * +---------------+---------------+---------------+---------------+ + * | | | temp | ths1_0 | ths1_1 | + + * +---------------+---------------+---------------+---------------+ + * + * efuse layout 0x44-0x4B (caldata[4..7]): + * caldata[4] caldata[5] caldata[6] caldata[7] + * 0 12 16 24 32 36 48 64 + * +---------------+---------------+---------------+---------------+ + * | ths1_2 | ths1_3 | ths0 | | + + * +---------------+---------------+---------------+---------------+ + */ +static int sun55i_a523_ths_calibrate(struct ths_device *tmdev, + u16 *caldata, int callen) +{ + struct device *dev = tmdev->dev; + int i, ft_temp; + + if (!caldata[0]) + return -EINVAL; + + ft_temp = (((caldata[2] << 8) | (caldata[1] >> 8)) & FT_TEMP_MASK) * 100; + + for (i = 0; i < tmdev->chip->sensor_num; i++) { + int sensor_reg, sensor_temp, cdata, offset; + /* + * Chips ths0 and ths1 have common parameters for value + * calibration. To separate them we can use the number of + * temperature sensors on each chip. + * For ths0 this value is 1. + */ + if (tmdev->chip->sensor_num == 1) { + sensor_reg = ((caldata[5] >> 8) | (caldata[6] << 8)) & TEMP_CALIB_MASK; + } else { + switch (i) { + case 0: + sensor_reg = (caldata[2] >> 4) & TEMP_CALIB_MASK; + break; + case 1: + sensor_reg = caldata[3] & TEMP_CALIB_MASK; + break; + case 2: + sensor_reg = caldata[4] & TEMP_CALIB_MASK; + break; + default: + sensor_reg = 0; + break; + } + } + + sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg); + + /* + * Calibration data is CALIBRATE_DEFAULT - (calculated + * temperature from sensor reading at factory temperature + * minus actual factory temperature) * X (scale from + * temperature to register values) + */ + cdata = CALIBRATE_DEFAULT - + ((sensor_temp - ft_temp) / SUN55I_A523_SCALE_ABOVE); + + if (cdata & ~TEMP_CALIB_MASK) { + /* + * Calibration value more than 12-bit, but calibration + * register is 12-bit. In this case, ths hardware can + * still work without calibration, although the data + * won't be so accurate. + */ + dev_warn(dev, "sensor%d is not calibrated.\n", i); + continue; + } + + offset = (i % 2) * 16; + regmap_update_bits(tmdev->regmap, + SUN50I_H6_THS_TEMP_CALIB + (i / 2 * 4), + TEMP_CALIB_MASK << offset, + cdata << offset); + } + + return 0; +} + static int sun8i_ths_calibrate(struct ths_device *tmdev) { struct nvmem_cell *calcell = NULL; @@ -730,6 +836,31 @@ static const struct ths_thermal_chip sun50i_h616_ths = { .calc_temp = sun8i_ths_calc_temp, }; +/* The A523 has a shared reset line for both chips */ +static const struct ths_thermal_chip sun55i_a523_ths0 = { + .sensor_num = 1, + .has_bus_clk_reset = true, + .has_gpadc_clk = true, + .ft_deviation = 5000, + .temp_data_base = SUN50I_H6_THS_TEMP_DATA, + .calibrate = sun55i_a523_ths_calibrate, + .init = sun50i_h6_thermal_init, + .irq_ack = sun50i_h6_irq_ack, + .calc_temp = sun55i_a523_calc_temp, +}; + +static const struct ths_thermal_chip sun55i_a523_ths1 = { + .sensor_num = 3, + .has_bus_clk_reset = true, + .has_gpadc_clk = true, + .ft_deviation = 5000, + .temp_data_base = SUN50I_H6_THS_TEMP_DATA, + .calibrate = sun55i_a523_ths_calibrate, + .init = sun50i_h6_thermal_init, + .irq_ack = sun50i_h6_irq_ack, + .calc_temp = sun55i_a523_calc_temp, +}; + static const struct of_device_id of_ths_match[] = { { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths }, { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths }, @@ -740,6 +871,8 @@ static const struct of_device_id of_ths_match[] = { { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths }, { .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths }, { .compatible = "allwinner,sun50i-h616-ths", .data = &sun50i_h616_ths }, + { .compatible = "allwinner,sun55i-a523-ths0", .data = &sun55i_a523_ths0 }, + { .compatible = "allwinner,sun55i-a523-ths1", .data = &sun55i_a523_ths1 }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, of_ths_match); From patchwork Thu Jul 3 15:11:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: iuncuim X-Patchwork-Id: 1483 Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A40962F0027 for ; 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Thu, 03 Jul 2025 08:14:19 -0700 (PDT) Received: from localhost.localdomain ([212.192.12.80]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-556384ae15esm725e87.178.2025.07.03.08.14.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jul 2025 08:14:19 -0700 (PDT) From: iuncuim To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Vasily Khoruzhick , Yangtao Li , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Philipp Zabel , Maxime Ripard , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 7/8] arm64: dts: allwinner: A523: Add SID controller node Date: Thu, 3 Jul 2025 23:11:31 +0800 Message-ID: <20250703151132.2642378-8-iuncuim@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250703151132.2642378-1-iuncuim@gmail.com> References: <20250703151132.2642378-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O From: Mikhail Kalashnikov The SID controller should be compatible with A64 and others SoC with 0x200 offset. Signed-off-by: Mikhail Kalashnikov Reviewed-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index 8b7cbc2e7..295292d67 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -181,6 +181,14 @@ ccu: clock-controller@2001000 { #reset-cells = <1>; }; + sid: efuse@3006000 { + compatible = "allwinner,sun55i-a523-sid", + "allwinner,sun50i-a64-sid"; + reg = <0x03006000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + mmc0: mmc@4020000 { compatible = "allwinner,sun55i-a523-mmc", "allwinner,sun20i-d1-mmc"; From patchwork Thu Jul 3 15:11:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: iuncuim X-Patchwork-Id: 1482 Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32A0E15442C for ; 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Thu, 03 Jul 2025 08:14:39 -0700 (PDT) Received: from localhost.localdomain ([212.192.12.80]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-556384ae15esm725e87.178.2025.07.03.08.14.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jul 2025 08:14:38 -0700 (PDT) From: iuncuim To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Vasily Khoruzhick , Yangtao Li , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Philipp Zabel , Maxime Ripard , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 8/8] arm64: dts: allwinner: A523: Add thermal sensors and zones Date: Thu, 3 Jul 2025 23:11:32 +0800 Message-ID: <20250703151132.2642378-9-iuncuim@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250703151132.2642378-1-iuncuim@gmail.com> References: <20250703151132.2642378-1-iuncuim@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O From: Mikhail Kalashnikov The A523 processor has two temperature controllers, THS0 and THS1. THS0 has only one temperature sensor, which is located in the DRAM. THS1 does have 3 sensors: ths1_0 - "big" cores ths1_1 - "little" cores ths1_2 - gpu Add the thermal sensor configuration and the thermal zones. Trips temperature, polling-delay and sustainable-power parameters are derived from the manufacturer's BSP. Signed-off-by: Mikhail Kalashnikov --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 154 ++++++++++++++++++ 1 file changed, 154 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index 295292d67..a1304c55c 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { interrupt-parent = <&gic>; @@ -22,6 +23,7 @@ cpu0: cpu@0 { device_type = "cpu"; reg = <0x000>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu1: cpu@100 { @@ -29,6 +31,7 @@ cpu1: cpu@100 { device_type = "cpu"; reg = <0x100>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu2: cpu@200 { @@ -36,6 +39,7 @@ cpu2: cpu@200 { device_type = "cpu"; reg = <0x200>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu3: cpu@300 { @@ -43,6 +47,7 @@ cpu3: cpu@300 { device_type = "cpu"; reg = <0x300>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu4: cpu@400 { @@ -50,6 +55,7 @@ cpu4: cpu@400 { device_type = "cpu"; reg = <0x400>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu5: cpu@500 { @@ -57,6 +63,7 @@ cpu5: cpu@500 { device_type = "cpu"; reg = <0x500>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu6: cpu@600 { @@ -64,6 +71,7 @@ cpu6: cpu@600 { device_type = "cpu"; reg = <0x600>; enable-method = "psci"; + #cooling-cells = <2>; }; cpu7: cpu@700 { @@ -71,6 +79,7 @@ cpu7: cpu@700 { device_type = "cpu"; reg = <0x700>; enable-method = "psci"; + #cooling-cells = <2>; }; }; @@ -181,12 +190,46 @@ ccu: clock-controller@2001000 { #reset-cells = <1>; }; + ths1: thermal-sensor@2009400 { + compatible = "allwinner,sun55i-a523-ths1"; + reg = <0x02009400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC1>; + clock-names = "bus", "gpadc"; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration0>, <&ths_calibration1>; + nvmem-cell-names = "calibration", + "calibration-second-part"; + #thermal-sensor-cells = <1>; + }; + + ths0: thermal-sensor@200a000 { + compatible = "allwinner,sun55i-a523-ths0"; + reg = <0x0200a000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC0>; + clock-names = "bus", "gpadc"; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration0>, <&ths_calibration1>; + nvmem-cell-names = "calibration", + "calibration-second-part"; + #thermal-sensor-cells = <0>; + }; + sid: efuse@3006000 { compatible = "allwinner,sun55i-a523-sid", "allwinner,sun50i-a64-sid"; reg = <0x03006000 0x1000>; #address-cells = <1>; #size-cells = <1>; + + ths_calibration0: ths-calibration0@38 { + reg = <0x38 0x8>; + }; + + ths_calibration1: ths-calibration1@44 { + reg = <0x44 0x8>; + }; }; mmc0: mmc@4020000 { @@ -644,4 +687,115 @@ rtc: rtc@7090000 { #clock-cells = <1>; }; }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&ths1 1>; + sustainable-power = <1200>; + + trips { + cpu0_threshold: cpu-trip-0 { + temperature = <70000>; + type = "passive"; + hysteresis = <0>; + }; + cpu0_target: cpu-trip-1 { + temperature = <90000>; + type = "passive"; + hysteresis = <0>; + }; + cpu0_critical: cpu-trip-2 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4_thermal: cpu4-thermal { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&ths1 0>; + sustainable-power = <1600>; + + trips { + cpu4_threshold: cpu-trip-0 { + temperature = <70000>; + type = "passive"; + hysteresis = <0>; + }; + cpu4_target: cpu-trip-1 { + temperature = <90000>; + type = "passive"; + hysteresis = <0>; + }; + cpu4_critical: cpu-trip-2 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu4_target>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&ths1 2>; + sustainable-power = <2400>; + + gpu-trips { + gpu_temp_threshold: gpu-trip-0 { + temperature = <60000>; + type = "passive"; + hysteresis = <0>; + }; + gpu_temp_target: gpu-trip-1 { + temperature = <90000>; + type = "passive"; + hysteresis = <0>; + }; + gpu_temp_critical: gpu-trip-2 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + }; + + ddr-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths0>; + + trips { + ddr_temp_critical: ddr-trip-0 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + }; + }; };