From patchwork Sun Jun 1 15:39:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Kocialkowski X-Patchwork-Id: 1641 Received: from leonov.paulk.fr (leonov.paulk.fr [185.233.101.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D17052DCC09 for ; Sun, 1 Jun 2025 15:40:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.233.101.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748792462; cv=none; b=Fdu2Vif2e3x/TPs/z0hz4q/IjDMiekAEOeETXJxAyBfp6rMoXBFBMC81Omq+17UeHbmxpWoZZX1zgUM0KdYF8wkst1QfSVMiTcw4ZQ1pKTNzf7aTWkTN6xCoDYo0IPhjERpfWM8jbbkU0oQkZ6CSgiHig6PFi0iDJpIDRZ+EcJk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748792462; c=relaxed/simple; bh=oD68e8YlVeLUBoQZ5Ie3hdL/0aasgXRSJOqj8rfT800=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MAwPA7heENrPbHa1G4qvH/6hjH3n2bS5mHZM7JYJaobjkGGIgr+nlOPQ8vNwEj5AABeihAUTiqGmYlmtXY5x5bPS7SKaiOmq9js000R3ZEnMa1jROqzJoPbawmihgNGdwUjGMUVITyiuQCJk1Rtdu7BOIbjAFqFDR4pHq7H8hCo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=paulk.fr; spf=pass smtp.mailfrom=paulk.fr; arc=none smtp.client-ip=185.233.101.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=paulk.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=paulk.fr Received: from laika.paulk.fr (12.234.24.109.rev.sfr.net [109.24.234.12]) by leonov.paulk.fr (Postfix) with ESMTPS id 4882F1F0004B for ; Sun, 1 Jun 2025 15:40:55 +0000 (UTC) Received: by laika.paulk.fr (Postfix, from userid 65534) id AE510AC32AD; Sun, 1 Jun 2025 15:40:54 +0000 (UTC) X-Spam-Level: * Received: from localhost.localdomain (unknown [192.168.1.64]) by laika.paulk.fr (Postfix) with ESMTP id 607A6AC32AD; Sun, 1 Jun 2025 15:39:59 +0000 (UTC) From: Paul Kocialkowski To: u-boot@lists.denx.de Cc: Tom Rini , Jagan Teki , Andre Przywara , Icenowy Zheng , linux-sunxi@lists.linux.dev, Paul Kocialkowski Subject: [PATCH 1/6] sunxi: Kconfig: Fix default order for V3s DRAM clock Date: Sun, 1 Jun 2025 17:39:38 +0200 Message-ID: <20250601153943.2690123-2-contact@paulk.fr> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250601153943.2690123-1-contact@paulk.fr> References: <20250601153943.2690123-1-contact@paulk.fr> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O The V3s (using co-packaged DRAM) runs at 360 MHz, which is specified in the common platform Kconfig file. However the value for MACH_SUN8I will be picked up instead due to ordering. Re-order the defaults to have MACH_SUN8I_V3S before MACH_SUN8I and let it select the correct default. Also update the LicheePi Zero Dock defconfig to remove the value, which is now correctly selected. Signed-off-by: Paul Kocialkowski --- arch/arm/mach-sunxi/Kconfig | 2 +- configs/LicheePi_Zero_defconfig | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 17179593913e..8b43fd176dc0 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -591,9 +591,9 @@ config DRAM_CLK int "sunxi dram clock speed" default 792 if MACH_SUN9I default 648 if MACH_SUN8I_R40 - default 312 if MACH_SUN6I || MACH_SUN8I default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \ MACH_SUN8I_V3S + default 312 if MACH_SUN6I || MACH_SUN8I default 672 if MACH_SUN50I default 744 if MACH_SUN50I_H6 default 720 if MACH_SUN50I_H616 diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig index c37c49ccbb16..b2cf0a018c7f 100644 --- a/configs/LicheePi_Zero_defconfig +++ b/configs/LicheePi_Zero_defconfig @@ -3,6 +3,5 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero" CONFIG_SPL=y CONFIG_MACH_SUN8I_V3S=y -CONFIG_DRAM_CLK=360 # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_NO_NET=y From patchwork Sun Jun 1 15:39:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Kocialkowski X-Patchwork-Id: 1640 Received: from leonov.paulk.fr (leonov.paulk.fr [185.233.101.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 832AE2DCC09 for ; Sun, 1 Jun 2025 15:41:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.233.101.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748792485; cv=none; b=b7+11k2FwhvPrgs3s+PtkpK74UCsJwXXU+isdU67OQgQyjEvtFI1u4vZvFc2fshuroZBJRnGaOwulY+wzC2cL2rRar7lgigiqnw0Y75kJngL8BvrJg7sE3xR9Ipyk2L/D6cgufcQF/Mp85kjiRebkLILs9Pfo2Od2vDaCV7od5Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748792485; c=relaxed/simple; bh=/1gPO18auefQVr2VnPI1NwQf85pxvy82Or2c6hR96p0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=r1U6/0wzJK2HXarlAH5ZmZ+nm89/YIbCejcsN167PIUdgwBaQ77/PrlX3ZOluhE2ZgC3duMn4wcQNbFHX7+tWD5r6GMaKHYWpBZgI49upDKZdFW7F6+VgqkpbB/TUz+ili58Zzn/tt3ejzAwv8CeaX30aADP227kGah7zk9RAqU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=paulk.fr; spf=pass smtp.mailfrom=paulk.fr; arc=none smtp.client-ip=185.233.101.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=paulk.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=paulk.fr Received: from laika.paulk.fr (12.234.24.109.rev.sfr.net [109.24.234.12]) by leonov.paulk.fr (Postfix) with ESMTPS id 50E1F1F0004D for ; Sun, 1 Jun 2025 15:41:17 +0000 (UTC) Received: by laika.paulk.fr (Postfix, from userid 65534) id C881DAC32E9; Sun, 1 Jun 2025 15:41:16 +0000 (UTC) X-Spam-Level: * Received: from localhost.localdomain (unknown [192.168.1.64]) by laika.paulk.fr (Postfix) with ESMTP id 919A9AC32C9; Sun, 1 Jun 2025 15:39:59 +0000 (UTC) From: Paul Kocialkowski To: u-boot@lists.denx.de Cc: Tom Rini , Jagan Teki , Andre Przywara , Icenowy Zheng , linux-sunxi@lists.linux.dev, Paul Kocialkowski Subject: [PATCH 2/6] sunxi: Add support for the Lichee Pi Zero with Dock Date: Sun, 1 Jun 2025 17:39:39 +0200 Message-ID: <20250601153943.2690123-3-contact@paulk.fr> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250601153943.2690123-1-contact@paulk.fr> References: <20250601153943.2690123-1-contact@paulk.fr> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O This adds a U-Boot config and device-tree build for the Lichee Pi Zero with Dock. Compared to the Lichee Pi Zero, it has an ethernet port (with internal PHY) so the EMAC driver and network support are enabled. Signed-off-by: Paul Kocialkowski --- arch/arm/dts/Makefile | 3 ++- configs/LicheePi_Zero_Dock_defconfig | 7 +++++++ 2 files changed, 9 insertions(+), 1 deletion(-) create mode 100644 configs/LicheePi_Zero_Dock_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 32b698a7f411..be6867ceae0e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -650,7 +650,8 @@ dtb-$(CONFIG_MACH_SUN8I_V3S) += \ sun8i-s3-elimo-initium.dtb \ sun8i-s3-pinecube.dtb \ sun8i-v3-sl631-imx179.dtb \ - sun8i-v3s-licheepi-zero.dtb + sun8i-v3s-licheepi-zero.dtb \ + sun8i-v3s-licheepi-zero-dock.dtb dtb-$(CONFIG_MACH_SUN8I_R528) += \ sun8i-t113s-mangopi-mq-r-t113.dtb dtb-$(CONFIG_MACH_SUN50I_H5) += \ diff --git a/configs/LicheePi_Zero_Dock_defconfig b/configs/LicheePi_Zero_Dock_defconfig new file mode 100644 index 000000000000..ec172d98b65e --- /dev/null +++ b/configs/LicheePi_Zero_Dock_defconfig @@ -0,0 +1,7 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero-dock" +CONFIG_SPL=y +CONFIG_MACH_SUN8I_V3S=y +# CONFIG_HAS_ARMV7_SECURE_BASE is not set +CONFIG_SUN8I_EMAC=y From patchwork Sun Jun 1 15:39:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Kocialkowski X-Patchwork-Id: 1639 Received: from leonov.paulk.fr (leonov.paulk.fr [185.233.101.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB77223CE for ; Sun, 1 Jun 2025 15:41:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.233.101.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748792514; cv=none; b=CCGXKzZ5WOCV2HPDqKMfN28DAQNMtJ8kyJi5Vim0iAWC+quc8duNBv+JwOFmySVP6bkD7Y5/UwUf+HEotpn7hoLO3CUWqL5ExatvjxpqBJn9sNHGhhZCJ4D8ukwQdinLQBN+sI39fbxP0i7NuMvxLt2+8XQ6z+AUMki+HfRxS6Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748792514; c=relaxed/simple; bh=sSkFbKb8yfOx865iwJAQIHvUwl1hycDIivP9OHa1f0U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IVEGwdyWhBrF8BJDJtnEXVPYme3PA29UCu6qWxICwYCDUhyVd0GSgMNRgsA31l7j2AFgDFwnS4KDex0NVXNhQ+Hpgi7qSfGNA/ayp9pijDCLopHApcMgpX7trEXauJ1duatyTC40y4D/Yr1/O/VLzHTMr/2mh3s5V/woZUsjQzU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=paulk.fr; spf=pass smtp.mailfrom=paulk.fr; arc=none smtp.client-ip=185.233.101.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=paulk.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=paulk.fr Received: from laika.paulk.fr (12.234.24.109.rev.sfr.net [109.24.234.12]) by leonov.paulk.fr (Postfix) with ESMTPS id 12A271F00047 for ; Sun, 1 Jun 2025 15:41:50 +0000 (UTC) Received: by laika.paulk.fr (Postfix, from userid 65534) id 34DC6AC32E7; Sun, 1 Jun 2025 15:41:49 +0000 (UTC) X-Spam-Level: * Received: from localhost.localdomain (unknown [192.168.1.64]) by laika.paulk.fr (Postfix) with ESMTP id CCD17AC32DD; Sun, 1 Jun 2025 15:39:59 +0000 (UTC) From: Paul Kocialkowski To: u-boot@lists.denx.de Cc: Tom Rini , Jagan Teki , Andre Przywara , Icenowy Zheng , linux-sunxi@lists.linux.dev, Paul Kocialkowski Subject: [PATCH 3/6] sunxi: Split V3/S3 support from V3s Date: Sun, 1 Jun 2025 17:39:40 +0200 Message-ID: <20250601153943.2690123-4-contact@paulk.fr> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250601153943.2690123-1-contact@paulk.fr> References: <20250601153943.2690123-1-contact@paulk.fr> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O There are significant differences between the V3 and V3s that are relevant for U-Boot support: a different DRAM driver, AXP209 support and extra UART1 pins. To avoid overwriting V3s defaults that do not apply to V3 in board configs, split off V3/S3 support as a separate MACH and pick-up all relevant V3s-specific choices with it. Also update the pinecube config to reflect the updated config options. Signed-off-by: Paul Kocialkowski --- arch/arm/dts/Makefile | 5 ++-- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 1 + arch/arm/mach-sunxi/Kconfig | 27 ++++++++++++++++----- arch/arm/mach-sunxi/board.c | 3 ++- arch/arm/mach-sunxi/cpu_info.c | 2 ++ arch/arm/mach-sunxi/dram_sunxi_dw.c | 4 +-- arch/arm/mach-sunxi/spl_spi_sunxi.c | 1 + board/sunxi/board.c | 2 +- configs/pinecube_defconfig | 4 +-- drivers/clk/sunxi/Kconfig | 2 +- drivers/phy/allwinner/Kconfig | 2 +- drivers/pinctrl/sunxi/Kconfig | 2 +- drivers/power/Kconfig | 4 +-- 13 files changed, 39 insertions(+), 20 deletions(-) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index be6867ceae0e..ba57284cda8a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -646,10 +646,11 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \ sun8i-r40-oka40i-c.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v40-bananapi-m2-berry.dtb -dtb-$(CONFIG_MACH_SUN8I_V3S) += \ +dtb-$(CONFIG_MACH_SUN8I_V3) += \ sun8i-s3-elimo-initium.dtb \ sun8i-s3-pinecube.dtb \ - sun8i-v3-sl631-imx179.dtb \ + sun8i-v3-sl631-imx179.dtb +dtb-$(CONFIG_MACH_SUN8I_V3S) += \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb dtb-$(CONFIG_MACH_SUN8I_R528) += \ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index f023a4cfd934..4863220d89bc 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -13,6 +13,7 @@ #if defined(CONFIG_SUNXI_GEN_SUN6I) && \ !defined(CONFIG_MACH_SUN8I_R40) && \ + !defined(CONFIG_MACH_SUN8I_V3) && \ !defined(CONFIG_MACH_SUN8I_V3S) #define SUNXI_SRAM_A2_BASE 0x00040000 #ifdef CONFIG_MACH_SUN8I_H3 diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 8b43fd176dc0..742ec17f9767 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -400,8 +400,20 @@ config MACH_SUN8I_R528 select SUPPORT_SPL select DRAM_SUN20I_D1 +config MACH_SUN8I_V3 + bool "sun8i (Allwinner V3/S3)" + select CPU_V7A + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select ARCH_SUPPORT_PSCI + select SUNXI_GEN_SUN6I + select SUNXI_DRAM_DW + select SUNXI_DRAM_DW_16BIT + select SUPPORT_SPL + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT + config MACH_SUN8I_V3S - bool "sun8i (Allwinner V3/V3s/S3/S3L)" + bool "sun8i (Allwinner V3s)" select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT @@ -472,6 +484,7 @@ config MACH_SUN8I default y if MACH_SUN8I_A83T default y if MACH_SUNXI_H3_H5 default y if MACH_SUN8I_R40 + default y if MACH_SUN8I_V3 default y if MACH_SUN8I_V3S config RESERVE_ALLWINNER_BOOT0_HEADER @@ -592,7 +605,7 @@ config DRAM_CLK default 792 if MACH_SUN9I default 648 if MACH_SUN8I_R40 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \ - MACH_SUN8I_V3S + MACH_SUN8I_V3 || MACH_SUN8I_V3S default 312 if MACH_SUN6I || MACH_SUN8I default 672 if MACH_SUN50I default 744 if MACH_SUN50I_H6 @@ -617,7 +630,7 @@ config DRAM_ZQ default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \ MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T default 127 if MACH_SUN7I - default 14779 if MACH_SUN8I_V3S + default 14779 if MACH_SUN8I_V3 || MACH_SUN8I_V3S default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6 default 4145117 if MACH_SUN9I default 3881915 if MACH_SUN50I @@ -743,7 +756,7 @@ config SYS_SOC config SUNXI_MINIMUM_DRAM_MB int "minimum DRAM size" default 32 if MACH_SUNIV - default 64 if MACH_SUN8I_V3S + default 64 if MACH_SUN8I_V3 || MACH_SUN8I_V3S default 256 ---help--- Minimum DRAM size expected on the board. Traditionally we assumed @@ -784,7 +797,8 @@ config MMC_SUNXI_SLOT_EXTRA config I2C0_ENABLE bool "Enable I2C/TWI controller 0" - default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40 + default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \ + MACH_SUN8I_R40 || MACH_SUN8I_V3 default n if MACH_SUN6I || MACH_SUN8I select CMD_I2C ---help--- @@ -829,6 +843,7 @@ config VIDEO_SUNXI depends on !MACH_SUN8I_A83T depends on !MACH_SUNXI_H3_H5 depends on !MACH_SUN8I_R40 + depends on !MACH_SUN8I_V3 depends on !MACH_SUN8I_V3S depends on !MACH_SUN9I depends on !MACH_SUN50I @@ -1052,7 +1067,7 @@ config SPL_STACK_R_ADDR config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN8I_V3S || SUN50I_GEN_H6 || MACH_SUNIV || SUNXI_GEN_NCAT2 + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN8I_V3 || MACH_SUN8I_V3S || SUN50I_GEN_H6 || MACH_SUNIV || SUNXI_GEN_NCAT2 help Enable support for SPI Flash. This option allows SPL to read from sunxi SPI Flash. It uses the same method as the boot ROM, so does diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index b1bf51f40c5c..1b721791635e 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -141,7 +141,8 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S) +#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN8I_V3) || \ + defined(CONFIG_MACH_SUN8I_V3S)) sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0); sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c index 310dca06e57e..1c6ef4b402fa 100644 --- a/arch/arm/mach-sunxi/cpu_info.c +++ b/arch/arm/mach-sunxi/cpu_info.c @@ -90,6 +90,8 @@ int print_cpuinfo(void) printf("CPU: Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id()); #elif defined CONFIG_MACH_SUN8I_R40 printf("CPU: Allwinner R40 (SUN8I %04x)\n", sunxi_get_sram_id()); +#elif defined CONFIG_MACH_SUN8I_V3 + printf("CPU: Allwinner V3/S3 (SUN8I %04x)\n", sunxi_get_sram_id()); #elif defined CONFIG_MACH_SUN8I_V3S printf("CPU: Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id()); #elif defined CONFIG_MACH_SUN8I_R528 diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index 4ed295909ceb..bf89509107b2 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -851,7 +851,7 @@ unsigned long sunxi_dram_init(void) .dx_read_delays = SUN8I_H3_DX_READ_DELAYS, .dx_write_delays = SUN8I_H3_DX_WRITE_DELAYS, .ac_delays = SUN8I_H3_AC_DELAYS, -#elif defined(CONFIG_MACH_SUN8I_V3S) +#elif defined(CONFIG_MACH_SUN8I_V3) || defined(CONFIG_MACH_SUN8I_V3S) .dx_read_delays = SUN8I_V3S_DX_READ_DELAYS, .dx_write_delays = SUN8I_V3S_DX_WRITE_DELAYS, .ac_delays = SUN8I_V3S_AC_DELAYS, @@ -878,7 +878,7 @@ unsigned long sunxi_dram_init(void) uint16_t socid = SOCID_H3; #elif defined(CONFIG_MACH_SUN8I_R40) uint16_t socid = SOCID_R40; -#elif defined(CONFIG_MACH_SUN8I_V3S) +#elif defined(CONFIG_MACH_SUN8I_V3) || defined(CONFIG_MACH_SUN8I_V3S) uint16_t socid = SOCID_V3S; #elif defined(CONFIG_MACH_SUN50I) uint16_t socid = SOCID_A64; diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 5f72e809952b..0e23bacdcaf0 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -141,6 +141,7 @@ static bool is_sun6i_gen_spi(void) return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) || IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) || + IS_ENABLED(CONFIG_MACH_SUN8I_V3) || IS_ENABLED(CONFIG_MACH_SUN8I_V3S); } diff --git a/board/sunxi/board.c b/board/sunxi/board.c index ac9cefc6eac9..4f0ceb319f32 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -68,7 +68,7 @@ void i2c_init_board(void) sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); clock_twi_onoff(0, 1); -#elif defined(CONFIG_MACH_SUN8I_V3S) +#elif defined(CONFIG_MACH_SUN8I_V3) || defined(CONFIG_MACH_SUN8I_V3S) sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0); clock_twi_onoff(0, 1); diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig index 7567a6aa7394..ea40d227bd53 100644 --- a/configs/pinecube_defconfig +++ b/configs/pinecube_defconfig @@ -2,11 +2,9 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube" CONFIG_SPL=y -CONFIG_MACH_SUN8I_V3S=y -CONFIG_SUNXI_DRAM_DDR3_1333=y +CONFIG_MACH_SUN8I_V3=y CONFIG_DRAM_CLK=504 CONFIG_DRAM_ODT_EN=y -CONFIG_I2C0_ENABLE=y # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_SPL_I2C=y CONFIG_NO_NET=y diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index f44db76c1823..620f330ea169 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -68,7 +68,7 @@ config CLK_SUN8I_R40 config CLK_SUN8I_V3S bool "Clock driver for Allwinner V3S" - default MACH_SUN8I_V3S + default MACH_SUN8I_V3 || MACH_SUN8I_V3S help This enables common clock driver support for platforms based on Allwinner V3S SoC. diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig index bb0bd8d5f812..8b995bde041d 100644 --- a/drivers/phy/allwinner/Kconfig +++ b/drivers/phy/allwinner/Kconfig @@ -5,7 +5,7 @@ config PHY_SUN4I_USB bool "Allwinner Sun4I USB PHY driver" depends on ARCH_SUNXI depends on !MACH_SUN9I - default n if MACH_SUN8I_V3S + default n if MACH_SUN8I_V3 || MACH_SUN8I_V3S default y select DM_REGULATOR select PHY diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 65e8192a99a1..1106102a5eae 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -76,7 +76,7 @@ config PINCTRL_SUN8I_H3_R config PINCTRL_SUN8I_V3S bool "Support for the Allwinner V3s PIO" - default MACH_SUN8I_V3S + default MACH_SUN8I_V3 || MACH_SUN8I_V3S select PINCTRL_SUNXI config PINCTRL_SUN9I_A80 diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index eed65058e667..08369bf833e4 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -54,7 +54,7 @@ source "drivers/power/regulator/Kconfig" choice prompt "Select Sunxi PMIC Variant" depends on ARCH_SUNXI - default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I + default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_V3 default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40 default AXP818_POWER if MACH_SUN8I_A83T default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_V3S @@ -75,7 +75,7 @@ config AXP152_POWER config AXP209_POWER bool "axp209 pmic support" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_V3S + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_V3 select AXP_PMIC_BUS select CMD_POWEROFF ---help--- From patchwork Sun Jun 1 15:39:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Kocialkowski X-Patchwork-Id: 1638 Received: from leonov.paulk.fr (leonov.paulk.fr [185.233.101.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 191E623CE for ; Sun, 1 Jun 2025 15:42:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.233.101.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748792536; cv=none; b=bywi8guX8lPxk0HaZ0hNRdZoQfNH2gNLjpCv7lI/h70bjLlt95zoys3R6N4EeRhDhHCfP+Z5RyCJ2x1e5No/Smk2tV13Y50AHLbPVeOrhjP9wjINcIeDA/SKWatQBkfxz/U7G/xseEmhbWZ2Xt99g2gn+fKOCBMt2wSJSjlhh+s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748792536; c=relaxed/simple; bh=friCtozI9WaJ6bcx1pkfLMJT7Q5c123ko5In3p5CxDc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lg/TPL3/vqYPiOZ90GqafepI22Ql+Oo4t1z+Wwd9eFLCpePPIaewwSmVk9IL2PmAKKNyUK9sSf65L82l1zcAPF9WXXyfdcGQ+TNvSErZpuLIsWgikYUi+QC0VpIXGBR/LYQXkhKuTpX94wvsOaNsYYBtBcfi7sPXWJUC3a/4hL8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=paulk.fr; spf=pass smtp.mailfrom=paulk.fr; arc=none smtp.client-ip=185.233.101.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=paulk.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=paulk.fr Received: from laika.paulk.fr (12.234.24.109.rev.sfr.net [109.24.234.12]) by leonov.paulk.fr (Postfix) with ESMTPS id E9A481F0004B for ; Sun, 1 Jun 2025 15:42:11 +0000 (UTC) Received: by laika.paulk.fr (Postfix, from userid 65534) id 73B36AC32ED; Sun, 1 Jun 2025 15:42:11 +0000 (UTC) X-Spam-Level: * Received: from localhost.localdomain (unknown [192.168.1.64]) by laika.paulk.fr (Postfix) with ESMTP id 04BB0AC32DF; Sun, 1 Jun 2025 15:39:59 +0000 (UTC) From: Paul Kocialkowski To: u-boot@lists.denx.de Cc: Tom Rini , Jagan Teki , Andre Przywara , Icenowy Zheng , linux-sunxi@lists.linux.dev, Paul Kocialkowski Subject: [PATCH 4/6] sunxi: pinecube: Enable EMAC and network support Date: Sun, 1 Jun 2025 17:39:41 +0200 Message-ID: <20250601153943.2690123-5-contact@paulk.fr> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250601153943.2690123-1-contact@paulk.fr> References: <20250601153943.2690123-1-contact@paulk.fr> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O The pinecube has an ethernet connector which uses the EMAC and internal PHY of the chip. Enable it in the config. Signed-off-by: Paul Kocialkowski --- configs/pinecube_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig index ea40d227bd53..2741e7ed9079 100644 --- a/configs/pinecube_defconfig +++ b/configs/pinecube_defconfig @@ -7,13 +7,13 @@ CONFIG_DRAM_CLK=504 CONFIG_DRAM_ODT_EN=y # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_SPL_I2C=y -CONFIG_NO_NET=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 CONFIG_MTD=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SUN8I_EMAC=y CONFIG_AXP209_POWER=y CONFIG_AXP_DCDC2_VOLT=1250 CONFIG_AXP_DCDC3_VOLT=3300 From patchwork Sun Jun 1 15:39:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Kocialkowski X-Patchwork-Id: 1637 Received: from leonov.paulk.fr (leonov.paulk.fr [185.233.101.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 358B723CE for ; Sun, 1 Jun 2025 15:42:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.233.101.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748792557; cv=none; b=ZT0BgCC8NGUOsymQCzSddMif5VBEMLQSnFxo1ZG16SdG8eMlgTXeVB/05LUsHSZFPnExxangcJN5F3wpCg/u1IwaxbzAV4Ic003LcYEA1l8noGdzgFdNDVMw63iw8Mpo7+Kn1XsCYNDhLlmGUxUKxV967si+2ILeDvgvMQ4yDe4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748792557; c=relaxed/simple; bh=2otS0b/RwtQt1DfxCSkwJQdfafehJPGTuKtTlGbWBTE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Azg2dnuBbczHG9igAEyXsV/8zM497qvCVzvwwc6hunZe7atBbvHdnzngdOXkuXcb9z198Q27mSwkoVurFAe+v17phhKHCrEPG+xLn9nF7NzKGcp3KnDq6TzUZQ793MCA8GMpHXQnx23doyw7GDss2a2FtW6oUVLzkZc/D4t53/0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=paulk.fr; spf=pass smtp.mailfrom=paulk.fr; arc=none smtp.client-ip=185.233.101.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=paulk.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=paulk.fr Received: from laika.paulk.fr (12.234.24.109.rev.sfr.net [109.24.234.12]) by leonov.paulk.fr (Postfix) with ESMTPS id DE5631F0004D for ; Sun, 1 Jun 2025 15:42:33 +0000 (UTC) Received: by laika.paulk.fr (Postfix, from userid 65534) id 4C687AC32F2; Sun, 1 Jun 2025 15:42:33 +0000 (UTC) X-Spam-Level: * Received: from localhost.localdomain (unknown [192.168.1.64]) by laika.paulk.fr (Postfix) with ESMTP id 3B18DAC32E1; Sun, 1 Jun 2025 15:40:00 +0000 (UTC) From: Paul Kocialkowski To: u-boot@lists.denx.de Cc: Tom Rini , Jagan Teki , Andre Przywara , Icenowy Zheng , linux-sunxi@lists.linux.dev, Paul Kocialkowski Subject: [PATCH 5/6] power: axp: Fixup default voltages for V3/S3 Date: Sun, 1 Jun 2025 17:39:42 +0200 Message-ID: <20250601153943.2690123-6-contact@paulk.fr> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250601153943.2690123-1-contact@paulk.fr> References: <20250601153943.2690123-1-contact@paulk.fr> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O The default voltages used by V3/S3 boards differs from the usual AXP209 default that are used on older chips. Correct the default voltages based on the Allwinner reference design schematics, which match boards found in the wild such as the Pinecube. Signed-off-by: Paul Kocialkowski --- configs/pinecube_defconfig | 3 --- drivers/power/Kconfig | 8 ++++++-- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig index 2741e7ed9079..8bd14ad90f6d 100644 --- a/configs/pinecube_defconfig +++ b/configs/pinecube_defconfig @@ -14,8 +14,5 @@ CONFIG_SYS_I2C_SPEED=400000 CONFIG_MTD=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y -CONFIG_AXP209_POWER=y -CONFIG_AXP_DCDC2_VOLT=1250 -CONFIG_AXP_DCDC3_VOLT=3300 CONFIG_CONS_INDEX=3 CONFIG_SPI=y diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 08369bf833e4..24b36be4c6cf 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -176,10 +176,11 @@ config AXP_DCDC2_VOLT int "axp pmic dcdc2 voltage" depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP313_POWER || AXP717_POWER || AXP803_POWER default 900 if AXP818_POWER - default 1400 if AXP152_POWER || AXP209_POWER + default 1400 if AXP152_POWER || (AXP209_POWER && !MACH_SUN8I_V3) default 1000 if AXP313_POWER default 1000 if AXP717_POWER default 1000 if AXP803_POWER + default 1250 if MACH_SUN8I_V3 default 1200 if MACH_SUN6I default 1100 if MACH_SUN8I default 0 if MACH_SUN9I @@ -192,6 +193,7 @@ config AXP_DCDC2_VOLT On A80 boards dcdc2 powers the GPU and can be left off. On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V. On R40 boards dcdc2 is VDD-CPU and should be 1.1V + On V3/S3 boards dcdc2 is VDD-CPU/VDD-SYS and should be 1.25V. On boards using the AXP313 or AXP717 it's often VDD-CPU. config AXP_DCDC3_VOLT @@ -199,9 +201,10 @@ config AXP_DCDC3_VOLT depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP313_POWER || AXP717_POWER default 900 if AXP809_POWER || AXP818_POWER default 1500 if AXP152_POWER - default 1250 if AXP209_POWER + default 1250 if (AXP209_POWER && !MACH_SUN8I_V3) default 1100 if AXP313_POWER default 1100 if MACH_SUN8I_R40 + default 3300 if MACH_SUN8I_V3 default 1200 if MACH_SUN6I || MACH_SUN8I ---help--- Set the voltage (mV) to program the axp pmic dcdc3 at, set to 0 to @@ -213,6 +216,7 @@ config AXP_DCDC3_VOLT On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V. On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V. On R40 boards dcdc3 is VDD-SYS and VDD-GPU and should be 1.1V. + On V3/S3 boards dcdc3 is VCC-IO and should be 3.3V. On boards using the AXP313 or AXP717 it's often VDD-DRAM and should be 1.1V for LPDDR4. From patchwork Sun Jun 1 15:39:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Kocialkowski X-Patchwork-Id: 1636 Received: from leonov.paulk.fr (leonov.paulk.fr [185.233.101.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C69D748F for ; Sun, 1 Jun 2025 15:43:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.233.101.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748792590; cv=none; b=N+f44B8pHFNG1/+SGOApNEDO0K04vdlg0092wuEOhh3r3C8eeuzkuPP6RqV/8dbsJ2Q178b9drhZriIyT8wM4AJfZm+NP6ncm0ADbMMHFwBkGVlNE0ywqUdU0pRBGOVr8K+azFNQmSv2Bw4sABWW2I7fArWodiDxyc3uBKhmq8U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748792590; c=relaxed/simple; bh=oa1YvIPvW4cdHZum0m45M7KIQTkPhZmn0qPCCmAXdFI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kfNQ4KvCb+10swc5hZUV8bP0wJfTBpExMuhvMGh6MEhbMuPw2kEO6gIKTV14AlIAYfHO0QwnVBeSa9SlQU/FzvSGU8eTbwYuArWN/Ei4XdeF9HFSSZS3qXAJZKzBKLsJ22Y3+OJJ3uXQ5duzbRqUP5EszlzxycthWFWLwZVNY54= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=paulk.fr; spf=pass smtp.mailfrom=paulk.fr; arc=none smtp.client-ip=185.233.101.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=paulk.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=paulk.fr Received: from laika.paulk.fr (12.234.24.109.rev.sfr.net [109.24.234.12]) by leonov.paulk.fr (Postfix) with ESMTPS id 6F9E31F00047 for ; Sun, 1 Jun 2025 15:43:06 +0000 (UTC) Received: by laika.paulk.fr (Postfix, from userid 65534) id EA057AC32F6; Sun, 1 Jun 2025 15:43:05 +0000 (UTC) X-Spam-Level: * Received: from localhost.localdomain (unknown [192.168.1.64]) by laika.paulk.fr (Postfix) with ESMTP id 6703BAC32E3; Sun, 1 Jun 2025 15:40:00 +0000 (UTC) From: Paul Kocialkowski To: u-boot@lists.denx.de Cc: Tom Rini , Jagan Teki , Andre Przywara , Icenowy Zheng , linux-sunxi@lists.linux.dev, Paul Kocialkowski Subject: [PATCH 6/6] net: sun8i-emac: Add support for active-low leds with internal PHY Date: Sun, 1 Jun 2025 17:39:43 +0200 Message-ID: <20250601153943.2690123-7-contact@paulk.fr> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250601153943.2690123-1-contact@paulk.fr> References: <20250601153943.2690123-1-contact@paulk.fr> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O A device-tree property is already defined to indicate that the internal PHY should be used with active-low leds, which corresponds to a specific bit in the dedicated syscon register. Add support for setting this bit when the property is present. Signed-off-by: Paul Kocialkowski --- drivers/net/sun8i_emac.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 8433e7db2654..990a184e4b1f 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -176,6 +176,7 @@ struct sun8i_eth_pdata { u32 reset_delays[3]; int tx_delay_ps; int rx_delay_ps; + bool leds_active_low; }; static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) @@ -287,7 +288,8 @@ static void sun8i_adjust_link(struct emac_eth_dev *priv, writel(v, priv->mac_reg + EMAC_CTL0); } -static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg) +static u32 sun8i_emac_set_syscon_ephy(struct sun8i_eth_pdata *pdata, + struct emac_eth_dev *priv, u32 reg) { if (priv->use_internal_phy) { /* H3 based SoC's that has an Internal 100MBit PHY @@ -295,6 +297,10 @@ static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg) */ reg &= ~H3_EPHY_DEFAULT_MASK; reg |= H3_EPHY_DEFAULT_VALUE; + + if (pdata->leds_active_low) + reg |= H3_EPHY_LED_POL; + reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT; reg &= ~H3_EPHY_SHUTDOWN; return reg | H3_EPHY_SELECT; @@ -314,7 +320,7 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, reg = readl(priv->sysctl_reg); - reg = sun8i_emac_set_syscon_ephy(priv, reg); + reg = sun8i_emac_set_syscon_ephy(pdata, priv, reg); reg &= ~(SC_ETCS_MASK | SC_EPIT); if (priv->variant->support_rmii) @@ -859,6 +865,10 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev) printf("%s: Invalid RX delay value %d\n", __func__, sun8i_pdata->rx_delay_ps); + sun8i_pdata->leds_active_low = + fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), + "allwinner,leds-active-low"); + if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), "snps,reset-active-low")) reset_flags |= GPIOD_ACTIVE_LOW;