From patchwork Thu Apr 17 00:05:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1775 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 736FB8F64 for ; Thu, 17 Apr 2025 00:06:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744848399; cv=none; b=Wf0pzbgz9DWswcik7KpaA5tUIu/NHHIGPMgHhel+KxdyGSF7RAFf7cNlwWvYz/r6BQPeoiIO7ifOYKwo/PEqdgA3Eoepy5zXZz4cw7fdrz91v+EHVdWrHQG4YZuFjV7HZPKj1vbtrcYb5vrkSHP1fUSKMiQr0XlkW+UoM9QZGYE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744848399; c=relaxed/simple; bh=f4A5PrJngWiZhrgTQs0iYjJPBKD2kTKqOYgFNktrUB0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=t1qi2fwG/mnn+sfob35gBRXn9E8MxuNCGZgS70hKTzv/dgWLdh4Xp+jhBlLCu5LgBsKXkYKr1rLcEnQmn6tX7dUIr4pdib30ibjMrdzO1sPzzZheZiQKTHG2Y16SpfZFH+9HA37V0sLsXtEUKWAUDNBy24L8puECCRBSoNPUiAE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5771F153B; Wed, 16 Apr 2025 17:06:33 -0700 (PDT) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 894A43F66E; Wed, 16 Apr 2025 17:06:34 -0700 (PDT) From: Andre Przywara To: Jagan Teki , u-boot@lists.denx.de Cc: Yixun Lan , Tom Rini , Jernej Skrabec , Samuel Holland , linux-sunxi@lists.linux.dev Subject: [PATCH v2 1/3] sunxi: fix return_to_fel() prototype Date: Thu, 17 Apr 2025 01:05:37 +0100 Message-ID: <20250417000539.3709-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250417000539.3709-1-andre.przywara@arm.com> References: <20250417000539.3709-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O In some sys_proto header file we describe the prototype of the return_to_fel() function, which is implemented in assembly. The order of the arguments listed there is wrong: the stack pointer is expected in r0/w0, and the return address in r1/w1. Fix the order to match the code. This is purely cosmetic, as the callers and the assembly code are already agreeing on this. Signed-off-by: Andre Przywara --- arch/arm/include/asm/arch-sunxi/sys_proto.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h index 92c7721a530..43ee0fdd558 100644 --- a/arch/arm/include/asm/arch-sunxi/sys_proto.h +++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h @@ -17,10 +17,10 @@ void sdelay(unsigned long); * This returns back into the BROM after U-Boot SPL has performed its initial * init. It uses the provided lr and sp to do so. * - * @lr: BROM link register value (return address) * @sp: BROM stack pointer + * @lr: BROM link register value (return address) */ -void return_to_fel(uint32_t lr, uint32_t sp); +void return_to_fel(uint32_t sp, uint32_t lr); /* Board / SoC level designware gmac init */ #if !defined CONFIG_XPL_BUILD && defined CONFIG_SUN7I_GMAC From patchwork Thu Apr 17 00:05:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1774 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F1DFA18EAB for ; Thu, 17 Apr 2025 00:06:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744848400; cv=none; b=gqfZ86PoKEwpm8+stexucb8GjZaVWIab/I62AziSMAmZvRdWQ1xcpN4L1CrFvj1WsLWl7WCxhk4ML/f/LD+IDhUHM1K2ivTVs11XAsqeYbPGMtkPp1jNjrhlUXLJNoX+ewQDbW13W+luw/CF5E3Umrb95Z8dMUENRJCt4osTaBM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744848400; c=relaxed/simple; bh=eaqgvtg1ladvxw6CdFuaG5ul93bH8xZ9B5ARG4uEuo8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KSHA0KYJeiPx+AOnhGmEjkW35jcK7NAakUVcDtX9ioVDM4etX1hmnQvU0soLVvSI6CdZfdBePei5LlcaxfTFz6ZbVeptQ6CVC3frA9/dj2MNeLxfjaRTVUoCWDJIMZ0yT3krLR48lfeBWSc7BZGfPgh88FTLmv0PJu18gjIcqIg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AAC411595; Wed, 16 Apr 2025 17:06:34 -0700 (PDT) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DD5083F66E; Wed, 16 Apr 2025 17:06:35 -0700 (PDT) From: Andre Przywara To: Jagan Teki , u-boot@lists.denx.de Cc: Yixun Lan , Tom Rini , Jernej Skrabec , Samuel Holland , linux-sunxi@lists.linux.dev Subject: [PATCH v2 2/3] sunxi: add "fake" FEL pin support Date: Thu, 17 Apr 2025 01:05:38 +0100 Message-ID: <20250417000539.3709-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250417000539.3709-1-andre.przywara@arm.com> References: <20250417000539.3709-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O Some boards with Allwinner SoCs feature a "FEL" key, sometimes also labelled "uboot", which triggers the BootROM FEL mode, when pressed upon power-on or reset. This allows to access the SoC's memory via USB OTG, and to upload and execute code. There is a tool to upload our U-Boot image and immediately boot it, when the SoC is in FEL mode. To mimic this convenient behaviour on boards without such a dedicated key, we can query a GPIO pin very early in the SPL boot, then trigger the BootROM FEL routine. There has not been much of a SoC or board setup at this point, so we enter the BROM in a rather pristine state still. On 64-bit SoCs the required AArch32 reset guarantees a clean CPU state anyway. Any GPIO can be used for that, the signal is expected to be active low, consequently we enable the pull-up resistors for that pin. A board (or a user) is expected to specify the GPIO name using the CONFIG_SUNXI_FAKE_FEL_PIN Kconfig variable. When this variable is not set, the compiler will optimise away the call. Call the code first thing in board_init_f(), which is the first sunxi specific C routine. Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/Kconfig | 10 ++++++++++ arch/arm/mach-sunxi/board.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index ab432390d3c..f1cfdb548bc 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -825,6 +825,16 @@ config USB3_VBUS_PIN ---help--- See USB1_VBUS_PIN help text. +config SUNXI_FAKE_FEL_PIN + string "fake FEL GPIO pin" + default "" + ---help--- + Define a GPIO that shall force entering FEL mode when a button + connected to this pin is pressed at boot time. This must be an + active low signal, the internal pull-up resistors are activated. + This takes a string in the format understood by sunxi_name_to_gpio, + e.g. PH1 for pin 1 of port H. + config I2C0_ENABLE bool "Enable I2C/TWI controller 0" default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 701899ee4b2..4ee0b333176 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -457,8 +457,39 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) return result; } +static void check_fake_fel_button(void) +{ + u32 brom_entry = 0x20; + int pin, value, mux; + + /* check for empty string at compile time */ + if (sizeof(CONFIG_SUNXI_FAKE_FEL_PIN) == sizeof("")) + return; + + pin = sunxi_name_to_gpio(CONFIG_SUNXI_FAKE_FEL_PIN); + if (pin < 0) + return; + + mux = sunxi_gpio_get_cfgpin(pin); + sunxi_gpio_set_cfgpin(pin, SUNXI_GPIO_INPUT); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + value = gpio_get_value(pin); + sunxi_gpio_set_cfgpin(pin, mux); + + if (value) + return; + + /* Older SoCs maps the BootROM high in the address space. */ + if (fel_stash.sctlr & BIT(13)) + brom_entry |= 0xffff0000; + + return_to_fel(0, brom_entry); +} + void board_init_f(ulong dummy) { + check_fake_fel_button(); + sunxi_sram_init(); /* Enable non-secure access to some peripherals */ From patchwork Thu Apr 17 00:05:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1773 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2BF64BA34 for ; Thu, 17 Apr 2025 00:06:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744848401; cv=none; b=gwJMHO8MLmhjaC+MTsi+BD8U8ZM5rhB+w4BNxXu17aIh3rKvtKMZo3whmHCQxsEXud5vG4j/CQaBD40mq40ShQEil5kiuo37wi0lDH6KiVh2ll+Qz86phl1eKHklzAoM+0pjsCv4OHCWv8xFG3CEEV28bOblbF9cEsYUNqzdI9E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744848401; c=relaxed/simple; bh=x7VVaSZpbp0xEvnGUTjsclDs6sRhLbwB5Sb487OXmws=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=muYNhfq+toiufuuMj1TOCjKqL1POFMczkBK3mI1BaaICk5g4g2OyQhyMHi4Q8+YmbR3B8PlzNRGEY9WI80VEvxjiiduC3oo2RIuXby9wgWYbe+934LTgO7dL9IQZdn7gFn0TKiNDIU7LA4SQ1Gy1I+U1Nr21q4A6KiVCcR6ewdE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0A2C81764; Wed, 16 Apr 2025 17:06:36 -0700 (PDT) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3C9D13F66E; Wed, 16 Apr 2025 17:06:37 -0700 (PDT) From: Andre Przywara To: Jagan Teki , u-boot@lists.denx.de Cc: Yixun Lan , Tom Rini , Jernej Skrabec , Samuel Holland , linux-sunxi@lists.linux.dev Subject: [PATCH v2 3/3] sunxi: x96_mate: Add "fake" FEL key definition Date: Thu, 17 Apr 2025 01:05:39 +0100 Message-ID: <20250417000539.3709-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250417000539.3709-1-andre.przywara@arm.com> References: <20250417000539.3709-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Status: O The X96 Mate TV box features a hidden button behind the earphone jack, which can be reached with a non-conductive tools like a toothpick. On the vendor firmware, holding this button during reset or power on triggers the BootROM FEL mode, though it's not an hardware FEL button, but a feature of Allwinner's "boot0" firmware. Mimic this behaviour by specifying the GPIO name (PH9) for our "fake" FEL button feature in the board's defconfig file, which actually enters FEL mode much faster than the vendor firmware. Signed-off-by: Andre Przywara --- configs/x96_mate_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig index bd9b611d6f5..b54d0bb5608 100644 --- a/configs/x96_mate_defconfig +++ b/configs/x96_mate_defconfig @@ -11,6 +11,7 @@ CONFIG_DRAM_SUNXI_TPR11=0xffffdddd CONFIG_DRAM_SUNXI_TPR12=0xfedf7557 CONFIG_MACH_SUN50I_H616=y CONFIG_SUNXI_DRAM_H616_DDR3_1333=y +CONFIG_SUNXI_FAKE_FEL_PIN="PH9" CONFIG_R_I2C_ENABLE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y