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Sun, 12 Oct 2025 17:05:28 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 01/20] iommu: Lock group->mutex in iommu_deferred_attach() Date: Sun, 12 Oct 2025 17:04:58 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: asahi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3C:EE_|IA1PR12MB6556:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b9185ca-84aa-4a27-39a7-08de09ec478c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: vN3bJGBS3zeTYl+olBOIhGmJi9yfUmB5qaGsuPfMuTZcVgfm9sMXo4I9LaSKsks4M6VCj1HGRubXgmBby7Oy4AfKFJQFTiOWV4YaOyivXdix80OUCRSDxxtHTmuHxXuOwdHJ/4kcATM5F8fhqE1kEL0CsVW3XaQOw/MSQu/m0wO1k8FEvLqDIvhzfpHb7I9zCExaV+tXWI4owUFCPcelqTHsMe48heLBGzuMj+fQh3COrABywARBbq2j6AA43s/VStsUm0VFhgSHj26/SQP/eyjI+2Y4BbZbK1WTxbFYviFKW1kTXM6RBCGPGZvVevcXHTPpZdVOGRL6HVg9lEqWBdTuRMV//6b2HW6+HzpeMuCtfF0dO2b+0jlRcaZ9moNN5cI1ozl3ZRnAh+p/1n6BCcypVy2lzBcKtrDOiyDSkQLaJStjJwDDW/2N1HwtS+Z8xodQRASMoqVSc8HlD6zvPF5JyeEjmnncaFOtHTjHf/jkDi9bErnB46sfFJfoWVNtLwSbY/u4mgezT2a+KyY3zx0kSPzouDPr19c+7jEET9bpMDizfEsFKVn8RAUw1sIHqrZETZNaxlqYVAUOus/aAJyXGqN4jnJZoPNmi0Af17IbKq8XG5LP0/Fyv0WB8iqve/BfHjBSa5/1RgS55vvZ+oHI7umtXQKLRhdlJDK0Go2nlXbnJAKn1T3ZoCP2AsQ0Wny1X+VQOIBszYMbeJSRD+Q6vbnY/o+b2T/3MDF+4Rn5HRme5WUAK5ncYfqMKLa7L+AVdqShgkI7LgZX5avVFT3Sxt0d62xFczMaXVP7dz23GZRnnnVlnDwwLB3Tu5fWx10ZSEbj2pQRB6w7nzFPPbZd3300VjFW4dWFk1bFj1BSYlzIBNVZTqGujdxJO6bpmXuEYwO34sSSMFZcTeEik0uektpquzTTrVLPEuFARDYMtxpUIDZOHF7h7EN1RJIVIykmYfLTJ35o0Q+TQbjm8EzoAulv/J51Rmh7H1EvMeVjayIgnzGThJmoBj75h8mLzaj+s8cD+jmoqYZpxixItS7dPVYw4RrSnw9BEmgCbGX8Xz9UY56OCh/4kh1ENnSqCKgqOrr6ejq27/KhybZl/2dxTujSkYlKIZYwdtfwGdeNfhXAXT9sCsxifs6G28tf0KcU74YFe9bIQvmVwZNwzkpRugVIspzI+1RnzZS8tu2xHMSObha5t/NNV+gEms/VIn/yMxlS1rI0BlPaXDIT+WR4Zw1HhVTdGbkK1pzBTpEpw0zvgPNSu3pp1sR4YL7vW0pqbUXwtKWeiLCU6Af9EXrfT1y8PgF8LInn0pp/26EKYigrnCDWdS54xgkxTu4vkCOPzxheg3HxlsOOuOpaSmSfnmbpDPI7QNzG0UApKNReF3KH26hTZPomfRK4fky7K7zXUoVCSt32TKLGVfoc85lx611b94E05ExA8uNtvAD8aCcYWFKr7oPWxce82x5YCAJSzAyUk3nq08iZ/8+nnMGEBPRihB0Owwj9seGqWiHVU/VyE/SMcTUt8OlX/dH7RhoLL5YPpHnGUjQfz1/GJU1y/u7ZM+LPpy0beowxg6g= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:05:54.9746 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3b9185ca-84aa-4a27-39a7-08de09ec478c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6556 Status: O The iommu_deferred_attach() function invokes __iommu_attach_device() while not holding the group->mutex, like other __iommu_attach_device() callers. Though there is no pratical bug being triggered so far, it would be better to apply the same locking to this __iommu_attach_device(), since the IOMMU drivers nowaday are more aware of the group->mutex -- some of them use the iommu_group_mutex_assert() function that could be potentially in the path of an attach_dev callback function invoked by the __iommu_attach_device(). The iommu_deferred_attach() will soon need to invoke a new domain op that must be locked with __iommu_attach_device under group->mutex. So, grab the mutex to guard __iommu_attach_device() like other callers. Reviewed-by: Jason Gunthorpe Reviewed-by: Kevin Tian Signed-off-by: Nicolin Chen --- drivers/iommu/iommu.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 2ca990dfbb884..170e522b5bda4 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -2185,10 +2185,17 @@ EXPORT_SYMBOL_GPL(iommu_attach_device); int iommu_deferred_attach(struct device *dev, struct iommu_domain *domain) { - if (dev->iommu && dev->iommu->attach_deferred) - return __iommu_attach_device(domain, dev, NULL); + /* + * This is called on the dma mapping fast path so avoid locking. This is + * racy, but we have an expectation that the driver will setup its DMAs + * inside probe while being single threaded to avoid racing. + */ + if (!dev->iommu || !dev->iommu->attach_deferred) + return 0; - return 0; + guard(mutex)(&dev->iommu_group->mutex); + + return __iommu_attach_device(domain, dev, NULL); } void iommu_detach_device(struct iommu_domain *domain, struct device *dev) From patchwork Mon Oct 13 00:04:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1901 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013028.outbound.protection.outlook.com [40.107.201.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD36C2A1BF; Mon, 13 Oct 2025 00:06:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.201.28 ARC-Seal: i=2; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:05:56.3213 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 78946808-a7f5-4dd5-b571-08de09ec4859 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6949 Status: O Add a new test_dev domain op for driver to test the compatibility between a domain and a device at the driver level, before calling into the actual attachment/replacement of a domain. Support pasid for set_dev_pasid call. Move existing core-level compatibility tests to a helper function. Invoke it prior to: * __iommu_attach_device() or its wrapper __iommu_device_set_domain() * __iommu_set_group_pasid() And keep them within the group->mutex, so drivers can simply move all the sanity and compatibility tests from their attach_dev callbacks to the new test_dev callbacks without concerning about a race condition. This may be a public API someday for VFIO/IOMMUFD to run a list of attach tests without doing any actual attachment, which may result in a list of failed tests. So encourage drivers to avoid printks to prevent kernel log spam. Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- include/linux/iommu.h | 17 +++++-- drivers/iommu/iommu.c | 111 ++++++++++++++++++++++++++++++------------ 2 files changed, 93 insertions(+), 35 deletions(-) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 801b2bd9e8d49..2ec99502dc29c 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -714,7 +714,12 @@ struct iommu_ops { /** * struct iommu_domain_ops - domain specific operations - * @attach_dev: attach an iommu domain to a device + * @test_dev: Test compatibility prior to an @attach_dev or @set_dev_pasid call. + * A driver-level callback of this op should do a thorough sanity, to + * make sure a device is compatible with the domain. So the following + * @attach_dev and @set_dev_pasid functions would likely succeed with + * only one exception due to a temporary failure like out of memory. + * It's suggested to avoid the kernel prints in this op. * Return: * * 0 - success * * EINVAL - can indicate that device and domain are incompatible due to @@ -722,11 +727,15 @@ struct iommu_ops { * driver shouldn't log an error, since it is legitimate for a * caller to test reuse of existing domains. Otherwise, it may * still represent some other fundamental problem - * * ENOMEM - out of memory - * * ENOSPC - non-ENOMEM type of resource allocation failures * * EBUSY - device is attached to a domain and cannot be changed * * ENODEV - device specific errors, not able to be attached * * - treated as ENODEV by the caller. Use is discouraged + * @attach_dev: attach an iommu domain to a device + * Return: + * * 0 - success + * * ENOMEM - out of memory + * * ENOSPC - non-ENOMEM type of resource allocation failures + * * - Use is discouraged * @set_dev_pasid: set or replace an iommu domain to a pasid of device. The pasid of * the device should be left in the old config in error case. * @map_pages: map a physically contiguous set of pages of the same size to @@ -751,6 +760,8 @@ struct iommu_ops { * @free: Release the domain after use. */ struct iommu_domain_ops { + int (*test_dev)(struct iommu_domain *domain, struct device *dev, + ioasid_t pasid, struct iommu_domain *old); int (*attach_dev)(struct iommu_domain *domain, struct device *dev, struct iommu_domain *old); int (*set_dev_pasid)(struct iommu_domain *domain, struct device *dev, diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 170e522b5bda4..95f0e2898b6b5 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -99,6 +99,9 @@ static int bus_iommu_probe(const struct bus_type *bus); static int iommu_bus_notifier(struct notifier_block *nb, unsigned long action, void *data); static void iommu_release_device(struct device *dev); +static int __iommu_domain_test_device(struct iommu_domain *domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old); static int __iommu_attach_device(struct iommu_domain *domain, struct device *dev, struct iommu_domain *old); static int __iommu_attach_group(struct iommu_domain *domain, @@ -642,6 +645,10 @@ static int __iommu_probe_device(struct device *dev, struct list_head *group_list if (group->default_domain) iommu_create_device_direct_mappings(group->default_domain, dev); if (group->domain) { + ret = __iommu_domain_test_device(group->domain, dev, + IOMMU_NO_PASID, NULL); + if (ret) + goto err_remove_gdev; ret = __iommu_device_set_domain(group, dev, group->domain, NULL, 0); if (ret) @@ -2185,6 +2192,8 @@ EXPORT_SYMBOL_GPL(iommu_attach_device); int iommu_deferred_attach(struct device *dev, struct iommu_domain *domain) { + int ret; + /* * This is called on the dma mapping fast path so avoid locking. This is * racy, but we have an expectation that the driver will setup its DMAs @@ -2195,6 +2204,10 @@ int iommu_deferred_attach(struct device *dev, struct iommu_domain *domain) guard(mutex)(&dev->iommu_group->mutex); + ret = __iommu_domain_test_device(domain, dev, IOMMU_NO_PASID, NULL); + if (ret) + return ret; + return __iommu_attach_device(domain, dev, NULL); } @@ -2262,6 +2275,53 @@ static bool domain_iommu_ops_compatible(const struct iommu_ops *ops, return false; } +/* + * Test if a future attach for a domain to the device will always fail. This may + * indicate that the device and the domain are incompatible in some way. Actual + * attach may still fail for some temporary failure like out of memory. + * + * If pasid != IOMMU_NO_PASID, it is meant to test a future set_dev_pasid call. + */ +static int __iommu_domain_test_device(struct iommu_domain *domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old) +{ + const struct iommu_ops *ops = dev_iommu_ops(dev); + struct iommu_group *group = dev->iommu_group; + + lockdep_assert_held(&group->mutex); + + if (!domain_iommu_ops_compatible(ops, domain)) + return -EINVAL; + + if (pasid != IOMMU_NO_PASID) { + struct group_device *gdev; + + if (!domain->ops->set_dev_pasid || !ops->blocked_domain || + !ops->blocked_domain->ops->set_dev_pasid) + return -EOPNOTSUPP; + /* + * Skip PASID validation for devices without PASID support + * (max_pasids = 0). These devices cannot issue transactions + * with PASID, so they don't affect group's PASID usage. + */ + for_each_group_device(group, gdev) { + if (gdev->dev->iommu->max_pasids > 0 && + pasid >= gdev->dev->iommu->max_pasids) + return -EINVAL; + } + } + + /* + * Domains that don't implement a test_dev callback function must have a + * simple domain attach behavior. The sanity above should be enough. + */ + if (!domain->ops->test_dev) + return 0; + + return domain->ops->test_dev(domain, dev, pasid, old); +} + static int __iommu_attach_group(struct iommu_domain *domain, struct iommu_group *group) { @@ -2272,8 +2332,7 @@ static int __iommu_attach_group(struct iommu_domain *domain, return -EBUSY; dev = iommu_group_first_dev(group); - if (!dev_has_iommu(dev) || - !domain_iommu_ops_compatible(dev_iommu_ops(dev), domain)) + if (!dev_has_iommu(dev)) return -EINVAL; return __iommu_group_set_domain(group, domain); @@ -2381,6 +2440,13 @@ static int __iommu_group_set_domain_internal(struct iommu_group *group, if (WARN_ON(!new_domain)) return -EINVAL; + for_each_group_device(group, gdev) { + ret = __iommu_domain_test_device(new_domain, gdev->dev, + IOMMU_NO_PASID, group->domain); + if (ret) + return ret; + } + /* * Changing the domain is done by calling attach_dev() on the new * domain. This switch does not have to be atomic and DMA can be @@ -3479,38 +3545,19 @@ int iommu_attach_device_pasid(struct iommu_domain *domain, { /* Caller must be a probed driver on dev */ struct iommu_group *group = dev->iommu_group; - struct group_device *device; - const struct iommu_ops *ops; void *entry; int ret; if (!group) return -ENODEV; - - ops = dev_iommu_ops(dev); - - if (!domain->ops->set_dev_pasid || - !ops->blocked_domain || - !ops->blocked_domain->ops->set_dev_pasid) - return -EOPNOTSUPP; - - if (!domain_iommu_ops_compatible(ops, domain) || - pasid == IOMMU_NO_PASID) + if (pasid == IOMMU_NO_PASID) return -EINVAL; mutex_lock(&group->mutex); - for_each_group_device(group, device) { - /* - * Skip PASID validation for devices without PASID support - * (max_pasids = 0). These devices cannot issue transactions - * with PASID, so they don't affect group's PASID usage. - */ - if ((device->dev->iommu->max_pasids > 0) && - (pasid >= device->dev->iommu->max_pasids)) { - ret = -EINVAL; - goto out_unlock; - } - } + + ret = __iommu_domain_test_device(domain, dev, pasid, NULL); + if (ret) + goto out_unlock; entry = iommu_make_pasid_array_entry(domain, handle); @@ -3573,12 +3620,7 @@ int iommu_replace_device_pasid(struct iommu_domain *domain, if (!group) return -ENODEV; - - if (!domain->ops->set_dev_pasid) - return -EOPNOTSUPP; - - if (!domain_iommu_ops_compatible(dev_iommu_ops(dev), domain) || - pasid == IOMMU_NO_PASID || !handle) + if (pasid == IOMMU_NO_PASID || !handle) return -EINVAL; mutex_lock(&group->mutex); @@ -3615,6 +3657,11 @@ int iommu_replace_device_pasid(struct iommu_domain *domain, ret = 0; if (curr_domain != domain) { + ret = __iommu_domain_test_device(domain, dev, pasid, + curr_domain); + if (ret) + goto out_unlock; + ret = __iommu_set_group_pasid(domain, group, pasid, curr_domain); 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Sun, 12 Oct 2025 17:05:34 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 03/20] iommu/arm-smmu-v3: Implement arm_smmu_domain_test_dev Date: Sun, 12 Oct 2025 17:05:00 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: asahi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6E:EE_|SJ2PR12MB8881:EE_ X-MS-Office365-Filtering-Correlation-Id: 8ac1a793-973b-40e7-9948-08de09ec4549 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|7416014|376014|82310400026; X-Microsoft-Antispam-Message-Info: xhsdQx3rW29xTC6K6kz9QpFrrlAk20RfkCnfvlQo5okLGvQyPS3yiUU+6m1Jgo8yaUwEWmOjn0Ddoh+9fKpPYCclHk44OC32n9oRMERTm54xqxi9mHOwGeYT4x/5u81B15IbmdjNKMR9gxa8f7z9MdButm4Z6QJR2iAWiVH6V7QZlJwGpoRQWJheR/x5rIVG484dVCM65NCq4v2YHIMVqHwzeK3tcbNHQK6dYFY1RtGPhFfkNzwbYiQjAo1Kqq1HmR2KXvw+EEEHhdpyfso3oJxONhkOlZCoT0qfMguTEDV5V3RfzikCVDnjni4j1mNsfBCcBFwBYwCopgu7auFRk55OdfLJXfW7xOH8aW3O0jzrXtNpkaVw6wMK4Due6DN3lUtxihFlIQvc4Glf8+D+Z3TAcIZ+MaJiWC/KMwZ/ESgMkgZktBqgM3ElYEGYfxUWuUeX7TURA/X8cXxmJkGcTDhWlRPwHAAK/2KsugD5BPJDvkJFOdaEX6vAVw9XtjJCzY4V7JI2uaor18ey6HJ30LVipK/Moyc/KSL6StVaOd/97I6qZAkjSEfcytF6xgrK76aXN6M+vZUESjfe+U27r6+AMj3q62CDmddVpzvi/C6/YqnSyspm+i/a9fyCGC44c4ZSSRIP6iJcl8bCwMIiwYT4vXk7O6Z5orKJLtkF9cGMZr6RSWw8yGwW70mhbJGyxzm8ktCMOjLdl7xQV5iN7cyRY4eZlUZ7lopy7F2WELj/WoIebVlLBwS/C47cv/QZCgGq+QU1QOC6HQ7+cxFqiNi4QqZPbgUYtBC63VRrWNfx4wQ9UT2F4ydLLxSYqlnyPGIeRj4oSH8mzFNIbt305QjTI4GlNOz8FGQYKlTqp2DcjLU1P1enHCLaZPoik7hGC6NXK7hd+jF0c82hyvwmS1hyr4dftIPBo6U1DU9C2/W3fuZ1yPKQmzG2v1P93yy8Xgczy+dQtVXzfFMScgHEr1WSXmoyeH+ySdEgF5hJr9VmAByS0CYln3R59vy2SkIQ3wy5PVQXiSEhHcFUa00ilr9A1+MtSWR+ybdiiQe0PQJttrCSWIle4MFbqN7FDhR4VJlbc8j27nK2mQHNTpcC6QYu3EWrEWe+UYIwm77Y3VBjPVVFUbiAcn7NqH2NivREWKj848d5qFocGBaY1+Xmh8TGREVnWWl8TW5RqpEkjHdRvf3oSjfaIlAFWp0YnFByoa/F0Q9NU6XEnPBe5UZdy+Axo30Fkjivw9rKT5uT1ah43CsKkR92GFxksgfuCTE4iR1mdVxe+1vRBvhDwLipasdkGx68aBmPH4PrJYn5nBuFvr0yw8t5Qao1O+WKDea45elBMFNQoVNJ43kh9x+j5ybq0PUIGHpY3RkNgshNtTPON3uykwJK6nq6dRmLanbKEC/kI2HddLgE96ogUm+62gjcznFpffCAQC5h3Ol026o/0cGp9YBCQIPT+lLJkg7GfwGGDi764TEj5EEP1tNOgHdUc3ZFA8ABCw3PRINht/eGoDLgIxOdVqhHEVAmAywjj5PFkt8BWd0RKKJULwIYuF6ThEPiLVPudpAiwixk7Tc= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(7416014)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:05:51.1083 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ac1a793-973b-40e7-9948-08de09ec4549 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8881 Status: O Move sanity and compatibility tests from the attach_dev callbacks to this new test_dev callback function. The IOMMU core makes sure an attach_dev() must be invoked after a successful test_dev callback. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 + .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 6 +- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 4 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 113 +++++++++++------- 4 files changed, 74 insertions(+), 51 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index ae23aacc38402..acb1dbc592cf0 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -963,6 +963,8 @@ void arm_smmu_write_cd_entry(struct arm_smmu_master *master, int ssid, struct arm_smmu_cd *cdptr, const struct arm_smmu_cd *target); +int arm_smmu_domain_test_dev(struct iommu_domain *domain, struct device *dev, + ioasid_t pasid, struct iommu_domain *old_domain); int arm_smmu_set_pasid(struct arm_smmu_master *master, struct arm_smmu_domain *smmu_domain, ioasid_t pasid, struct arm_smmu_cd *cd, struct iommu_domain *old); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 313201a616991..a253f9c8bb290 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -152,11 +152,6 @@ static int arm_smmu_attach_dev_nested(struct iommu_domain *domain, struct arm_smmu_ste ste; int ret; - if (nested_domain->vsmmu->smmu != master->smmu) - return -EINVAL; - if (arm_smmu_ssids_in_use(&master->cd_table)) - return -EBUSY; - mutex_lock(&arm_smmu_asid_lock); /* * The VM has to control the actual ATS state at the PCI device because @@ -187,6 +182,7 @@ static void arm_smmu_domain_nested_free(struct iommu_domain *domain) } static const struct iommu_domain_ops arm_smmu_nested_ops = { + .test_dev = arm_smmu_domain_test_dev, .attach_dev = arm_smmu_attach_dev_nested, .free = arm_smmu_domain_nested_free, }; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 59a480974d80f..610d9e826c07e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -276,9 +276,6 @@ static int arm_smmu_sva_set_dev_pasid(struct iommu_domain *domain, struct arm_smmu_cd target; int ret; - if (!(master->smmu->features & ARM_SMMU_FEAT_SVA)) - return -EOPNOTSUPP; - /* Prevent arm_smmu_mm_release from being called while we are attaching */ if (!mmget_not_zero(domain->mm)) return -EINVAL; @@ -319,6 +316,7 @@ static void arm_smmu_sva_domain_free(struct iommu_domain *domain) } static const struct iommu_domain_ops arm_smmu_sva_domain_ops = { + .test_dev = arm_smmu_domain_test_dev, .set_dev_pasid = arm_smmu_sva_set_dev_pasid, .free = arm_smmu_sva_domain_free }; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index a33fbd12a0dd9..3448e55bbcdbb 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2765,9 +2765,6 @@ static int arm_smmu_enable_iopf(struct arm_smmu_master *master, iommu_group_mutex_assert(master->dev); - if (!IS_ENABLED(CONFIG_ARM_SMMU_V3_SVA)) - return -EOPNOTSUPP; - /* * Drivers for devices supporting PRI or stall require iopf others have * device-specific fault handlers and don't need IOPF, so this is not a @@ -2776,10 +2773,6 @@ static int arm_smmu_enable_iopf(struct arm_smmu_master *master, if (!master->stall_enabled) return 0; - /* We're not keeping track of SIDs in fault events */ - if (master->num_streams != 1) - return -EOPNOTSUPP; - if (master->iopf_refcount) { master->iopf_refcount++; master_domain->using_iopf = true; @@ -2937,14 +2930,6 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, * one of them. */ spin_lock_irqsave(&smmu_domain->devices_lock, flags); - if (smmu_domain->enforce_cache_coherency && - !arm_smmu_master_canwbs(master)) { - spin_unlock_irqrestore(&smmu_domain->devices_lock, - flags); - ret = -EINVAL; - goto err_iopf; - } - if (state->ats_enabled) atomic_inc(&smmu_domain->nr_ats_masters); list_add(&master_domain->devices_elm, &smmu_domain->devices); @@ -2962,8 +2947,6 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, } return 0; -err_iopf: - arm_smmu_disable_iopf(master, master_domain); err_free_master_domain: kfree(master_domain); err_free_vmaster: @@ -3002,13 +2985,79 @@ void arm_smmu_attach_commit(struct arm_smmu_attach_state *state) master->ats_enabled = state->ats_enabled; } +int arm_smmu_domain_test_dev(struct iommu_domain *domain, struct device *dev, + ioasid_t pasid, struct iommu_domain *old_domain) +{ + struct arm_smmu_domain *device_domain = to_smmu_domain_devices(domain); + struct arm_smmu_master *master = dev_iommu_priv_get(dev); + + if (!dev_iommu_fwspec_get(dev)) + return -ENOENT; + + switch (domain->type) { + case IOMMU_DOMAIN_NESTED: { + struct arm_smmu_nested_domain *nested_domain = + to_smmu_nested_domain(domain); + + if (WARN_ON(pasid != IOMMU_NO_PASID)) + return -EOPNOTSUPP; + if (nested_domain->vsmmu->smmu != master->smmu) + return -EINVAL; + if (arm_smmu_ssids_in_use(&master->cd_table)) + return -EBUSY; + break; + } + case IOMMU_DOMAIN_SVA: + if (!(master->smmu->features & ARM_SMMU_FEAT_SVA)) + return -EOPNOTSUPP; + break; + default: { + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + + if (smmu_domain->smmu != master->smmu) + return -EINVAL; + if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2 && + arm_smmu_ssids_in_use(&master->cd_table)) + return -EBUSY; + if (pasid != IOMMU_NO_PASID) { + struct iommu_domain *sid_domain = + iommu_get_domain_for_dev(master->dev); + + if (smmu_domain->stage != ARM_SMMU_DOMAIN_S1) + return -EINVAL; + if (!master->cd_table.in_ste && + sid_domain->type != IOMMU_DOMAIN_IDENTITY && + sid_domain->type != IOMMU_DOMAIN_BLOCKED) + return -EINVAL; + } + break; + } + } + + if (domain->iopf_handler) { + if (!IS_ENABLED(CONFIG_ARM_SMMU_V3_SVA)) + return -EOPNOTSUPP; + /* We're not keeping track of SIDs in fault events */ + if (master->stall_enabled && master->num_streams != 1) + return -EOPNOTSUPP; + } + + if (device_domain) { + scoped_guard(spinlock_irqsave, &device_domain->devices_lock) { + if (device_domain->enforce_cache_coherency && + !arm_smmu_master_canwbs(master)) + return -EINVAL; + } + } + + return 0; +} + static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev, struct iommu_domain *old_domain) { int ret = 0; struct arm_smmu_ste target; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct arm_smmu_device *smmu; struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_attach_state state = { .old_domain = old_domain, @@ -3017,21 +3066,13 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev, struct arm_smmu_master *master; struct arm_smmu_cd *cdptr; - if (!fwspec) - return -ENOENT; - state.master = master = dev_iommu_priv_get(dev); - smmu = master->smmu; - - if (smmu_domain->smmu != smmu) - return -EINVAL; if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { cdptr = arm_smmu_alloc_cd_ptr(master, IOMMU_NO_PASID); if (!cdptr) return -ENOMEM; - } else if (arm_smmu_ssids_in_use(&master->cd_table)) - return -EBUSY; + } /* * Prevent arm_smmu_share_asid() from trying to change the ASID @@ -3078,15 +3119,8 @@ static int arm_smmu_s1_set_dev_pasid(struct iommu_domain *domain, { struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_master *master = dev_iommu_priv_get(dev); - struct arm_smmu_device *smmu = master->smmu; struct arm_smmu_cd target_cd; - if (smmu_domain->smmu != smmu) - return -EINVAL; - - if (smmu_domain->stage != ARM_SMMU_DOMAIN_S1) - return -EINVAL; - /* * We can read cd.asid outside the lock because arm_smmu_set_pasid() * will fix it @@ -3136,14 +3170,6 @@ int arm_smmu_set_pasid(struct arm_smmu_master *master, /* The core code validates pasid */ - if (smmu_domain->smmu != master->smmu) - return -EINVAL; - - if (!master->cd_table.in_ste && - sid_domain->type != IOMMU_DOMAIN_IDENTITY && - sid_domain->type != IOMMU_DOMAIN_BLOCKED) - return -EINVAL; - cdptr = arm_smmu_alloc_cd_ptr(master, pasid); if (!cdptr) return -ENOMEM; @@ -3695,6 +3721,7 @@ static const struct iommu_ops arm_smmu_ops = { .user_pasid_table = 1, .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { + .test_dev = arm_smmu_domain_test_dev, .attach_dev = arm_smmu_attach_dev, .enforce_cache_coherency = arm_smmu_enforce_cache_coherency, .set_dev_pasid = arm_smmu_s1_set_dev_pasid, From patchwork Mon Oct 13 00:05:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1899 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011060.outbound.protection.outlook.com [40.107.208.60]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2EAA1D5141; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:05:59.8461 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 72735675-3d61-4672-9007-08de09ec4a73 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7956 Status: O Move sanity and compatibility tests from the attach_dev callbacks to the new test_dev callback functions. The IOMMU core makes sure an attach_dev call must be invoked after a successful test_dev call. Following the test_dev guideline, replace dev_err with dev_dbg. Signed-off-by: Nicolin Chen --- drivers/iommu/intel/iommu.c | 66 +++++++++++++++++++++--------------- drivers/iommu/intel/nested.c | 29 +++++++++++----- drivers/iommu/intel/svm.c | 11 +++--- 3 files changed, 67 insertions(+), 39 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index f0396591cd9bb..10d422bd463a2 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -3537,6 +3537,26 @@ int paging_domain_compatible(struct iommu_domain *domain, struct device *dev) return 0; } +static int intel_iommu_test_device(struct iommu_domain *domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old) +{ + struct device_domain_info *info = dev_iommu_priv_get(dev); + struct intel_iommu *iommu = info->iommu; + + if (pasid != IOMMU_NO_PASID) { + if (WARN_ON_ONCE(!(domain->type & __IOMMU_DOMAIN_PAGING))) + return -EINVAL; + if (!pasid_supported(iommu) || dev_is_real_dma_subdevice(dev)) + return -EOPNOTSUPP; + if (domain->dirty_ops) + return -EINVAL; + if (context_copied(iommu, info->bus, info->devfn)) + return -EBUSY; + } + return paging_domain_compatible(domain, dev); +} + static int intel_iommu_attach_device(struct iommu_domain *domain, struct device *dev, struct iommu_domain *old) @@ -3545,10 +3565,6 @@ static int intel_iommu_attach_device(struct iommu_domain *domain, device_block_translation(dev); - ret = paging_domain_compatible(domain, dev); - if (ret) - return ret; - ret = iopf_for_domain_set(domain, dev); if (ret) return ret; @@ -4151,22 +4167,6 @@ static int intel_iommu_set_dev_pasid(struct iommu_domain *domain, struct dev_pasid_info *dev_pasid; int ret; - if (WARN_ON_ONCE(!(domain->type & __IOMMU_DOMAIN_PAGING))) - return -EINVAL; - - if (!pasid_supported(iommu) || dev_is_real_dma_subdevice(dev)) - return -EOPNOTSUPP; - - if (domain->dirty_ops) - return -EINVAL; - - if (context_copied(iommu, info->bus, info->devfn)) - return -EBUSY; - - ret = paging_domain_compatible(domain, dev); - if (ret) - return ret; - dev_pasid = domain_add_dev_pasid(domain, dev, pasid); if (IS_ERR(dev_pasid)) return PTR_ERR(dev_pasid); @@ -4178,12 +4178,9 @@ static int intel_iommu_set_dev_pasid(struct iommu_domain *domain, if (intel_domain_is_fs_paging(dmar_domain)) ret = domain_setup_first_level(iommu, dmar_domain, dev, pasid, old); - else if (intel_domain_is_ss_paging(dmar_domain)) + else /* paging_domain_compatible() made sure it's ss_paging */ ret = domain_setup_second_level(iommu, dmar_domain, dev, pasid, old); - else if (WARN_ON(true)) - ret = -EINVAL; - if (ret) goto out_unwind_iopf; @@ -4403,6 +4400,21 @@ static int device_setup_pass_through(struct device *dev) context_setup_pass_through_cb, dev); } +static int identity_domain_test_dev(struct iommu_domain *domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old) +{ + if (pasid != IOMMU_NO_PASID) { + struct device_domain_info *info = dev_iommu_priv_get(dev); + struct intel_iommu *iommu = info->iommu; + + if (!pasid_supported(iommu) || dev_is_real_dma_subdevice(dev)) + return -EOPNOTSUPP; + } + + return 0; +} + static int identity_domain_attach_dev(struct iommu_domain *domain, struct device *dev, struct iommu_domain *old) @@ -4440,9 +4452,6 @@ static int identity_domain_set_dev_pasid(struct iommu_domain *domain, struct intel_iommu *iommu = info->iommu; int ret; - if (!pasid_supported(iommu) || dev_is_real_dma_subdevice(dev)) - return -EOPNOTSUPP; - ret = iopf_for_domain_replace(domain, old, dev); if (ret) return ret; @@ -4460,12 +4469,14 @@ static int identity_domain_set_dev_pasid(struct iommu_domain *domain, static struct iommu_domain identity_domain = { .type = IOMMU_DOMAIN_IDENTITY, .ops = &(const struct iommu_domain_ops) { + .test_dev = identity_domain_test_dev, .attach_dev = identity_domain_attach_dev, .set_dev_pasid = identity_domain_set_dev_pasid, }, }; const struct iommu_domain_ops intel_fs_paging_domain_ops = { + .test_dev = intel_iommu_test_device, .attach_dev = intel_iommu_attach_device, .set_dev_pasid = intel_iommu_set_dev_pasid, .map_pages = intel_iommu_map_pages, @@ -4479,6 +4490,7 @@ const struct iommu_domain_ops intel_fs_paging_domain_ops = { }; const struct iommu_domain_ops intel_ss_paging_domain_ops = { + .test_dev = intel_iommu_test_device, .attach_dev = intel_iommu_attach_device, .set_dev_pasid = intel_iommu_set_dev_pasid, .map_pages = intel_iommu_map_pages, diff --git a/drivers/iommu/intel/nested.c b/drivers/iommu/intel/nested.c index 760d7aa2ade84..708b8e653d5cd 100644 --- a/drivers/iommu/intel/nested.c +++ b/drivers/iommu/intel/nested.c @@ -18,19 +18,17 @@ #include "iommu.h" #include "pasid.h" -static int intel_nested_attach_dev(struct iommu_domain *domain, - struct device *dev, struct iommu_domain *old) +static int intel_nested_test_dev(struct iommu_domain *domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old) { struct device_domain_info *info = dev_iommu_priv_get(dev); struct dmar_domain *dmar_domain = to_dmar_domain(domain); struct intel_iommu *iommu = info->iommu; - unsigned long flags; - int ret = 0; - - device_block_translation(dev); + int ret; if (iommu->agaw < dmar_domain->s2_domain->agaw) { - dev_err_ratelimited(dev, "Adjusted guest address width not compatible\n"); + dev_dbg_ratelimited(dev, "Adjusted guest address width not compatible\n"); return -ENODEV; } @@ -41,10 +39,24 @@ static int intel_nested_attach_dev(struct iommu_domain *domain, */ ret = paging_domain_compatible(&dmar_domain->s2_domain->domain, dev); if (ret) { - dev_err_ratelimited(dev, "s2 domain is not compatible\n"); + dev_dbg_ratelimited(dev, "s2 domain is not compatible\n"); return ret; } + return 0; +} + +static int intel_nested_attach_dev(struct iommu_domain *domain, + struct device *dev, struct iommu_domain *old) +{ + struct device_domain_info *info = dev_iommu_priv_get(dev); + struct dmar_domain *dmar_domain = to_dmar_domain(domain); + struct intel_iommu *iommu = info->iommu; + unsigned long flags; + int ret = 0; + + device_block_translation(dev); + ret = domain_attach_iommu(dmar_domain, iommu); if (ret) { dev_err_ratelimited(dev, "Failed to attach domain to iommu\n"); @@ -192,6 +204,7 @@ static int intel_nested_set_dev_pasid(struct iommu_domain *domain, } static const struct iommu_domain_ops intel_nested_domain_ops = { + .test_dev = intel_nested_test_dev, .attach_dev = intel_nested_attach_dev, .set_dev_pasid = intel_nested_set_dev_pasid, .free = intel_nested_domain_free, diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c index e147f71f91b72..5901caa4ceebc 100644 --- a/drivers/iommu/intel/svm.c +++ b/drivers/iommu/intel/svm.c @@ -145,6 +145,12 @@ static int intel_iommu_sva_supported(struct device *dev) return 0; } +static int intel_svm_test_dev(struct iommu_domain *domain, struct device *dev, + ioasid_t pasid, struct iommu_domain *old) +{ + return intel_iommu_sva_supported(dev); +} + static int intel_svm_set_dev_pasid(struct iommu_domain *domain, struct device *dev, ioasid_t pasid, struct iommu_domain *old) @@ -156,10 +162,6 @@ static int intel_svm_set_dev_pasid(struct iommu_domain *domain, unsigned long sflags; int ret = 0; - ret = intel_iommu_sva_supported(dev); - if (ret) - return ret; - dev_pasid = domain_add_dev_pasid(domain, dev, pasid); if (IS_ERR(dev_pasid)) return PTR_ERR(dev_pasid); @@ -195,6 +197,7 @@ static void intel_svm_domain_free(struct iommu_domain *domain) } static const struct iommu_domain_ops intel_svm_domain_ops = { + .test_dev = intel_svm_test_dev, .set_dev_pasid = intel_svm_set_dev_pasid, .free = intel_svm_domain_free }; From patchwork Mon Oct 13 00:05:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1897 Received: from SA9PR02CU001.outbound.protection.outlook.com (mail-southcentralusazon11013037.outbound.protection.outlook.com [40.93.196.37]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F10E82BB1D; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:06:02.9886 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d1bcd165-1730-4bbc-92dc-08de09ec4c53 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6356 Status: O Move sanity and compatibility tests from the attach_dev callbacks to the new test_dev callback functions. The IOMMU core makes sure an attach_dev call must be invoked after a successful test_dev call. Correct the errno upon malloc failure. Also, drop the function prototype of iommu_sva_set_dev_pasid() from the header and make it static, as only pasid.c uses it. Signed-off-by: Nicolin Chen --- drivers/iommu/amd/amd_iommu.h | 3 --- drivers/iommu/amd/iommu.c | 27 +++++++++++++++++++-------- drivers/iommu/amd/pasid.c | 29 +++++++++++++++++++---------- 3 files changed, 38 insertions(+), 21 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 9b4b589a54b57..f99fa4da34996 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -52,9 +52,6 @@ struct protection_domain *protection_domain_alloc(void); struct iommu_domain *amd_iommu_domain_alloc_sva(struct device *dev, struct mm_struct *mm); void amd_iommu_domain_free(struct iommu_domain *dom); -int iommu_sva_set_dev_pasid(struct iommu_domain *domain, - struct device *dev, ioasid_t pasid, - struct iommu_domain *old); void amd_iommu_remove_dev_pasid(struct device *dev, ioasid_t pasid, struct iommu_domain *domain); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index e16ad510c8c8a..dc0406427dcf8 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -70,6 +70,8 @@ int amd_iommu_max_glx_val = -1; */ DEFINE_IDA(pdom_ids); +static int amd_iommu_test_device(struct iommu_domain *dom, struct device *dev, + ioasid_t pasid, struct iommu_domain *old); static int amd_iommu_attach_device(struct iommu_domain *dom, struct device *dev, struct iommu_domain *old); @@ -2670,6 +2672,7 @@ static struct iommu_domain blocked_domain = { static struct protection_domain identity_domain; static const struct iommu_domain_ops identity_domain_ops = { + .test_dev = amd_iommu_test_device, .attach_dev = amd_iommu_attach_device, }; @@ -2686,12 +2689,26 @@ void amd_iommu_init_identity_domain(void) protection_domain_init(&identity_domain); } +static int amd_iommu_test_device(struct iommu_domain *dom, struct device *dev, + ioasid_t pasid, struct iommu_domain *old) +{ + struct amd_iommu *iommu = get_amd_iommu_from_dev(dev); + + /* + * Restrict to devices with compatible IOMMU hardware support + * when enforcement of dirty tracking is enabled. + */ + if (dom->dirty_ops && !amd_iommu_hd_support(iommu)) + return -EINVAL; + + return 0; +} + static int amd_iommu_attach_device(struct iommu_domain *dom, struct device *dev, struct iommu_domain *old) { struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev); struct protection_domain *domain = to_pdomain(dom); - struct amd_iommu *iommu = get_amd_iommu_from_dev(dev); int ret; /* @@ -2703,13 +2720,6 @@ static int amd_iommu_attach_device(struct iommu_domain *dom, struct device *dev, dev_data->defer_attach = false; - /* - * Restrict to devices with compatible IOMMU hardware support - * when enforcement of dirty tracking is enabled. - */ - if (dom->dirty_ops && !amd_iommu_hd_support(iommu)) - return -EINVAL; - if (dev_data->domain) detach_device(dev); @@ -3047,6 +3057,7 @@ const struct iommu_ops amd_iommu_ops = { .def_domain_type = amd_iommu_def_domain_type, .page_response = amd_iommu_page_response, .default_domain_ops = &(const struct iommu_domain_ops) { + .test_dev = amd_iommu_test_device, .attach_dev = amd_iommu_attach_device, .map_pages = amd_iommu_map_pages, .unmap_pages = amd_iommu_unmap_pages, diff --git a/drivers/iommu/amd/pasid.c b/drivers/iommu/amd/pasid.c index 77c8e9a91cbca..474494a66dd40 100644 --- a/drivers/iommu/amd/pasid.c +++ b/drivers/iommu/amd/pasid.c @@ -99,31 +99,39 @@ static const struct mmu_notifier_ops sva_mn = { .release = sva_mn_release, }; -int iommu_sva_set_dev_pasid(struct iommu_domain *domain, - struct device *dev, ioasid_t pasid, - struct iommu_domain *old) +static int iommu_sva_test_dev(struct iommu_domain *domain, struct device *dev, + ioasid_t pasid, struct iommu_domain *old) { - struct pdom_dev_data *pdom_dev_data; - struct protection_domain *sva_pdom = to_pdomain(domain); struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev); - unsigned long flags; - int ret = -EINVAL; if (old) return -EOPNOTSUPP; /* PASID zero is used for requests from the I/O device without PASID */ if (!is_pasid_valid(dev_data, pasid)) - return ret; + return -EINVAL; /* Make sure PASID is enabled */ if (!is_pasid_enabled(dev_data)) - return ret; + return -EINVAL; + + return 0; +} + +static int iommu_sva_set_dev_pasid(struct iommu_domain *domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old) +{ + struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev); + struct protection_domain *sva_pdom = to_pdomain(domain); + struct pdom_dev_data *pdom_dev_data; + unsigned long flags; + int ret; /* Add PASID to protection domain pasid list */ pdom_dev_data = kzalloc(sizeof(*pdom_dev_data), GFP_KERNEL); if (pdom_dev_data == NULL) - return ret; + return -ENOMEM; pdom_dev_data->pasid = pasid; pdom_dev_data->dev_data = dev_data; @@ -175,6 +183,7 @@ static void iommu_sva_domain_free(struct iommu_domain *domain) } static const struct iommu_domain_ops amd_sva_domain_ops = { + .test_dev = iommu_sva_test_dev, .set_dev_pasid = iommu_sva_set_dev_pasid, .free = iommu_sva_domain_free }; From patchwork Mon Oct 13 00:05:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1900 Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010051.outbound.protection.outlook.com [40.93.198.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5256C1DDC1D; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:06:00.0566 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f53487a-5098-4eee-5aa2-08de09ec4a9f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F69.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV9PR12MB9760 Status: O Move sanity and compatibility tests from the attach_dev callback to the new test_dev callback function. The IOMMU core makes sure an attach_dev call must be invoked after a successful test_dev call. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 116 ++++++++++++++++---------- 1 file changed, 71 insertions(+), 45 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 5e690cf85ec96..5752eecc1d434 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -672,6 +672,37 @@ static int arm_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain, return __arm_smmu_alloc_bitmap(smmu->context_map, start, smmu->num_context_banks); } +static enum arm_smmu_context_fmt +arm_smmu_get_context_fmt(struct arm_smmu_domain *smmu_domain) +{ + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; + enum arm_smmu_context_fmt fmt = cfg->fmt; + + /* + * Choosing a suitable context format is even more fiddly. Until we + * grow some way for the caller to express a preference, and/or move + * the decision into the io-pgtable code where it arguably belongs, + * just aim for the closest thing to the rest of the system, and hope + * that the hardware isn't esoteric enough that we can't assume AArch64 + * support to be a superset of AArch32 support... + */ + if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_L) + fmt = ARM_SMMU_CTX_FMT_AARCH32_L; + if (IS_ENABLED(CONFIG_IOMMU_IO_PGTABLE_ARMV7S) && + !IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_ARM_LPAE) && + (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S) && + (smmu_domain->stage == ARM_SMMU_DOMAIN_S1)) + fmt = ARM_SMMU_CTX_FMT_AARCH32_S; + if ((IS_ENABLED(CONFIG_64BIT) || cfg->fmt == ARM_SMMU_CTX_FMT_NONE) && + (smmu->features & (ARM_SMMU_FEAT_FMT_AARCH64_64K | + ARM_SMMU_FEAT_FMT_AARCH64_16K | + ARM_SMMU_FEAT_FMT_AARCH64_4K))) + fmt = ARM_SMMU_CTX_FMT_AARCH64; + + return fmt; +} + static int arm_smmu_init_domain_context(struct arm_smmu_domain *smmu_domain, struct arm_smmu_device *smmu, struct device *dev) @@ -712,31 +743,8 @@ static int arm_smmu_init_domain_context(struct arm_smmu_domain *smmu_domain, if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) smmu_domain->stage = ARM_SMMU_DOMAIN_S1; - /* - * Choosing a suitable context format is even more fiddly. Until we - * grow some way for the caller to express a preference, and/or move - * the decision into the io-pgtable code where it arguably belongs, - * just aim for the closest thing to the rest of the system, and hope - * that the hardware isn't esoteric enough that we can't assume AArch64 - * support to be a superset of AArch32 support... - */ - if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_L) - cfg->fmt = ARM_SMMU_CTX_FMT_AARCH32_L; - if (IS_ENABLED(CONFIG_IOMMU_IO_PGTABLE_ARMV7S) && - !IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_ARM_LPAE) && - (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S) && - (smmu_domain->stage == ARM_SMMU_DOMAIN_S1)) - cfg->fmt = ARM_SMMU_CTX_FMT_AARCH32_S; - if ((IS_ENABLED(CONFIG_64BIT) || cfg->fmt == ARM_SMMU_CTX_FMT_NONE) && - (smmu->features & (ARM_SMMU_FEAT_FMT_AARCH64_64K | - ARM_SMMU_FEAT_FMT_AARCH64_16K | - ARM_SMMU_FEAT_FMT_AARCH64_4K))) - cfg->fmt = ARM_SMMU_CTX_FMT_AARCH64; - - if (cfg->fmt == ARM_SMMU_CTX_FMT_NONE) { - ret = -EINVAL; - goto out_unlock; - } + cfg->fmt = arm_smmu_get_context_fmt(smmu_domain); + WARN_ON(cfg->fmt == ARM_SMMU_CTX_FMT_NONE); switch (smmu_domain->stage) { case ARM_SMMU_DOMAIN_S1: @@ -1165,14 +1173,11 @@ static void arm_smmu_master_install_s2crs(struct arm_smmu_master_cfg *cfg, } } -static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev, - struct iommu_domain *old) +static int arm_smmu_test_dev(struct iommu_domain *domain, struct device *dev, + ioasid_t pasid, struct iommu_domain *old) { - struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct arm_smmu_master_cfg *cfg; - struct arm_smmu_device *smmu; - int ret; + struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev); + struct arm_smmu_domain *smmu_domain; /* * FIXME: The arch/arm DMA API code tries to attach devices to its own @@ -1181,11 +1186,40 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev, * domains, just say no (but more politely than by dereferencing NULL). * This should be at least a WARN_ON once that's sorted. */ - cfg = dev_iommu_priv_get(dev); if (!cfg) return -ENODEV; - smmu = cfg->smmu; + if (domain == arm_smmu_ops.identity_domain || + domain == arm_smmu_ops.blocked_domain) + return 0; + + smmu_domain = to_smmu_domain(domain); + scoped_guard(mutex, &smmu_domain->init_mutex) { + /* arm_smmu_init_domain_context() will initialize it */ + if (!smmu_domain->smmu) + return 0; + /* + * Sanity check the domain. We don't support domains across + * different SMMUs. + */ + if (smmu_domain->smmu != cfg->smmu) + return -EINVAL; + if (arm_smmu_get_context_fmt(smmu_domain) == + ARM_SMMU_CTX_FMT_NONE) + return -EINVAL; + } + + return 0; +} + +static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev, + struct iommu_domain *old) +{ + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev); + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct arm_smmu_device *smmu = cfg->smmu; + int ret; ret = arm_smmu_rpm_get(smmu); if (ret < 0) @@ -1196,15 +1230,6 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev, if (ret < 0) goto rpm_put; - /* - * Sanity check the domain. We don't support domains across - * different SMMUs. - */ - if (smmu_domain->smmu != smmu) { - ret = -EINVAL; - goto rpm_put; - } - /* Looks ok, so add the device to the domain */ arm_smmu_master_install_s2crs(cfg, S2CR_TYPE_TRANS, smmu_domain->cfg.cbndx, fwspec); @@ -1221,8 +1246,6 @@ static int arm_smmu_attach_dev_type(struct device *dev, struct arm_smmu_device *smmu; int ret; - if (!cfg) - return -ENODEV; smmu = cfg->smmu; ret = arm_smmu_rpm_get(smmu); @@ -1242,6 +1265,7 @@ static int arm_smmu_attach_dev_identity(struct iommu_domain *domain, } static const struct iommu_domain_ops arm_smmu_identity_ops = { + .test_dev = arm_smmu_test_dev, .attach_dev = arm_smmu_attach_dev_identity, }; @@ -1258,6 +1282,7 @@ static int arm_smmu_attach_dev_blocked(struct iommu_domain *domain, } static const struct iommu_domain_ops arm_smmu_blocked_ops = { + .test_dev = arm_smmu_test_dev, .attach_dev = arm_smmu_attach_dev_blocked, }; @@ -1647,6 +1672,7 @@ static const struct iommu_ops arm_smmu_ops = { .def_domain_type = arm_smmu_def_domain_type, .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { + .test_dev = arm_smmu_test_dev, .attach_dev = arm_smmu_attach_dev, .map_pages = arm_smmu_map_pages, .unmap_pages = arm_smmu_unmap_pages, From patchwork Mon Oct 13 00:05:04 2025 Content-Type: text/plain; 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Sun, 12 Oct 2025 17:05:44 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 07/20] iommu/qcom_iommu: Implement test_dev callbacks to domain ops Date: Sun, 12 Oct 2025 17:05:04 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: asahi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3C:EE_|MW6PR12MB7072:EE_ X-MS-Office365-Filtering-Correlation-Id: 00dd7a17-2c7f-414b-b769-08de09ec4f01 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|7416014|82310400026; X-Microsoft-Antispam-Message-Info: GsfHxoZMhQ99zP74mCx3qItBlYpNkXykhvyv6ubSLxzcj2pcHj5GzmomUVhcPUyrvHqtfnLHfWCS1jDrXA39wz7UQ/eb+IKCMQ52MOlu0E50LbxGnQNOjbbWGefRMslnvyXpaPdsBdRlhwsKVrwJEI4+ILKK8VB7TMv9RL8fw5vuZFvKIIqMDqP5Jj6+60znUaLE/XSHlD+1L7Md/Cyme4WgzOh1LCfigAkqWzn/ksFPyDwkS/hH15QjA+i6EZvToxo0CYtsBfQxckMg0D6n81FZ9T+VUYSJl015f9MRA+BFE9tMBJn423xNegT4E9Vod1U6ZawjoCfxeFRxgNa8K81LqHAE5H02OBwEr5nPCcDNxkM1YaK2+OFN9Pxx+e6arcEKsDZZNOdqn9QhcKvu5EHBDMHQKQdQefUbxxJlk/yxoRcGc4MPfODzn/C7dUNriAsWJfdr/ZUQvFfcDvNJSyvFVlOjK+9fp7knsrR8nIztX7BRYgQB0EXFG/Jv0PMwwb/yb81/wQCdOxcjMUM21Das0qXUDtnUpHcixtQ9umSj+fYR8hp7LJlCaFut0Gvz6kzhhbl1g0HNTrtG6NM6DKfc3Iv7fWW+IRAJbPnMWjH4rh2SUejAxJv78T2quWMAfRtkscYM/VYPGYWpt3t/L8XCXa/aQE7a83qFMaYaZv0QBpN3ovPXG4RlDA/j/m4LcTUtfLi0XuO5cdavI8tZYqeDa8do8kZTObGSyozZZS0GJQkK0Sh+DfO8sEiLAGu3kPq1KmiO3F3FsVgccMFb/wZlakoEFQef94NjPKITSbo0yS7IpHJIcJs7tnUbHylpE9ZVcdYAbFmMtZM50usB8oUtkTyLwRre39GTqWbGgfw7qg7usPNQr4oya4k/2Tskva+6gxAGvXbsnbMB97U+iqXtQYtxPW8HXvVVlI0VpPP2oBrcvgMx6tXwMqV+0XZbVBZxOSZQF/nMBUzKRzNrtPb9TZPs9D/cgWopxC9GTLicQWNvPgV4P0itr/E3sROWB3oy47Y+HkH6ZmSdr3m0vMz5rC1hxabHyQdexP3tcDRs23Vrrwxndoozbm5506CUHXv8rZruqEoToQ9UPVMIZrurWn8YY5vTcr0sMa1XtDsAXNyE/GnAPjejC91kCIH3Av9M0gLimptndeFENVFmVm1HLteAl4U9LQ9HQQ4viSZesVYd5YbGoByWNQ1D1DcXA95bUzW19o5WHwefbWNQhIgKFCw4noGE7P6518NJBzF6CzVjXM3MMDkywpR5sZ+fBEsk5Mrnn3L47aFPuuF7wWkd5sy7E6FlEVZkL1pydXRyfg062RwlWyxrmqNArGePs+0KQFLLF9oXBP5rt0+lfcFFCsq4zRx0sVIxO3S+jx9F6IjMc8AuRCrgoNHDvgEm5Ff17dZedYdY36xt9MK7HoEJIJ0X7DNbqpYdbrwS+PDZecRYR2rg7Spaz0GS6sEkmxq5CP5kKcgiYaRDK0NcMT2WJE6DU8Zg8u1oTXn9/PazGoygdtETVZ9YjTnCooWmiT1F9f8RGC5vCEZRqkb1KBwBNIQWvWMn6e/GMbNWj14= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:06:07.4880 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 00dd7a17-2c7f-414b-b769-08de09ec4f01 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB7072 Status: O Move sanity and compatibility tests from the attach_dev callbacks to the new test_dev callback functions. The IOMMU core makes sure an attach_dev call must be invoked after a successful test_dev call. Following the test_dev guideline, replace dev_err with dev_dbg. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu/qcom_iommu.c | 46 ++++++++++++++++++------- 1 file changed, 34 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c index 9222a4a48bb33..53b1c279563ba 100644 --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c @@ -359,18 +359,36 @@ static void qcom_iommu_domain_free(struct iommu_domain *domain) kfree(qcom_domain); } -static int qcom_iommu_attach_dev(struct iommu_domain *domain, - struct device *dev, struct iommu_domain *old) +static int qcom_iommu_domain_test_dev(struct iommu_domain *domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old) { struct qcom_iommu_dev *qcom_iommu = dev_iommu_priv_get(dev); struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); - int ret; if (!qcom_iommu) { - dev_err(dev, "cannot attach to IOMMU, is it on the same bus?\n"); + dev_dbg(dev, "cannot attach to IOMMU, is it on the same bus?\n"); return -ENXIO; } + scoped_guard(mutex, &qcom_domain->init_mutex) { + /* + * Sanity check the domain. We don't support domains across + * different IOMMUs. + */ + if (qcom_domain->iommu && qcom_domain->iommu != qcom_iommu) + return -EINVAL; + } + + return 0; +} + +static int qcom_iommu_attach_dev(struct iommu_domain *domain, + struct device *dev, struct iommu_domain *old) +{ + struct qcom_iommu_dev *qcom_iommu = dev_iommu_priv_get(dev); + int ret; + /* Ensure that the domain is finalized */ pm_runtime_get_sync(qcom_iommu->dev); ret = qcom_iommu_init_domain(domain, qcom_iommu, dev); @@ -378,13 +396,17 @@ static int qcom_iommu_attach_dev(struct iommu_domain *domain, if (ret < 0) return ret; - /* - * Sanity check the domain. We don't support domains across - * different IOMMUs. - */ - if (qcom_domain->iommu != qcom_iommu) - return -EINVAL; + return 0; +} +static int qcom_iommu_identity_test(struct iommu_domain *identity_domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old) +{ + if (old == identity_domain || !old) + return 0; + if (WARN_ON(!to_qcom_iommu_domain(old)->iommu)) + return -EINVAL; return 0; } @@ -401,8 +423,6 @@ static int qcom_iommu_identity_attach(struct iommu_domain *identity_domain, return 0; qcom_domain = to_qcom_iommu_domain(old); - if (WARN_ON(!qcom_domain->iommu)) - return -EINVAL; pm_runtime_get_sync(qcom_iommu->dev); for (i = 0; i < fwspec->num_ids; i++) { @@ -418,6 +438,7 @@ static int qcom_iommu_identity_attach(struct iommu_domain *identity_domain, } static struct iommu_domain_ops qcom_iommu_identity_ops = { + .test_dev = qcom_iommu_identity_test, .attach_dev = qcom_iommu_identity_attach, }; @@ -599,6 +620,7 @@ static const struct iommu_ops qcom_iommu_ops = { .device_group = generic_device_group, .of_xlate = qcom_iommu_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { + .test_dev = qcom_iommu_domain_test_dev, .attach_dev = qcom_iommu_attach_dev, .map_pages = qcom_iommu_map, .unmap_pages = qcom_iommu_unmap, From patchwork Mon Oct 13 00:05:05 2025 Content-Type: text/plain; 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Sun, 12 Oct 2025 17:05:47 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 08/20] iommu/riscv: Implement riscv_iommu_test_paging_domain Date: Sun, 12 Oct 2025 17:05:05 -0700 Message-ID: <77e60e630435ed5fcd755a09126c0bc2e85bf1ff.1760312725.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: asahi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3E:EE_|SA1PR12MB9003:EE_ X-MS-Office365-Filtering-Correlation-Id: 7becf227-8728-4d92-6f71-08de09ec50f7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|7416014|82310400026; X-Microsoft-Antispam-Message-Info: Qy2XFjOA+tR7kH9q/IARx/fpOo5BzZzfC8gz7gKRUi7to5qhWxKy8TC4HJLjZ10hdLpj//GUw839wvaaSTtKCDk9xDjxsfPp/ZMPsl0hUbqq6SY993QN9hLAns70C028lh9s5msfHMzRyBWbSLWtJcbTp3n/28kGuZGcOYTLZAP+ZW5WfCSS2KxlhyB/izxLLLrjB0hlxqHZMG1Bas9+FV7jUDaM8GOeysPkSpEADw+bVLiqWX4CppyEYuoJiXnZjM2kbugV98+HulyS2Vk4uRLnPKikWvWUUAUsuwAvZ9kcgDTg79YfVVhGgUPpwq1SlxWIC2CcLteLY0IGf0z6hgwLU/yPyN7nqFN1r03x7S5t0qjnh7yDnipJCr1ZCGw2EPuvRjI9apUd8L+lq7Mt1qPEk+5e097ou2tOzVP56mc6EIryboW3j0JgAZpGuQvoA//NOFq3lCI/xlKPJy+9et4FFWoWJKnIjhzFety5ynp40rnG6Wu0KUiSWAzuUCtCPr7ahUfCfm7pT8Uaw4PzX+dLKW5KfkFzLIBly0MFNNsWMjtsaQRNIoiM3ZbkVidxYnU2ArEXB4CULD1psN6Oj4kekBn9l0ydapILg0zXQobSdE0+cE+zkS0iuqJ7NSquFasdAVwRJKKSTuFrXw0PAisuQt3AQ/cjL4TZT7Uf7YHbWz/jd3WUtfaRPfcAaFpN+PdEsWrz/M5rT0E+lJl+EMG/VoGLTQBi6gIYpbIOgPZvnhZL7rm7+6qglHZC3FpD4Ha/aKyF8RUna/aS+fZULeSAQDZ0anyikE1V6Sbb4N5ABdizBUehbWmeIdoOTdUz7YzSgIMmA3OyMYS+nvYemcP+IW38bc1dLVYiJlj+roISRSgaFVkqa62EWgnXpcpIXPtDfdCtqYdiAHoCXUuSVwZV7q2i97ueX1cV9VXAVBXYZ2huPfa7sXDSbvoB+AjO6P4If/qK7ZC0WUF4xxomBwAJ1ihzDfrHrkw/DlQ2GVotUm3EpDZZT1blCkOd5V7IM225mThz7VdvkbVbbbmstamz3GxN0fo5L5j1CS4tlzwJZFu9hA9aral6aTtJ7jmwHrc3nfzIQHBNcAcBzFhIhlg5MZ8aqNuH70tHozhjYmF/YXCzgqW+iydzUQfuMC/lP9Zs+wblNCItIVc5OponzYe0B73wxVtIl/l7VyWAPxst5pVXOFjblK3Io7CQb9bPkhScJ6ZUvqAfcXqOrXw2zKBPi4rQv2pOfQx3N3PlcAKwDooKZkZN+o7levvMqTlXxEJQrfj13J10HPWuC6ZbBErqXzRDW0oabcRdo9fJHnbhyZvNuQ4t9YVt5TYNMOc1VDIEs0JpTUFgvBioljibg4jX/4skQSwEGxF6q5nA7w8iMF+/casIjbo+lTOm1JX0Qhppi9MfdTDgG5yyNRWvFEeFTIw4ugx9ca8DoEPFHtyH70Bb+zwu63Dl3K7kuZ3AqUkQbEVnKd3/t99/3JIXFxDwzL+oml8umwXZ6v+JebeSHrxcx3cc0Oo18VRnBHXjkyJUeakokHmIbDMup2pHLrnGj4q+1SdyFvRHRNlv+gg= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:06:10.7766 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7becf227-8728-4d92-6f71-08de09ec50f7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9003 Status: O Move sanity and compatibility tests from the attach_dev callback to the new test_dev callback function. The IOMMU core makes sure an attach_dev call must be invoked after a successful test_dev call. Signed-off-by: Nicolin Chen --- drivers/iommu/riscv/iommu.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index d9429097a2b51..6613ece2c9f41 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1320,6 +1320,18 @@ static bool riscv_iommu_pt_supported(struct riscv_iommu_device *iommu, int pgd_m return false; } +static int riscv_iommu_test_paging_domain(struct iommu_domain *iommu_domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old) +{ + struct riscv_iommu_domain *domain = iommu_domain_to_riscv(iommu_domain); + struct riscv_iommu_device *iommu = dev_to_iommu(dev); + + if (!riscv_iommu_pt_supported(iommu, domain->pgd_mode)) + return -ENODEV; + return 0; +} + static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain, struct device *dev, struct iommu_domain *old) @@ -1329,9 +1341,6 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain, struct riscv_iommu_info *info = dev_iommu_priv_get(dev); u64 fsc, ta; - if (!riscv_iommu_pt_supported(iommu, domain->pgd_mode)) - return -ENODEV; - fsc = FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, domain->pgd_mode) | FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, virt_to_pfn(domain->pgd_root)); ta = FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, domain->pscid) | @@ -1348,6 +1357,7 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain, } static const struct iommu_domain_ops riscv_iommu_paging_domain_ops = { + .test_dev = riscv_iommu_test_paging_domain, .attach_dev = riscv_iommu_attach_paging_domain, .free = riscv_iommu_free_paging_domain, .map_pages = riscv_iommu_map_pages, From patchwork Mon Oct 13 00:05:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1898 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012026.outbound.protection.outlook.com [40.107.200.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E21952163B2; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:06:05.6446 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3ed24eb3-349b-47dd-6a46-08de09ec4df3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN6PR12MB8567 Status: O Move sanity and compatibility tests from the attach_dev callback to the new test_dev callback function. The IOMMU core makes sure an attach_dev call must be invoked after a successful test_dev call. Signed-off-by: Nicolin Chen --- drivers/iommu/mtk_iommu.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 9747ef1644138..0cfcd0d08ae64 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -704,6 +704,20 @@ static void mtk_iommu_domain_free(struct iommu_domain *domain) kfree(to_mtk_domain(domain)); } +static int mtk_iommu_test_device(struct iommu_domain *domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old) +{ + struct mtk_iommu_data *data = dev_iommu_priv_get(dev); + int region_id; + + region_id = mtk_iommu_get_iova_region_id(dev, data->plat_data); + if (region_id < 0) + return region_id; + + return 0; +} + static int mtk_iommu_attach_device(struct iommu_domain *domain, struct device *dev, struct iommu_domain *old) { @@ -716,8 +730,6 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain, int ret, region_id; region_id = mtk_iommu_get_iova_region_id(dev, data->plat_data); - if (region_id < 0) - return region_id; bankid = mtk_iommu_get_bank_id(dev, data->plat_data); mutex_lock(&dom->mutex); @@ -1019,6 +1031,7 @@ static const struct iommu_ops mtk_iommu_ops = { .get_resv_regions = mtk_iommu_get_resv_regions, .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { + .test_dev = mtk_iommu_test_device, .attach_dev = mtk_iommu_attach_device, .map_pages = mtk_iommu_map, .unmap_pages = mtk_iommu_unmap, From patchwork Mon Oct 13 00:05:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1895 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012058.outbound.protection.outlook.com [52.101.43.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A65C21CC5A; Mon, 13 Oct 2025 00:06:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:06:07.2276 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 699abd7f-dc73-43d3-1561-08de09ec4ee5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6086 Status: O Move sanity and compatibility tests from the attach_dev callbacks to the new test_dev callback functions. The IOMMU core makes sure an attach_dev call must be invoked after a successful test_dev call. Note the apple_dart_finalize_domain() has another caller than attach_dev so it has to duplicate the pgsize sanity too. Signed-off-by: Nicolin Chen --- drivers/iommu/apple-dart.c | 50 +++++++++++++++++++++++++++++--------- 1 file changed, 39 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/apple-dart.c b/drivers/iommu/apple-dart.c index b5848770ef482..fb63dcb7462a7 100644 --- a/drivers/iommu/apple-dart.c +++ b/drivers/iommu/apple-dart.c @@ -593,9 +593,6 @@ static int apple_dart_finalize_domain(struct apple_dart_domain *dart_domain, int ret = 0; int i, j; - if (dart->pgsize > PAGE_SIZE) - return -EINVAL; - mutex_lock(&dart_domain->init_lock); if (dart_domain->finalized) @@ -643,11 +640,6 @@ apple_dart_mod_streams(struct apple_dart_atomic_stream_map *domain_maps, { int i, j; - for (i = 0; i < MAX_DARTS_PER_DEVICE; ++i) { - if (domain_maps[i].dart != master_maps[i].dart) - return -EINVAL; - } - for (i = 0; i < MAX_DARTS_PER_DEVICE; ++i) { if (!domain_maps[i].dart) break; @@ -671,6 +663,29 @@ static int apple_dart_domain_add_streams(struct apple_dart_domain *domain, true); } +static int apple_dart_test_dev_paging(struct iommu_domain *domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old) +{ + struct apple_dart_domain *dart_domain = to_dart_domain(domain); + struct apple_dart_master_cfg *cfg = dev_iommu_priv_get(dev); + struct apple_dart *dart = cfg->stream_maps[0].dart; + + if (dart->pgsize > PAGE_SIZE) + return -EINVAL; + if (dart_domain->finalized) { + int i; + + for (i = 0; i < MAX_DARTS_PER_DEVICE; ++i) { + if (dart_domain->stream_maps[i].dart != + cfg->stream_maps[i].dart) + return -EINVAL; + } + } + + return 0; +} + static int apple_dart_attach_dev_paging(struct iommu_domain *domain, struct device *dev, struct iommu_domain *old) @@ -693,6 +708,17 @@ static int apple_dart_attach_dev_paging(struct iommu_domain *domain, return 0; } +static int apple_dart_test_dev_identity(struct iommu_domain *domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old) +{ + struct apple_dart_master_cfg *cfg = dev_iommu_priv_get(dev); + + if (!cfg->supports_bypass) + return -EINVAL; + return 0; +} + static int apple_dart_attach_dev_identity(struct iommu_domain *domain, struct device *dev, struct iommu_domain *old) @@ -701,15 +727,13 @@ static int apple_dart_attach_dev_identity(struct iommu_domain *domain, struct apple_dart_stream_map *stream_map; int i; - if (!cfg->supports_bypass) - return -EINVAL; - for_each_stream_map(i, cfg, stream_map) apple_dart_hw_enable_bypass(stream_map); return 0; } static const struct iommu_domain_ops apple_dart_identity_ops = { + .test_dev = apple_dart_test_dev_identity, .attach_dev = apple_dart_attach_dev_identity, }; @@ -776,8 +800,11 @@ static struct iommu_domain *apple_dart_domain_alloc_paging(struct device *dev) if (dev) { struct apple_dart_master_cfg *cfg = dev_iommu_priv_get(dev); + struct apple_dart *dart = cfg->stream_maps[0].dart; int ret; + if (dart->pgsize > PAGE_SIZE) + return ERR_PTR(-EINVAL); ret = apple_dart_finalize_domain(dart_domain, cfg); if (ret) { kfree(dart_domain); @@ -1010,6 +1037,7 @@ static const struct iommu_ops apple_dart_iommu_ops = { .get_resv_regions = apple_dart_get_resv_regions, .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { + .test_dev = apple_dart_test_dev_paging, .attach_dev = apple_dart_attach_dev_paging, .map_pages = apple_dart_map_pages, .unmap_pages = apple_dart_unmap_pages, From patchwork Mon Oct 13 00:05:08 2025 Content-Type: text/plain; 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Sun, 12 Oct 2025 17:05:55 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 11/20] iommu/ipmmu-vmsa: Implement ipmmu_domain_test_device Date: Sun, 12 Oct 2025 17:05:08 -0700 Message-ID: <9460b6fc29dc82ac38bdb5769e37c4814d8f2ad0.1760312725.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: asahi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6B:EE_|DS7PR12MB6168:EE_ X-MS-Office365-Filtering-Correlation-Id: d29668f7-b0f3-4d4d-7a7a-08de09ec4fac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|7416014|376014|82310400026; X-Microsoft-Antispam-Message-Info: vuXvuekpdyn8qg/tBTu7TFp5SRHPdbszejxlEcxGpRWyf12LOYJqoLVzXNBaKbPW7Da0pmyWKF620D2ZWmqyNJ6k82XjsQUZeLAStls5ziCSufSAtJdiWlQVWmUcnD6o0KG13/6b+tKPXXHdkeigzo6Bbx+DWyW4o9BsUte+OXpm68vTDFHduzI8pnT30Gmq8GxIb3zGd/riBsacPQrTWeJPgh0xwFq0XJU8SHGKwo8BQJVLNxCWWjLXV1FWYVZXXp2pkgcZkV+zBkxALj7/j26IBIOT2uZ6hn6Iy1BRMhcEuUNvGQHWvpIPkvLVEyBURuITRlHNSYUIDVZpQuKtM9DxU1vFZnFAxvgAo0zJwYbXOG1fKhfVO932HEdKdRLR/FbtX9z8azxpvR7BsgICqkSFvA/ZBB2/1dXXxOeIhJWsAloxJ5sg7IpaYTp+7++bkMUwV4os7j/vJ9Y5mI5TBy16Zu7XO7EtMvzNFMa3CYrfTuhfZ/8ptIE/taZm02GHxM+iQp6XBUEj3ibRENObPli+8UcDQUNDon6FdVfooa2uiK+qiRa2H8va5r+XZDiUkmkApzQ4+VpHyXviHvbyKhJey+XMDJPMDntlqtafgAU0riUGbxYvt5cfH4SihREHkzcsK5e8VeMq7NXSmFPqFf2j16b9iCKpAh7OoIYH5GD35X2lUbM9czc9YUkW6OiHTr/SxEuzb2xALt67i9SLhS7DljPfueQXX/3vX2x3thOI83tY5CUXUsdfPv2u0+kuIA/LoLyNaqxPO/RqeacAkZHm+XtSrHBWWi0bXt53ARApnWfPMK171pIRFLdPZK1ttkDFH6KBS8DvEwWHhTtL5pZcjMtL7FTFIx/4HzYmMxOiZoynHOPCa2Oz0PS5CUEjN4VHna1CrWVG//9cgIsoTOBnzAplanvBQQ3q3uaA+gHiHoN/auT7PDNopg6M9c/UJ13NAoBV4Evo4pb3l6vHjqY1MKUzdnQv2sOPeroOF13BWi3Ok4RgPkfk229VnfAi3c2KgDz+1o0kJh868y6M5LALvhFRoUHYH6eOf4tubAmHK60I1lb4bTSdW8V2zl4w7ik+MthcNzRx+NPeBSXOfF5dqzr63o80XSsHyqWVZS+TCycuV7/qaQP0X6S0dDJ1rHF3FJ2b8esEbC9t4T/JZ20Ui46h+PBlW2WBeSBNIrlKPFZSv01Ag5ypXSjq8977gugEVhxSawnO2Ak9yHV4ivoyWbgG4lx4S/MVpHexB8rRM4cwc1TWXtAp7sxuzq2AeoAhzqU8luK3/W8WhwwysMS67vjJlnKO9ecQWmH4GExSuTbKbOpLOOrptybnY19dV4UJ4Z2VfXxUpc7r2SJc5Hi8hNtnMprxw7RYqr/rGfVdVCaXVWj80cVpGgiaeeZpILuDub7ByYCTc+ljOALywFl751shS4omDnHZ5ohuOnLInusxQBjtSeoJRhb7wemgeXZvLlsIYfvguY7BQftNfxhZQMdFkLCqvGApkO9g7eSgkKQfWuRz0lVGZZu1088ruObsFMoiw4Dxu/Zv7MJo9GuowjK+sUwinEFKI+U4BqY= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(7416014)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:06:08.5351 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d29668f7-b0f3-4d4d-7a7a-08de09ec4fac X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6168 Status: O Move sanity and compatibility tests from the attach_dev callback to the new test_dev callback function. The IOMMU core makes sure an attach_dev call must be invoked after a successful test_dev call. Signed-off-by: Nicolin Chen --- drivers/iommu/ipmmu-vmsa.c | 38 ++++++++++++++++++++++++++------------ 1 file changed, 26 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c index 6667ecc331f01..fdbb26ec6c632 100644 --- a/drivers/iommu/ipmmu-vmsa.c +++ b/drivers/iommu/ipmmu-vmsa.c @@ -589,6 +589,30 @@ static void ipmmu_domain_free(struct iommu_domain *io_domain) kfree(domain); } +static int ipmmu_domain_test_device(struct iommu_domain *io_domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old) +{ + struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); + struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); + + if (!mmu) { + dev_dbg(dev, "Cannot attach to IPMMU\n"); + return -ENXIO; + } + + scoped_guard(mutex, &domain->mutex) { + /* + * Something is wrong, we can't attach two devices using different + * IOMMUs to the same domain. + */ + if (domain->mmu && domain->mmu != mmu) + return -EINVAL; + } + + return 0; +} + static int ipmmu_attach_device(struct iommu_domain *io_domain, struct device *dev, struct iommu_domain *old) { @@ -598,11 +622,6 @@ static int ipmmu_attach_device(struct iommu_domain *io_domain, unsigned int i; int ret = 0; - if (!mmu) { - dev_err(dev, "Cannot attach to IPMMU\n"); - return -ENXIO; - } - mutex_lock(&domain->mutex); if (!domain->mmu) { @@ -616,13 +635,7 @@ static int ipmmu_attach_device(struct iommu_domain *io_domain, dev_info(dev, "Using IPMMU context %u\n", domain->context_id); } - } else if (domain->mmu != mmu) { - /* - * Something is wrong, we can't attach two devices using - * different IOMMUs to the same domain. - */ - ret = -EINVAL; - } else + } else /* domain->mmu == mmu */ dev_info(dev, "Reusing IPMMU context %u\n", domain->context_id); mutex_unlock(&domain->mutex); @@ -885,6 +898,7 @@ static const struct iommu_ops ipmmu_ops = { ? generic_device_group : generic_single_device_group, .of_xlate = ipmmu_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { + .test_dev = ipmmu_domain_test_device, .attach_dev = ipmmu_attach_device, .map_pages = ipmmu_map, .unmap_pages = ipmmu_unmap, From patchwork Mon Oct 13 00:05:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1894 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011059.outbound.protection.outlook.com [52.101.62.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADC93228CB0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:06:09.8977 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 707bbbf8-04d5-44fc-8d33-08de09ec507c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F69.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPF946CC24FA Status: O Move sanity and compatibility tests from the attach_dev callback to the new test_dev callback function. The IOMMU core makes sure an attach_dev call must be invoked after a successful test_dev call. Signed-off-by: Nicolin Chen --- drivers/iommu/sun50i-iommu.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c index d3b190be18b5a..d7517cfb260d5 100644 --- a/drivers/iommu/sun50i-iommu.c +++ b/drivers/iommu/sun50i-iommu.c @@ -797,16 +797,21 @@ static struct iommu_domain sun50i_iommu_identity_domain = { .ops = &sun50i_iommu_identity_ops, }; +static int sun50i_iommu_domain_test_device(struct iommu_domain *domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old) +{ + if (!sun50i_iommu_from_dev(dev)) + return -ENODEV; + return 0; +} + static int sun50i_iommu_attach_device(struct iommu_domain *domain, struct device *dev, struct iommu_domain *old) { struct sun50i_iommu_domain *sun50i_domain = to_sun50i_domain(domain); - struct sun50i_iommu *iommu; - - iommu = sun50i_iommu_from_dev(dev); - if (!iommu) - return -ENODEV; + struct sun50i_iommu *iommu = sun50i_iommu_from_dev(dev); dev_dbg(dev, "Attaching to IOMMU domain\n"); @@ -851,6 +856,7 @@ static const struct iommu_ops sun50i_iommu_ops = { .of_xlate = sun50i_iommu_of_xlate, .probe_device = sun50i_iommu_probe_device, .default_domain_ops = &(const struct iommu_domain_ops) { + .test_dev = sun50i_iommu_domain_test_device, .attach_dev = sun50i_iommu_attach_device, .flush_iotlb_all = sun50i_iommu_flush_iotlb_all, .iotlb_sync_map = sun50i_iommu_iotlb_sync_map, From patchwork Mon Oct 13 00:05:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1889 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012024.outbound.protection.outlook.com [52.101.43.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB67327280E; Mon, 13 Oct 2025 00:06:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.24 ARC-Seal: i=2; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:06:19.7447 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0b1f14b6-419a-495b-da9a-08de09ec564f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5754 Status: O Move sanity and compatibility tests from the attach_dev callback to the new test_dev callback function. The IOMMU core makes sure an attach_dev call must be invoked after a successful test_dev call. Signed-off-by: Nicolin Chen --- drivers/iommu/rockchip-iommu.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c index 85f3667e797c3..89cb65f76fe52 100644 --- a/drivers/iommu/rockchip-iommu.c +++ b/drivers/iommu/rockchip-iommu.c @@ -959,20 +959,25 @@ static int rk_iommu_enable(struct rk_iommu *iommu) return ret; } +static int rk_iommu_identity_test_dev(struct iommu_domain *domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old) +{ + /* Allow 'virtual devices' (eg drm) to detach from domain */ + if (!rk_iommu_from_dev(dev)) + return -ENODEV; + return 0; +} + static int rk_iommu_identity_attach(struct iommu_domain *identity_domain, struct device *dev, struct iommu_domain *old) { - struct rk_iommu *iommu; + struct rk_iommu *iommu = rk_iommu_from_dev(dev); struct rk_iommu_domain *rk_domain; unsigned long flags; int ret; - /* Allow 'virtual devices' (eg drm) to detach from domain */ - iommu = rk_iommu_from_dev(dev); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:06:15.4873 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d5b78e84-93e9-44c5-5cf8-08de09ec53d1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6967 Status: O Move sanity and compatibility tests from the attach_dev callback to the new test_dev callback function. The IOMMU core makes sure an attach_dev call must be invoked after a successful test_dev call. Following the test_dev guideline, replace -EEXIST with -EBUSY. Signed-off-by: Nicolin Chen --- drivers/iommu/msm_iommu.c | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index 819add75a6652..b7b21c97d1bd7 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -391,6 +391,31 @@ static struct iommu_device *msm_iommu_probe_device(struct device *dev) return &iommu->iommu; } +static int msm_iommu_domain_test_dev(struct iommu_domain *domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old) +{ + struct msm_iommu_dev *iommu; + + guard(spinlock_irqsave)(&msm_iommu_lock); + + list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) { + struct msm_iommu_ctx_dev *master = list_first_entry( + &iommu->ctx_list, struct msm_iommu_ctx_dev, list); + + if (master->of_node != dev->of_node) + continue; + list_for_each_entry(master, &iommu->ctx_list, list) { + if (master->num) { + dev_dbg(dev, "domain already attached"); + return -EBUSY; + } + } + } + + return 0; +} + static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev, struct iommu_domain *old) { @@ -414,11 +439,6 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev, goto fail; list_for_each_entry(master, &iommu->ctx_list, list) { - if (master->num) { - dev_err(dev, "domain already attached"); - ret = -EEXIST; - goto fail; - } master->num = msm_iommu_alloc_ctx(iommu->context_map, 0, iommu->ncb); @@ -695,6 +715,7 @@ static struct iommu_ops msm_iommu_ops = { .device_group = generic_device_group, .of_xlate = qcom_iommu_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { + .test_dev = msm_iommu_domain_test_dev, .attach_dev = msm_iommu_attach_dev, .map_pages = msm_iommu_map, .unmap_pages = msm_iommu_unmap, From patchwork Mon Oct 13 00:05:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1890 Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010008.outbound.protection.outlook.com [40.93.198.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E50002727E7; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:06:21.7879 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 648676e8-fa86-4032-ba1c-08de09ec5787 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4383 Status: O Move sanity and compatibility tests from the attach_dev callback to the new test_dev callback function. The IOMMU core makes sure an attach_dev call must be invoked after a successful test_dev call. Signed-off-by: Nicolin Chen --- drivers/iommu/fsl_pamu_domain.c | 50 +++++++++++++++++++++++++-------- 1 file changed, 38 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/fsl_pamu_domain.c b/drivers/iommu/fsl_pamu_domain.c index 9664ef9840d2c..fbdaa74936394 100644 --- a/drivers/iommu/fsl_pamu_domain.c +++ b/drivers/iommu/fsl_pamu_domain.c @@ -237,6 +237,43 @@ static int update_domain_stash(struct fsl_dma_domain *dma_domain, u32 val) return ret; } +static int fsl_pamu_domain_test_device(struct iommu_domain *domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old) +{ + struct fsl_dma_domain *dma_domain = to_fsl_dma_domain(domain); + const u32 *liodn; + int len, i; + + /* Use LIODN of the PCI controller while attaching a PCI device. */ + if (dev_is_pci(dev)) { + /* + * make dev point to pci controller device so we can get the + * LIODN programmed by u-boot. + */ + dev = pci_bus_to_host(to_pci_dev(dev)->bus)->parent; + } + + liodn = of_get_property(dev->of_node, "fsl,liodn", &len); + if (!liodn) { + pr_debug("missing fsl,liodn property at %pOF\n", dev->of_node); + return -ENODEV; + } + + guard(spin_lock_irqsave)(&dma_domain->domain_lock); + + for (i = 0; i < len / sizeof(u32); i++) { + /* Ensure that LIODN value is valid */ + if (liodn[i] < PAACE_NUMBER_ENTRIES) + continue; + pr_debug("Invalid liodn %d, attach device failed for %pOF\n", + liodn[i], dev->of_node); + return -ENODEV; + } + + return 0; +} + static int fsl_pamu_attach_device(struct iommu_domain *domain, struct device *dev, struct iommu_domain *old) { @@ -263,21 +300,9 @@ static int fsl_pamu_attach_device(struct iommu_domain *domain, } liodn = of_get_property(dev->of_node, "fsl,liodn", &len); - if (!liodn) { - pr_debug("missing fsl,liodn property at %pOF\n", dev->of_node); - return -ENODEV; - } spin_lock_irqsave(&dma_domain->domain_lock, flags); for (i = 0; i < len / sizeof(u32); i++) { - /* Ensure that LIODN value is valid */ - if (liodn[i] >= PAACE_NUMBER_ENTRIES) { - pr_debug("Invalid liodn %d, attach device failed for %pOF\n", - liodn[i], dev->of_node); - ret = -ENODEV; - break; - } - attach_device(dma_domain, liodn[i], dev); ret = pamu_set_liodn(dma_domain, dev, liodn[i]); if (ret) @@ -434,6 +459,7 @@ static const struct iommu_ops fsl_pamu_ops = { .probe_device = fsl_pamu_probe_device, .device_group = fsl_pamu_device_group, .default_domain_ops = &(const struct iommu_domain_ops) { + .test_dev = fsl_pamu_domain_test_device, .attach_dev = fsl_pamu_attach_device, .iova_to_phys = fsl_pamu_iova_to_phys, .free = fsl_pamu_domain_free, From patchwork Mon Oct 13 00:05:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1888 Received: from CO1PR03CU002.outbound.protection.outlook.com (mail-westus2azon11010026.outbound.protection.outlook.com [52.101.46.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BDF162741DA; Mon, 13 Oct 2025 00:06:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:06:23.0369 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bbac575b-5806-481b-3825-08de09ec5846 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3A.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9176 Status: O Move sanity and compatibility tests from the attach_dev callback to the new test_dev callback function. The IOMMU core makes sure an attach_dev call must be invoked after a successful test_dev call. Following the test_dev guideline, replace dev_err with dev_dbg. Signed-off-by: Nicolin Chen --- drivers/iommu/omap-iommu.c | 41 ++++++++++++++++++++++++-------------- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index 9f0057ccea573..26a7803e4144f 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -1392,9 +1392,6 @@ static int omap_iommu_attach_init(struct device *dev, int i; odomain->num_iommus = omap_iommu_count(dev); - if (!odomain->num_iommus) - return -ENODEV; - odomain->iommus = kcalloc(odomain->num_iommus, sizeof(*iommu), GFP_ATOMIC); if (!odomain->iommus) @@ -1431,6 +1428,31 @@ static void omap_iommu_detach_fini(struct omap_iommu_domain *odomain) odomain->iommus = NULL; } +static int omap_iommu_domain_test_dev(struct iommu_domain *domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old) +{ + struct omap_iommu_arch_data *arch_data = dev_iommu_priv_get(dev); + struct omap_iommu_domain *omap_domain = to_omap_domain(domain); + + if (!arch_data || !arch_data->iommu_dev) { + dev_dbg(dev, "device doesn't have an associated iommu\n"); + return -ENODEV; + } + + scoped_guard(spinlock, &omap_domain->lock) { + /* only a single client device can be attached to a domain */ + if (omap_domain->dev) { + dev_dbg(dev, "iommu domain is already attached\n"); + return -EINVAL; + } + if (!omap_iommu_count(dev)) + return -ENODEV; + } + + return 0; +} + static int omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev, struct iommu_domain *old) { @@ -1441,20 +1463,8 @@ static int omap_iommu_attach_dev(struct iommu_domain *domain, int ret = 0; int i; - if (!arch_data || !arch_data->iommu_dev) { - dev_err(dev, "device doesn't have an associated iommu\n"); - return -ENODEV; - } - spin_lock(&omap_domain->lock); - /* only a single client device can be attached to a domain */ - if (omap_domain->dev) { - dev_err(dev, "iommu domain is already attached\n"); - ret = -EINVAL; - goto out; - } - ret = omap_iommu_attach_init(dev, omap_domain); if (ret) { dev_err(dev, "failed to allocate required iommu data %d\n", @@ -1724,6 +1734,7 @@ static const struct iommu_ops omap_iommu_ops = { .device_group = generic_single_device_group, .of_xlate = omap_iommu_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { + .test_dev = omap_iommu_domain_test_dev, .attach_dev = omap_iommu_attach_dev, .map_pages = omap_iommu_map, .unmap_pages = omap_iommu_unmap, From patchwork Mon Oct 13 00:05:14 2025 Content-Type: text/plain; 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Sun, 12 Oct 2025 17:06:11 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 17/20] iommu/s390-iommu: Implement s390_iommu_domain_test_device Date: Sun, 12 Oct 2025 17:05:14 -0700 Message-ID: <792e825476efe58d14cc16cca18209a2b6088a4b.1760312725.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: asahi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3A:EE_|SA1PR12MB6799:EE_ X-MS-Office365-Filtering-Correlation-Id: 62766a9d-148d-428f-3aae-08de09ec58e0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026|7416014; X-Microsoft-Antispam-Message-Info: pYp+ICfEFqQUQUY/ydYHFnkJR4znATyhcdCLGd3W0f4VVhnDQloIvK8csF27FyogxOV1R3cokNBys7DNRLSEGI5AmzcnJSUANyFxMAJlon0ElkIYLOU+wz0rvurqqenaNA0VPFaUIZLQaTctnBqgZSl74C2qVEIKhWzfoNj+4rGvjAulDhxlrS/6PrclOzihD0FB5azER3yZGemSgcGX1vYPprm1cTChiWqtbAZMTF5Ks/ekgabORs25pk/B78lztgAO8n/cmweEKT7G42MJosI0bJ/FH3WSWyrcOxTHiusIRe4e7VrOTMER+fw4x+hqcoSDvFWfFAltugEP39Q1nHploXB+WB8ehI6tjacbiDIfrinNdtpbPzaiNeJuNQDIt1asW93kFASMcD6DeXTt9IGmLyp/RqaPM86xzdcNSfd2EPT6xlwX2O79tkGYF8XOO+V8b2Y0wHbbYeywfRzWoQ2KtQvyxsuZiWohvTByDJQ7A9Afpn5nvvKbHJMEEDXb6FYaTqwXbUOtOlDB3kBpYXnKCuin0IlcDYkA1QM3R2qh9yZqiuFGo3UrhXXVyI5qj9t/S2EHyIBWnsm7tSUxkL+Qef7vGLqzRfZVHVrQD7d6XrV2I5MzsHNrglSNuXOuDHD+L1ucjc1eEvJ/PtzGNO6jdOztmSSXWGqhZdZEJ8HhJmOu0+zQlAvKHhoEg/WRUH8sFPu3dRYs1XJLDwATg0HqpzN6xlGEuUExaWjwF4cgAeeHLLabGDB37ViEnyLOhOs9SdQZqUtLcV7FjNQC+V+PFKFo3LtBzGBVFhL2U8vR51MqTrUETdYaZiBM5DgfLMuNnlJJcN3HOf5uaBOmRfkPMD4io+XT21IMK2xEgHmU6RMjCh6Bo0lJiqsmP/DE7MOOcB83X8gLwfyd6Tf+qpviqtpBDnj33Q1Flj25GbDGve9StZPSUXXEiAZBahytopbApyslwR9S5FOu1iPgsk2goG1vEVwPZV0k9kiG7netgKxTBCU7doDpXlohqNXY1MfMaMoZDWk+oJJcp6v7kOXJ08h6GCf2tHiZGreKJ3a/YIJzyD+WCIW2m6b7/nAWS4OuBh0aCnmUHytyICimtrMsdG2t6duukyX5kzCJHA+7hB+xs8KnEOP+p8BkiTrBnt25CmKNBFpTYfAYSPR18TYnCxQkRIhZ+zcl6cV6D5liDpNdGCW6/tDb5NL9+sgrhDoFVZxfhwT6HOa1jyjP8jGlI1Jw4pxRgSVxgSMEjva+/4j8EgkGsu9R9kxK4xnkeURygDU5uVGM5/6H5MRXRwujWJLeePa95q6LOgot5oQXmdpGB1T0L/rejnAXj2GDB9eVZFcRj7EHaHlHdLswB/umo+ALRgKXI52wuQtrcqbjr2t5dBhER2r4SdxRIknX6N8KWegUDRSwWCGz42w9nFZ4/+vDw7oIXdJD6zTfD4RaSYI9td25Tc0Hzp6MOHtGYsu7/zaSTcz/p81rQt6lAaebCZP2tWELF9BEsKOZWqXhqHkZqUuzjJomD0xJOX8+Umks1xsc0eWBNIeGVOfbyY+RcEw/zxJfM6iZi5hX5j0= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:06:24.0454 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 62766a9d-148d-428f-3aae-08de09ec58e0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3A.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6799 Status: O Move sanity and compatibility tests from the attach_dev callback to the new test_dev callback function. The IOMMU core makes sure an attach_dev call must be invoked after a successful test_dev call. Signed-off-by: Nicolin Chen --- drivers/iommu/s390-iommu.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/s390-iommu.c b/drivers/iommu/s390-iommu.c index 366e47978ac07..3c6141a4a1faf 100644 --- a/drivers/iommu/s390-iommu.c +++ b/drivers/iommu/s390-iommu.c @@ -694,6 +694,20 @@ static int blocking_domain_attach_device(struct iommu_domain *domain, return 0; } +static int s390_iommu_domain_test_device(struct iommu_domain *domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old) +{ + struct zpci_dev *zdev = to_zpci_dev(dev); + + if (!zdev) + return -ENODEV; + if (WARN_ON(domain->geometry.aperture_start > zdev->end_dma || + domain->geometry.aperture_end < zdev->start_dma)) + return -EINVAL; + return 0; +} + static int s390_iommu_attach_device(struct iommu_domain *domain, struct device *dev, struct iommu_domain *old) @@ -704,13 +718,6 @@ static int s390_iommu_attach_device(struct iommu_domain *domain, u8 status; int cc; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:06:25.0482 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b7c00cf5-9244-42ad-f1e0-08de09ec5978 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6209 Status: O Move sanity and compatibility tests from the attach_dev callback to the new test_dev callback function. The IOMMU core makes sure an attach_dev call must be invoked after a successful test_dev call. Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/selftest.c | 45 +++++++++++++++++++++++++------- 1 file changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/iommufd/selftest.c b/drivers/iommu/iommufd/selftest.c index 5661d2da2b679..f9c871a280b03 100644 --- a/drivers/iommu/iommufd/selftest.c +++ b/drivers/iommu/iommufd/selftest.c @@ -58,6 +58,7 @@ enum { MOCK_PFN_HUGE_IOVA = _MOCK_PFN_START << 2, }; +static struct iopf_queue *mock_iommu_iopf_queue; static int mock_dev_enable_iopf(struct device *dev, struct iommu_domain *domain); static void mock_dev_disable_iopf(struct device *dev, struct iommu_domain *domain); @@ -215,6 +216,37 @@ static inline struct selftest_obj *to_selftest_obj(struct iommufd_object *obj) return container_of(obj, struct selftest_obj, obj); } +static int mock_domain_nop_test(struct iommu_domain *domain, struct device *dev, + ioasid_t pasid, struct iommu_domain *old) +{ + struct mock_dev *mdev = to_mock_dev(dev); + + if (domain->dirty_ops && (mdev->flags & MOCK_FLAGS_DEVICE_NO_DIRTY)) + return -EINVAL; + + iommu_group_mutex_assert(dev); + if (domain->type == IOMMU_DOMAIN_NESTED) { + struct mock_viommu *viommu = + to_mock_nested(domain)->mock_viommu; + unsigned long vdev_id = 0; + int rc; + + if (viommu) { + rc = iommufd_viommu_get_vdev_id(&viommu->core, dev, + &vdev_id); + if (rc) + return rc; + } + } + + if (domain->iopf_handler) { + if (!mock_iommu_iopf_queue) + return -ENODEV; + } + + return 0; +} + static int mock_domain_nop_attach(struct iommu_domain *domain, struct device *dev, struct iommu_domain *old) { @@ -223,16 +255,13 @@ static int mock_domain_nop_attach(struct iommu_domain *domain, unsigned long vdev_id = 0; int rc; - if (domain->dirty_ops && (mdev->flags & MOCK_FLAGS_DEVICE_NO_DIRTY)) - return -EINVAL; - iommu_group_mutex_assert(dev); if (domain->type == IOMMU_DOMAIN_NESTED) { new_viommu = to_mock_nested(domain)->mock_viommu; if (new_viommu) { rc = iommufd_viommu_get_vdev_id(&new_viommu->core, dev, &vdev_id); - if (rc) + if (WARN_ON(rc)) return rc; } } @@ -296,6 +325,7 @@ static int mock_domain_set_dev_pasid_nop(struct iommu_domain *domain, } static const struct iommu_domain_ops mock_blocking_ops = { + .test_dev = mock_domain_nop_test, .attach_dev = mock_domain_nop_attach, .set_dev_pasid = mock_domain_set_dev_pasid_nop }; @@ -630,8 +660,6 @@ static bool mock_domain_capable(struct device *dev, enum iommu_cap cap) return false; } -static struct iopf_queue *mock_iommu_iopf_queue; - static struct mock_iommu_device { struct iommu_device iommu_dev; struct completion complete; @@ -658,9 +686,6 @@ static int mock_dev_enable_iopf(struct device *dev, struct iommu_domain *domain) if (!domain || !domain->iopf_handler) return 0; - if (!mock_iommu_iopf_queue) - return -ENODEV; - if (mdev->iopf_refcount) { mdev->iopf_refcount++; return 0; @@ -958,6 +983,7 @@ static const struct iommu_ops mock_ops = { .default_domain_ops = &(struct iommu_domain_ops){ .free = mock_domain_free, + .test_dev = mock_domain_nop_test, .attach_dev = mock_domain_nop_attach, .map_pages = mock_domain_map_pages, .unmap_pages = mock_domain_unmap_pages, @@ -1021,6 +1047,7 @@ mock_domain_cache_invalidate_user(struct iommu_domain *domain, static struct iommu_domain_ops domain_nested_ops = { .free = mock_domain_free_nested, + .test_dev = mock_domain_nop_test, .attach_dev = mock_domain_nop_attach, .cache_invalidate_user = mock_domain_cache_invalidate_user, .set_dev_pasid = mock_domain_set_dev_pasid_nop, From patchwork Mon Oct 13 00:05:16 2025 Content-Type: text/plain; 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Sun, 12 Oct 2025 17:06:16 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 19/20] iommu/virtio-iommu: Implement viommu_domain_test_dev Date: Sun, 12 Oct 2025 17:05:16 -0700 Message-ID: <562f5a6c9f55066dd50f95210e5669e256852d36.1760312725.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: asahi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F69:EE_|CY3PR12MB9703:EE_ X-MS-Office365-Filtering-Correlation-Id: b2ff0e49-a48a-4535-974a-08de09ec5b89 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: tIsNpha0J/T8syGzcUg54ECBkPWdm8IaqKY6Av+DtEGBJIQWPXP0+PSlnv2p2t+UN+dtXd0e+dxefSepkTA4r2/goYJrNOBeMldldk4rgmeOWW25CCTNeODM5i6iiM/Qi2tOkqV3iZQbAWMucaOG8pxJg+5S4CgsRksEfi7syUfY1mwcVJbXvEESY/dK0SAW0mtsVwNkrXr0S0Zp6tMF3uOCzTGuQZgMKq1ws9pTuxQDzGuL+WL1hqkNyRvf2gG7hWAte8zTow4lUkK8Vlh4qp7GWtlp0X8P8uElr25dSeZEFUMGMkll4rHR8dSGRYGcSXPijwLR1RIx/SX2hLXOr//ze+aiSRN7jhFhQ/ClS6yc8Lac+VDkseExJWW0eWpuKBPsPj0u836HXoBjGFmjTpZAgV6ylqGfxNWAsC4WlKahPvvTFbb+xw3y4Nj34d9GcQX0MJUIQtswiYpshP+LxnrkMWmKEInPJ9lat7h54KKPxS0PQ4YX5TMe9N7QMMDEdngZFvPZPyuSr6H2MbTqQcdTupS7CS1jPD7q5EJrrjMeBiMkVOXH7Cv+5dI+GhXsclGdVS9eZn7yEZxqHlyVr7qoxvHjr6/Vts3CeaghlPneput/w0y2bED0Cj/XoSd6wsVt90Kfk1OuS/1djnoTfdxykVcSh0ILWyPbBTuQO3JcrOj5TntZ5mkASTTqsikfK7IBE/JPVuOC00EVjLWKTpRd2TyZuCQlyklVTj6MwlS8MwBDHGDz8VJtgM5ujZXyQUBn4EvYBnebw8o7jm4pCvmYP7fCN4W/9Kox9Fr267MXf54tr/3i2KozLZb+iCoNccMdyrjhGM3UMW6N9p6w7mqpD8kcq2SoJF2xZqZAmTtUuX9dv7vLUuSCUed33f6W06nQi9+rIj+abmVsPKnq9/07QfFsyYCTFUrLFG6kg7M2vuUuwUZs22+3Jo/g+6m37m62g62/nYDHYfVuG/xw9xdU5ipZZVSuSMKYflKl6ePXImkGoGKHs7pHcGJYtPI79nQJW9euP86Vr/OdxoTjLI/CK4AklLEVMuZq0EdoCq/gL7MYGVA3xd/JzveVnOfyR2l7Xf4gxFGEFgJA9iV6FJz7UtxKJLNeFajyceCx7xs+w8sFDsrSQNZp5RhXNxGDDgEzrzZG1qIxUdeBjERrZ2S8J32Dj9yCQ4iM1Vt6eYdSL66yav8UDnYNaWODdK/yDUC/uqF/2AXoM2oXUqDMfOzqzgcqw2JjIfKKvlmrBLtkdeGnH3ZlqvnxwWF5fmLgwl4hMfDB5HA+sZ4gCnOe/b2KeLQ4ppamPo3yS9uP+A4j5gc9zsykbDfeiUug+JP3HO3jzNMmQxEAUxq/8c2qfG8graFc9V8VYo3jaosS8nzuFqwVczYT/9ljdrRot5U9LuLrEeZ+bWemEbLRom5d0z8cD0hBomO4jYUOdhmprlrdTkGC0Hu9bYu7ROiapAzlq/c6hSVAMkg5sUNau7yeQDXuBKD6yLBBBRuDytnYA02xWMS0WWHGW0xlztLv8rqqyNDQ35ZaNyPOLfuLoDkp9zgf1FQU5+FBXvTq7hipu7U= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:06:28.4377 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b2ff0e49-a48a-4535-974a-08de09ec5b89 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F69.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9703 Status: O Move sanity and compatibility tests from the attach_dev callback to the new test_dev callback function. The IOMMU core makes sure an attach_dev call must be invoked after a successful test_dev call. Signed-off-by: Nicolin Chen --- drivers/iommu/virtio-iommu.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/virtio-iommu.c b/drivers/iommu/virtio-iommu.c index d314fa5cd8476..766dded8fc8a6 100644 --- a/drivers/iommu/virtio-iommu.c +++ b/drivers/iommu/virtio-iommu.c @@ -730,6 +730,18 @@ static struct iommu_domain *viommu_domain_alloc_identity(struct device *dev) return domain; } +static int viommu_domain_test_dev(struct iommu_domain *domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old) +{ + struct viommu_endpoint *vdev = dev_iommu_priv_get(dev); + struct viommu_domain *vdomain = to_viommu_domain(domain); + + if (vdomain->viommu != vdev->viommu) + return -EINVAL; + return 0; +} + static int viommu_attach_dev(struct iommu_domain *domain, struct device *dev, struct iommu_domain *old) { @@ -738,9 +750,6 @@ static int viommu_attach_dev(struct iommu_domain *domain, struct device *dev, struct viommu_endpoint *vdev = dev_iommu_priv_get(dev); struct viommu_domain *vdomain = to_viommu_domain(domain); - if (vdomain->viommu != vdev->viommu) - return -EINVAL; - /* * In the virtio-iommu device, when attaching the endpoint to a new * domain, it is detached from the old one and, if as a result the @@ -1099,6 +1108,7 @@ static const struct iommu_ops viommu_ops = { .of_xlate = viommu_of_xlate, .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { + .test_dev = viommu_domain_test_dev, .attach_dev = viommu_attach_dev, .map_pages = viommu_map_pages, .unmap_pages = viommu_unmap_pages, From patchwork Mon Oct 13 00:05:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1884 Received: from BN1PR04CU002.outbound.protection.outlook.com (mail-eastus2azon11010022.outbound.protection.outlook.com [52.101.56.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C54F684A35; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2025 00:06:30.8053 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9bb0a35-4e89-446e-67cf-08de09ec5ce7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9704 Status: O Move sanity and compatibility tests from the attach_dev callback to the new test_dev callback function. The IOMMU core makes sure an attach_dev call must be invoked after a successful test_dev call. Signed-off-by: Nicolin Chen --- drivers/iommu/tegra-smmu.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 336e0a3ff41fb..cfbe67678a426 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -489,6 +489,18 @@ static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu, mutex_unlock(&smmu->lock); } +static int tegra_smmu_domain_test_dev(struct iommu_domain *domain, + struct device *dev, ioasid_t pasid, + struct iommu_domain *old) +{ + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + + if (!fwspec || !fwspec->num_ids) + return -ENOENT; + + return 0; +} + static int tegra_smmu_attach_dev(struct iommu_domain *domain, struct device *dev, struct iommu_domain *old) { @@ -498,9 +510,6 @@ static int tegra_smmu_attach_dev(struct iommu_domain *domain, unsigned int index; int err; - if (!fwspec) - return -ENOENT; - for (index = 0; index < fwspec->num_ids; index++) { err = tegra_smmu_as_prepare(smmu, as); if (err) @@ -509,9 +518,6 @@ static int tegra_smmu_attach_dev(struct iommu_domain *domain, tegra_smmu_enable(smmu, fwspec->ids[index], as->id); } - if (index == 0) - return -ENODEV; - return 0; disable: @@ -532,9 +538,6 @@ static int tegra_smmu_identity_attach(struct iommu_domain *identity_domain, struct tegra_smmu *smmu; unsigned int index; - if (!fwspec) - return -ENODEV; - if (old == identity_domain || !old) return 0; @@ -548,6 +551,7 @@ static int tegra_smmu_identity_attach(struct iommu_domain *identity_domain, } static struct iommu_domain_ops tegra_smmu_identity_ops = { + .test_dev = tegra_smmu_domain_test_dev, .attach_dev = tegra_smmu_identity_attach, }; @@ -1005,6 +1009,7 @@ static const struct iommu_ops tegra_smmu_ops = { .device_group = tegra_smmu_device_group, .of_xlate = tegra_smmu_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { + .test_dev = tegra_smmu_domain_test_dev, .attach_dev = tegra_smmu_attach_dev, .map_pages = tegra_smmu_map, .unmap_pages = tegra_smmu_unmap,