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a=ed25519-sha256; t=1776602788; l=1615; i=michal.piekos@mmpsystems.pl; s=20260301; h=from:subject:message-id; bh=dD/RfwTsFCY3zQ8t1EhNPKXgRitASUKlWpSEoGxz1ds=; b=4nrUKn+94IDdME4xFuYNSnTvSuLhM+KuSC/GFrXESVLIh2b4USkQsHXGE6Wc6uzTa+NahW8l3 52ir+K2U/Y9B9eKDTLvl+S2C1Q3uPalViRvckW5G43m32MaSMppxa4G X-Developer-Key: i=michal.piekos@mmpsystems.pl; a=ed25519; pk=Aixyx03If7ZDamiKKN0lsa+0mtA+WjIuIf2ZQVYNBqg= X-Authenticated-Id: michal.piekos@mmpsystems.pl X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= H616 is compatible with the existing sun5i binding, but require its own compatible string to differentiate register offsets. T113-S3 uses same offsets as H616. Add allwinner,sun50i-h616-hstimer Add allwinner,sun8i-t113s-hstimer with fallback to allwinner,sun50i-h616-hstimer Extend schema condition for interrupts to cover H616 compatible variant. Signed-off-by: Michal Piekos --- .../devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml index f1853daec2f9..bb60a85dc34b 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml +++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml @@ -15,9 +15,13 @@ properties: oneOf: - const: allwinner,sun5i-a13-hstimer - const: allwinner,sun7i-a20-hstimer + - const: allwinner,sun50i-h616-hstimer - items: - const: allwinner,sun6i-a31-hstimer - const: allwinner,sun7i-a20-hstimer + - items: + - const: allwinner,sun8i-t113s-hstimer + - const: allwinner,sun50i-h616-hstimer reg: maxItems: 1 @@ -45,7 +49,9 @@ required: if: properties: compatible: - const: allwinner,sun5i-a13-hstimer + enum: + - allwinner,sun5i-a13-hstimer + - allwinner,sun50i-h616-hstimer then: properties: From patchwork Sun Apr 19 12:46:08 2026 Content-Type: text/plain; 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Add selectable register layout structures. Add H616 compatible string to OF match table. Signed-off-by: Michal Piekos --- drivers/clocksource/timer-sun5i.c | 56 ++++++++++++++++++++++++++++++++++----- 1 file changed, 50 insertions(+), 6 deletions(-) diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-sun5i.c index f827d3f98f60..125abc11c3c3 100644 --- a/drivers/clocksource/timer-sun5i.c +++ b/drivers/clocksource/timer-sun5i.c @@ -21,18 +21,52 @@ #define TIMER_IRQ_EN_REG 0x00 #define TIMER_IRQ_EN(val) BIT(val) #define TIMER_IRQ_ST_REG 0x04 -#define TIMER_CTL_REG(val) (0x20 * (val) + 0x10) #define TIMER_CTL_ENABLE BIT(0) #define TIMER_CTL_RELOAD BIT(1) -#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4) #define TIMER_CTL_ONESHOT BIT(7) -#define TIMER_INTVAL_LO_REG(val) (0x20 * (val) + 0x14) -#define TIMER_INTVAL_HI_REG(val) (0x20 * (val) + 0x18) -#define TIMER_CNTVAL_LO_REG(val) (0x20 * (val) + 0x1c) -#define TIMER_CNTVAL_HI_REG(val) (0x20 * (val) + 0x20) +#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4) +#define TIMER_CTL_REG(val) \ + (soc_base->stride * (val) + soc_base->ctl_base) +#define TIMER_INTVAL_LO_REG(val) \ + (soc_base->stride * (val) + soc_base->intval_lo_base) +#define TIMER_INTVAL_HI_REG(val) \ + (soc_base->stride * (val) + soc_base->intval_hi_base) +#define TIMER_CNTVAL_LO_REG(val) \ + (soc_base->stride * (val) + soc_base->cntval_lo_base) +#define TIMER_CNTVAL_HI_REG(val) \ + (soc_base->stride * (val) + soc_base->cntval_hi_base) #define TIMER_SYNC_TICKS 3 +struct sunxi_timer_base { + u32 ctl_base; + u32 intval_lo_base; + u32 intval_hi_base; + u32 cntval_lo_base; + u32 cntval_hi_base; + u32 stride; +}; + +static const struct sunxi_timer_base sun5i_base = { + .ctl_base = 0x10, + .intval_lo_base = 0x14, + .intval_hi_base = 0x18, + .cntval_lo_base = 0x1c, + .cntval_hi_base = 0x20, + .stride = 0x20 +}; + +static const struct sunxi_timer_base sun50i_base = { + .ctl_base = 0x20, + .intval_lo_base = 0x24, + .intval_hi_base = 0x28, + .cntval_lo_base = 0x2c, + .cntval_hi_base = 0x30, + .stride = 0x20 +}; + +static const struct sunxi_timer_base *soc_base; + struct sun5i_timer { void __iomem *base; struct clk *clk; @@ -238,6 +272,7 @@ static int sun5i_setup_clockevent(struct platform_device *pdev, static int sun5i_timer_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct device_node *node = dev_of_node(&pdev->dev); struct sun5i_timer *st; struct reset_control *rstc; void __iomem *timer_base; @@ -251,6 +286,14 @@ static int sun5i_timer_probe(struct platform_device *pdev) platform_set_drvdata(pdev, st); + if (!node) + return -EINVAL; + + if (of_device_is_compatible(node, "allwinner,sun50i-h616-hstimer")) + soc_base = &sun50i_base; + else + soc_base = &sun5i_base; + timer_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(timer_base)) { dev_err(dev, "Can't map registers\n"); @@ -314,6 +357,7 @@ static void sun5i_timer_remove(struct platform_device *pdev) static const struct of_device_id sun5i_timer_of_match[] = { { .compatible = "allwinner,sun5i-a13-hstimer" }, { .compatible = "allwinner,sun7i-a20-hstimer" }, + { .compatible = "allwinner,sun50i-h616-hstimer" }, {}, }; MODULE_DEVICE_TABLE(of, sun5i_timer_of_match); From patchwork Sun Apr 19 12:46:09 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Piekos X-Patchwork-Id: 2022 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id A9BF21C19CE for ; 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Tested on Orange Pi Zero 3: - hstimer is registered as clocksource - switching clocksource at runtime works - after rating increase hstimer operates as a broadcast clockevent device Signed-off-by: Michal Piekos --- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index bf054869e78b..0713a17264ec 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -237,6 +237,15 @@ timer0: timer@3009000 { clocks = <&osc24M>; }; + hstimer@3005000 { + compatible = "allwinner,sun50i-h616-hstimer"; + reg = <0x03005000 0x1000>; + interrupts = , + ; + clocks = <&ccu CLK_BUS_HSTIMER>; + resets = <&ccu RST_BUS_HSTIMER>; + }; + watchdog: watchdog@30090a0 { compatible = "allwinner,sun50i-h616-wdt", "allwinner,sun6i-a31-wdt"; From patchwork Sun Apr 19 12:46:10 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Piekos X-Patchwork-Id: 2021 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 5C0591C0C97 for ; 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a=ed25519-sha256; t=1776602788; l=1183; i=michal.piekos@mmpsystems.pl; s=20260301; h=from:subject:message-id; bh=XIZIjEbSaQwU8SHGIG2f7vQGlj5NsG6mt1shAs4DnYk=; b=TWIqqEA3ErGL3FCRddP1xCmGyg6MgptJEaxLHGDfIlXCIwxmqmSSlTDe+7h5M1kN/P9BSgKau jlIiAaWCfkTBQMbfJDBTIr2MWKsAwz5QTib25pUuAMasN+08WxHdfMO X-Developer-Key: i=michal.piekos@mmpsystems.pl; a=ed25519; pk=Aixyx03If7ZDamiKKN0lsa+0mtA+WjIuIf2ZQVYNBqg= X-Authenticated-Id: michal.piekos@mmpsystems.pl X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Describe high speed timer block on Allwinner T113-S3. Tested on LCPI-PC-T113/F113: - hstimer is registered as clocksource - switching clocksource at runtime works - after rating increase hstimer operates as a broadcast clockevent device Signed-off-by: Michal Piekos --- arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi index 424f4a2487e2..f811ae0924d6 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi @@ -34,6 +34,18 @@ cpu1: cpu@1 { }; }; + soc { + hstimer@3008000 { + compatible = "allwinner,sun8i-t113s-hstimer", + "allwinner,sun50i-h616-hstimer"; + reg = <0x03008000 0x1000>; + interrupts = , + ; + clocks = <&ccu CLK_BUS_HSTIMER>; + resets = <&ccu RST_BUS_HSTIMER>; + }; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x03021000 0x1000>,