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Thu, 23 Apr 2026 13:40:33 -0400 (EDT) From: Kevin Mehall To: Mark Brown , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Mirko Vogt , Ralf Schlatterbeck , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] spi: sun6i: Honor CS setup delay on the first transfer with native CS Date: Thu, 23 Apr 2026 11:40:00 -0600 Message-ID: <20260423174001.2797797-2-km@kevinmehall.net> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260423174001.2797797-1-km@kevinmehall.net> References: <20260423174001.2797797-1-km@kevinmehall.net> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-0.66 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.232.135.74:from]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; MAILLIST(-0.15)[generic]; MIME_GOOD(-0.10)[text/plain]; BAD_REP_POLICIES(0.10)[]; HAS_LIST_UNSUB(-0.01)[]; R_DKIM_ALLOW(0.00)[kevinmehall.net:s=fm1,messagingengine.com:s=fm2]; FROM_HAS_DN(0.00)[]; PRECEDENCE_BULK(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[kevinmehall.net:email,kevinmehall.net:dkim,messagingengine.com:dkim,sto.lore.kernel.org:rdns,sto.lore.kernel.org:helo]; TAGGED_RCPT(0.00)[]; RCVD_COUNT_SEVEN(0.00)[7]; FUZZY_BLOCKED(0.00)[rspamd.com]; FROM_NEQ_ENVFROM(0.00)[km@kevinmehall.net,linux-sunxi@lists.linux.dev]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; ASN(0.00)[asn:63949, ipnet:172.232.128.0/19, country:SG]; R_SPF_ALLOW(0.00)[+ip4:172.232.135.74:c]; DKIM_TRACE(0.00)[kevinmehall.net:+,messagingengine.com:+]; TO_DN_SOME(0.00)[]; FORGED_SENDER_MAILLIST(0.00)[]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[100.90.174.1:received]; TAGGED_FROM(0.00)[bounces-22927-noreply=patchwork.local]; DMARC_POLICY_ALLOW(0.00)[kevinmehall.net,reject]; FREEMAIL_TO(0.00)[kernel.org,gmail.com,sholland.org,nanl.de,runtux.com,vger.kernel.org,lists.infradead.org,lists.linux.dev]; RCVD_TLS_LAST(0.00)[]; RCPT_COUNT_SEVEN(0.00)[10]; MIME_TRACE(0.00)[0:+]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.232.135.74:from] X-Rspamd-Queue-Id: C6D741C0063 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Move SUN6I_TFR_CTL_CS_MANUAL to sun6i_spi_set_cs. The CS_MANUAL bit is required for CS_LEVEL to affect the CS pin state. Set it in the same place as other CS bits to ensure that set_cs takes effect immediately, and to make it easier to reason about CS behavior. Previously, this bit was not set until the first transfer's sun6i_spi_transfer_one. That meant that on the first transfer, set_cs would have no immediate effect, and the CS falling edge was deferred until the bit is set in transfer_one. As any configured cs_setup delay happens between those two steps, the configured delay would have effectively been ignored on the very first transfer. This change makes the first transfer work like subsequent ones. Link: https://lore.kernel.org/linux-spi/d199f72a-093b-41bb-b33e-b6685563f704@app.fastmail.com/ Fixes: 3558fe900e8a ("spi: sunxi: Add Allwinner A31 SPI controller driver") Signed-off-by: Kevin Mehall --- drivers/spi/spi-sun6i.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c index 240e46f84f7b..fc228574ed38 100644 --- a/drivers/spi/spi-sun6i.c +++ b/drivers/spi/spi-sun6i.c @@ -185,6 +185,10 @@ static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) u32 reg; reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); + + /* SUN6I_TFR_CTL_CS_LEVEL sets CS rather than the controller doing it automatically */ + reg |= SUN6I_TFR_CTL_CS_MANUAL; + reg &= ~SUN6I_TFR_CTL_CS_MASK; reg |= SUN6I_TFR_CTL_CS(spi_get_chipselect(spi, 0)); @@ -364,9 +368,6 @@ static int sun6i_spi_transfer_one(struct spi_controller *host, reg |= SUN6I_TFR_CTL_DHB; } - /* We want to control the chip select manually */ - reg |= SUN6I_TFR_CTL_CS_MANUAL; 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Thu, 23 Apr 2026 13:40:41 -0400 (EDT) From: Kevin Mehall To: Mark Brown , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Mirko Vogt , Ralf Schlatterbeck , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] spi: sun6i: Set SPI mode in prepare_message Date: Thu, 23 Apr 2026 11:40:01 -0600 Message-ID: <20260423174001.2797797-3-km@kevinmehall.net> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260423174001.2797797-1-km@kevinmehall.net> References: <20260423174001.2797797-1-km@kevinmehall.net> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-0.66 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.105.105.114:from]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; MAILLIST(-0.15)[generic]; BAD_REP_POLICIES(0.10)[]; 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RCVD_TLS_LAST(0.00)[]; RCPT_COUNT_SEVEN(0.00)[10]; MIME_TRACE(0.00)[0:+]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.105.105.114:from] X-Rspamd-Queue-Id: 1A4691C0063 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= With a GPIO chip select, CS is asserted before entering transfer_one. The spi-sun6i driver previously configured the SPI mode (including clock polarity) and enabled the bus in transfer_one, which can cause an extraneous SCK transition with CS asserted, corrupting the transferred data. This patch moves the SPI mode configuration and bus enable to the spi_prepare_message callback, ensuring that SCK is driven to the correct level prior to asserting CS. A previous fix for a related issue (0d7993b234c9f) was incomplete in that it only delayed enabling the SCK output drive to prevent it from being driven at the wrong level when resuming from autosuspend, but didn't help if switching CPOL modes between chip selects while active, or if SCK floats to the opposite level when suspended. Fixes: 0d7993b234c9 ("spi: spi-sun6i: Fix chipselect/clock bug") Signed-off-by: Kevin Mehall --- drivers/spi/spi-sun6i.c | 67 +++++++++++++++++++++++++---------------- 1 file changed, 41 insertions(+), 26 deletions(-) diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c index fc228574ed38..983e791e3396 100644 --- a/drivers/spi/spi-sun6i.c +++ b/drivers/spi/spi-sun6i.c @@ -205,6 +205,44 @@ static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) return SUN6I_MAX_XFER_SIZE - 1; } +static int sun6i_spi_prepare_message(struct spi_controller *ctlr, + struct spi_message *msg) +{ + struct sun6i_spi *sspi = spi_controller_get_devdata(ctlr); + struct spi_device *spi = msg->spi; + u32 reg; + + /* Set the mode bits in the transfer control register */ + reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); + + if (spi->mode & SPI_CPOL) + reg |= SUN6I_TFR_CTL_CPOL; + else + reg &= ~SUN6I_TFR_CTL_CPOL; + + if (spi->mode & SPI_CPHA) + reg |= SUN6I_TFR_CTL_CPHA; + else + reg &= ~SUN6I_TFR_CTL_CPHA; + + if (spi->mode & SPI_LSB_FIRST) + reg |= SUN6I_TFR_CTL_FBS; + else + reg &= ~SUN6I_TFR_CTL_FBS; + + sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); + + /* + * Now that the clock polarity is configured, enable the bus if the + * controller was previously suspended. + */ + reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG); + reg |= SUN6I_GBL_CTL_BUS_ENABLE; + sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg); + + return 0; +} + static void sun6i_spi_dma_rx_cb(void *param) { struct sun6i_spi *sspi = param; @@ -336,31 +374,12 @@ static int sun6i_spi_transfer_one(struct spi_controller *host, sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, reg); - /* - * Setup the transfer control register: Chip Select, - * polarities, etc. - */ - reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); - - if (spi->mode & SPI_CPOL) - reg |= SUN6I_TFR_CTL_CPOL; - else - reg &= ~SUN6I_TFR_CTL_CPOL; - - if (spi->mode & SPI_CPHA) - reg |= SUN6I_TFR_CTL_CPHA; - else - reg &= ~SUN6I_TFR_CTL_CPHA; - - if (spi->mode & SPI_LSB_FIRST) - reg |= SUN6I_TFR_CTL_FBS; - else - reg &= ~SUN6I_TFR_CTL_FBS; - /* * If it's a TX only transfer, we don't want to fill the RX * FIFO with bogus data */ + reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); + if (sspi->rx_buf) { reg &= ~SUN6I_TFR_CTL_DHB; rx_len = tfr->len; @@ -429,11 +448,6 @@ static int sun6i_spi_transfer_one(struct spi_controller *host, sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); } - /* Finally enable the bus - doing so before might raise SCK to HIGH */ - reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG); - reg |= SUN6I_GBL_CTL_BUS_ENABLE; - sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg); - /* Setup the transfer now... */ if (sspi->tx_buf) { tx_len = tfr->len; @@ -668,6 +682,7 @@ static int sun6i_spi_probe(struct platform_device *pdev) host->max_speed_hz = 100 * 1000 * 1000; host->min_speed_hz = 3 * 1000; host->use_gpio_descriptors = true; + host->prepare_message = sun6i_spi_prepare_message; host->set_cs = sun6i_spi_set_cs; host->transfer_one = sun6i_spi_transfer_one; host->num_chipselect = 4;