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H616 uses same offsets as D1. Add allwinner,sun20i-d1-hstimer Add allwinner,sun50i-h616-hstimer with fallback to allwinner,sun20i-d1-hstimer Extend schema condition for interrupts to cover D1 compatible variant. Signed-off-by: Michal Piekos Acked-by: Conor Dooley --- .../devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml index f1853daec2f9..3e2725c56995 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml +++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml @@ -15,9 +15,13 @@ properties: oneOf: - const: allwinner,sun5i-a13-hstimer - const: allwinner,sun7i-a20-hstimer + - const: allwinner,sun20i-d1-hstimer - items: - const: allwinner,sun6i-a31-hstimer - const: allwinner,sun7i-a20-hstimer + - items: + - const: allwinner,sun50i-h616-hstimer + - const: allwinner,sun20i-d1-hstimer reg: maxItems: 1 @@ -45,7 +49,10 @@ required: if: properties: compatible: - const: allwinner,sun5i-a13-hstimer + anyOf: + - const: allwinner,sun5i-a13-hstimer + - contains: + const: allwinner,sun20i-d1-hstimer then: properties: From patchwork Sun Apr 26 10:15:27 2026 Content-Type: text/plain; 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Add sunxi quirks to handle D1 specific offset. Add D1 compatible string to OF match table. Signed-off-by: Michal Piekos --- drivers/clocksource/timer-sun5i.c | 88 ++++++++++++++++++++++++++++++--------- 1 file changed, 69 insertions(+), 19 deletions(-) diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-sun5i.c index f827d3f98f60..2b17904debfa 100644 --- a/drivers/clocksource/timer-sun5i.c +++ b/drivers/clocksource/timer-sun5i.c @@ -18,21 +18,30 @@ #include #include -#define TIMER_IRQ_EN_REG 0x00 +#define TIMER_IRQ_EN_REG 0x00 #define TIMER_IRQ_EN(val) BIT(val) -#define TIMER_IRQ_ST_REG 0x04 -#define TIMER_CTL_REG(val) (0x20 * (val) + 0x10) +#define TIMER_IRQ_ST_REG 0x04 +#define TIMER_CTL_REG(val, offset) (0x20 * (val) + 0x10 + (offset)) #define TIMER_CTL_ENABLE BIT(0) #define TIMER_CTL_RELOAD BIT(1) #define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4) #define TIMER_CTL_ONESHOT BIT(7) -#define TIMER_INTVAL_LO_REG(val) (0x20 * (val) + 0x14) -#define TIMER_INTVAL_HI_REG(val) (0x20 * (val) + 0x18) -#define TIMER_CNTVAL_LO_REG(val) (0x20 * (val) + 0x1c) -#define TIMER_CNTVAL_HI_REG(val) (0x20 * (val) + 0x20) +#define TIMER_INTVAL_LO_REG(val, offset) (0x20 * (val) + 0x14 + (offset)) +#define TIMER_INTVAL_HI_REG(val, offset) (0x20 * (val) + 0x18 + (offset)) +#define TIMER_CNTVAL_LO_REG(val, offset) (0x20 * (val) + 0x1c + (offset)) +#define TIMER_CNTVAL_HI_REG(val, offset) (0x20 * (val) + 0x20 + (offset)) #define TIMER_SYNC_TICKS 3 +/** + * struct sunxi_timer_quirks - Differences between SoC variants. + * + * @from_ctl_base_offset: offset applied from ctl register onwards + */ +struct sunxi_timer_quirks { + u32 from_ctl_base_offset; +}; + struct sun5i_timer { void __iomem *base; struct clk *clk; @@ -40,6 +49,7 @@ struct sun5i_timer { u32 ticks_per_jiffy; struct clocksource clksrc; struct clock_event_device clkevt; + const struct sunxi_timer_quirks *quirks; }; #define nb_to_sun5i_timer(x) \ @@ -57,28 +67,36 @@ struct sun5i_timer { */ static void sun5i_clkevt_sync(struct sun5i_timer *ce) { - u32 old = readl(ce->base + TIMER_CNTVAL_LO_REG(1)); + u32 offset = ce->quirks->from_ctl_base_offset; + u32 old = readl(ce->base + TIMER_CNTVAL_LO_REG(1, offset)); - while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS) + while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1, offset))) < + TIMER_SYNC_TICKS) cpu_relax(); } static void sun5i_clkevt_time_stop(struct sun5i_timer *ce, u8 timer) { - u32 val = readl(ce->base + TIMER_CTL_REG(timer)); - writel(val & ~TIMER_CTL_ENABLE, ce->base + TIMER_CTL_REG(timer)); + u32 offset = ce->quirks->from_ctl_base_offset; + u32 val = readl(ce->base + TIMER_CTL_REG(timer, offset)); + + writel(val & ~TIMER_CTL_ENABLE, + ce->base + TIMER_CTL_REG(timer, offset)); sun5i_clkevt_sync(ce); } static void sun5i_clkevt_time_setup(struct sun5i_timer *ce, u8 timer, u32 delay) { - writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer)); + u32 offset = ce->quirks->from_ctl_base_offset; + + writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer, offset)); } static void sun5i_clkevt_time_start(struct sun5i_timer *ce, u8 timer, bool periodic) { - u32 val = readl(ce->base + TIMER_CTL_REG(timer)); + u32 offset = ce->quirks->from_ctl_base_offset; + u32 val = readl(ce->base + TIMER_CTL_REG(timer, offset)); if (periodic) val &= ~TIMER_CTL_ONESHOT; @@ -86,7 +104,7 @@ static void sun5i_clkevt_time_start(struct sun5i_timer *ce, u8 timer, bool perio val |= TIMER_CTL_ONESHOT; writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, - ce->base + TIMER_CTL_REG(timer)); + ce->base + TIMER_CTL_REG(timer, offset)); } static int sun5i_clkevt_shutdown(struct clock_event_device *clkevt) @@ -141,8 +159,9 @@ static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id) static u64 sun5i_clksrc_read(struct clocksource *clksrc) { struct sun5i_timer *cs = clksrc_to_sun5i_timer(clksrc); + u32 offset = cs->quirks->from_ctl_base_offset; - return ~readl(cs->base + TIMER_CNTVAL_LO_REG(1)); + return ~readl(cs->base + TIMER_CNTVAL_LO_REG(1, offset)); } static int sun5i_rate_cb(struct notifier_block *nb, @@ -173,12 +192,13 @@ static int sun5i_setup_clocksource(struct platform_device *pdev, unsigned long rate) { struct sun5i_timer *cs = platform_get_drvdata(pdev); + u32 offset = cs->quirks->from_ctl_base_offset; void __iomem *base = cs->base; int ret; - writel(~0, base + TIMER_INTVAL_LO_REG(1)); + writel(~0, base + TIMER_INTVAL_LO_REG(1, offset)); writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, - base + TIMER_CTL_REG(1)); + base + TIMER_CTL_REG(1, offset)); cs->clksrc.name = pdev->dev.of_node->name; cs->clksrc.rating = 340; @@ -237,7 +257,9 @@ static int sun5i_setup_clockevent(struct platform_device *pdev, static int sun5i_timer_probe(struct platform_device *pdev) { + const struct sunxi_timer_quirks *quirks; struct device *dev = &pdev->dev; + struct device_node *node = dev_of_node(&pdev->dev); struct sun5i_timer *st; struct reset_control *rstc; void __iomem *timer_base; @@ -251,6 +273,9 @@ static int sun5i_timer_probe(struct platform_device *pdev) platform_set_drvdata(pdev, st); + if (!node) + return -EINVAL; + timer_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(timer_base)) { dev_err(dev, "Can't map registers\n"); @@ -273,11 +298,18 @@ static int sun5i_timer_probe(struct platform_device *pdev) return -EINVAL; } + quirks = of_device_get_match_data(&pdev->dev); + if (!quirks) { + dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); + return -ENODEV; + } + st->base = timer_base; st->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ); st->clk = clk; st->clk_rate_cb.notifier_call = sun5i_rate_cb; st->clk_rate_cb.next = NULL; + st->quirks = quirks; ret = devm_clk_notifier_register(dev, clk, &st->clk_rate_cb); if (ret) { @@ -311,9 +343,27 @@ static void sun5i_timer_remove(struct platform_device *pdev) clocksource_unregister(&st->clksrc); } +static const struct sunxi_timer_quirks sun5i_sun7i_hstimer_quirks = { + .from_ctl_base_offset = 0x0, +}; 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Tested on LCPI-PC-T113/F113: - hstimer is registered as clocksource - switching clocksource at runtime works - after rating increase hstimer operates as a broadcast clockevent device Signed-off-by: Michal Piekos --- arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi index 424f4a2487e2..40e76cfc8a1d 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi @@ -34,6 +34,17 @@ cpu1: cpu@1 { }; }; + soc { + hstimer@3008000 { + compatible = "allwinner,sun20i-d1-hstimer"; + reg = <0x03008000 0x1000>; + interrupts = , + ; + clocks = <&ccu CLK_BUS_HSTIMER>; + resets = <&ccu RST_BUS_HSTIMER>; + }; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x03021000 0x1000>, From patchwork Sun Apr 26 10:15:29 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Piekos X-Patchwork-Id: 2053 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 69D641C0046 for ; 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Received: from user-188-33-36-99.play-internet.pl ([188.33.36.99] helo=localhost) by s106.cyber-folks.pl with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wGwX9-0000000CBRV-3ut5; Sun, 26 Apr 2026 12:16:16 +0200 From: Michal Piekos Date: Sun, 26 Apr 2026 12:15:29 +0200 Subject: [PATCH v2 4/4] arm64: dts: allwinner: h616: add hstimer node Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260426-h616-t113s-hstimer-v2-4-e65e9dc0c9da@mmpsystems.pl> References: <20260426-h616-t113s-hstimer-v2-0-e65e9dc0c9da@mmpsystems.pl> In-Reply-To: <20260426-h616-t113s-hstimer-v2-0-e65e9dc0c9da@mmpsystems.pl> To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Michal Piekos X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1777198529; l=1212; i=michal.piekos@mmpsystems.pl; s=20260301; h=from:subject:message-id; bh=cCHCvUuPpHPu5/1mgf/ezZ1u0bRGr6TqCo7i9RhbRKk=; b=0x0K5umTBuHAYa/VBYZvkuflhbBQIa1oByPmLb0zonwXUViZBNgJ3TSBKIRGDk/8Payuva2uG zx9x83mwLcMC2kPHFZJEXGuASvsTKqT0CnfES+2VefcrYFfTnsswHp4 X-Developer-Key: i=michal.piekos@mmpsystems.pl; a=ed25519; pk=Aixyx03If7ZDamiKKN0lsa+0mtA+WjIuIf2ZQVYNBqg= X-Authenticated-Id: michal.piekos@mmpsystems.pl X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Describe high speed timer block on Allwinner H616. Tested on Orange Pi Zero 3: - hstimer is registered as clocksource - switching clocksource at runtime works - after rating increase hstimer operates as a broadcast clockevent device Signed-off-by: Michal Piekos --- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index bf054869e78b..1356e5df2562 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -237,6 +237,16 @@ timer0: timer@3009000 { clocks = <&osc24M>; }; + hstimer@3005000 { + compatible = "allwinner,sun50i-h616-hstimer", + "allwinner,sun20i-d1-hstimer"; + reg = <0x03005000 0x1000>; + interrupts = , + ; + clocks = <&ccu CLK_BUS_HSTIMER>; + resets = <&ccu RST_BUS_HSTIMER>; + }; + watchdog: watchdog@30090a0 { compatible = "allwinner,sun50i-h616-wdt", "allwinner,sun6i-a31-wdt";