From patchwork Mon May 11 21:37:09 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 2221 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 5BF7C1C053C for ; Mon, 11 May 2026 23:38:30 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=arm.com; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-23267-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; envelope-from=linux-sunxi+bounces-23267-noreply=patchwork.local@lists.linux.dev; helo=sea.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sea.lore.kernel.org (Postfix) with ESMTP id C1E653018AE1 for ; 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Mon, 11 May 2026 14:37:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778535480; bh=huUaM+2jNsjuuFYu0LdBhE+OYXFSoWbfHGjyw/gu+ds=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NR+2Ect3BUvXRiWfJnijXhF8l4S93R9eVFTaysfpJ8bOL28BCdSrJjM4NJzg/KNRr K7QBOOttZPC3RSTeCZskvI4142l3d+yiIlEnqv2dN0RM/dqzX2oL3bTQTRPN75E0Xo nvBbcMR0HP9W9hpfoUMfYXV/Dq/ht+CkGY+EH+l8= From: Andre Przywara To: u-boot@lists.denx.de Cc: Tom Rini , Jernej Skrabec , Chen-Yu Tsai , Paul Kocialkowski , linux-sunxi@lists.linux.dev Subject: [PATCH 1/5] spi: sunxi: add support for A523 SPI controller Date: Mon, 11 May 2026 23:37:09 +0200 Message-ID: <20260511213713.15943-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.4 In-Reply-To: <20260511213713.15943-1-andre.przywara@arm.com> References: <20260511213713.15943-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-0.66 / 15.00]; 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TAGGED_FROM(0.00)[bounces-23267-noreply=patchwork.local]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 5BF7C1C053C X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The SPI controllers in the Allwinner A523/A527/T527 SoCs is very close to the one used in the R329 and D1 generation, definitely as far as our driver is concerned. Add the new compatible string, but use the existing config section from the previous SoC generation. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec --- drivers/spi/spi-sunxi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c index 08b603f04a2..4e91cf6b7fd 100644 --- a/drivers/spi/spi-sunxi.c +++ b/drivers/spi/spi-sunxi.c @@ -587,6 +587,10 @@ static const struct udevice_id sun4i_spi_ids[] = { .compatible = "allwinner,sun50i-r329-spi", .data = (ulong)&sun50i_r329_spi_variant, }, + { + .compatible = "allwinner,sun55i-a523-spi", + .data = (ulong)&sun50i_r329_spi_variant, + }, { /* sentinel */ } }; From patchwork Mon May 11 21:37:10 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 2219 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sto.lore.kernel.org (sto.lore.kernel.org [172.232.135.74]) by mxe881.netcup.net (Postfix) with ESMTPS id 9A3F21C053C for ; Mon, 11 May 2026 23:38:08 +0200 (CEST) Authentication-Results: mxe881; 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arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 78FE22C34; Mon, 11 May 2026 14:37:57 -0700 (PDT) Received: from ryzen.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3F2093F85F; Mon, 11 May 2026 14:38:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778535482; bh=lA6JiRAdI1XNNDYB3a5liEgF5w+Ea9wm3rCG6xAJBk8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B7G5r0ZM21q1CUN2G2/a7f7aDhxA8gZ/tU3F/ZJLJ2yYcqcxccM6779CRUpJBj7Bv E72pCk1L7cn1JK6WHlukPWMc/vVoWro/XWMnwfmNFyMu3l+EpV3CyG3AtalD2nHhW2 zSW7extABQw0gMkICIHPiELGvvaBNsaMZiqmqxnk= From: Andre Przywara To: u-boot@lists.denx.de Cc: Tom Rini , Jernej Skrabec , Chen-Yu Tsai , Paul Kocialkowski , linux-sunxi@lists.linux.dev Subject: [PATCH 2/5] sunxi: spl: spi: Clean up SPI0 pinmux setting Date: Mon, 11 May 2026 23:37:10 +0200 Message-ID: <20260511213713.15943-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.4 In-Reply-To: <20260511213713.15943-1-andre.przywara@arm.com> References: <20260511213713.15943-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-0.66 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.232.135.74:from]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; MAILLIST(-0.15)[generic]; MIME_GOOD(-0.10)[text/plain]; BAD_REP_POLICIES(0.10)[]; HAS_LIST_UNSUB(-0.01)[]; PRECEDENCE_BULK(0.00)[]; TAGGED_RCPT(0.00)[]; FUZZY_BLOCKED(0.00)[rspamd.com]; FREEMAIL_CC(0.00)[konsulko.com,gmail.com,kernel.org,paulk.fr,lists.linux.dev]; DBL_BLOCKED_OPENRESOLVER(0.00)[sto.lore.kernel.org:rdns,sto.lore.kernel.org:helo,arm.com:email,arm.com:dkim]; FROM_HAS_DN(0.00)[]; R_DKIM_ALLOW(0.00)[arm.com:s=foss]; RCVD_COUNT_FIVE(0.00)[6]; FROM_NEQ_ENVFROM(0.00)[andre.przywara@arm.com,linux-sunxi@lists.linux.dev]; DKIM_TRACE(0.00)[arm.com:+]; DMARC_POLICY_ALLOW(0.00)[arm.com,none]; RCPT_COUNT_FIVE(0.00)[6]; TO_DN_SOME(0.00)[]; R_SPF_ALLOW(0.00)[+ip4:172.232.135.74]; FORGED_SENDER_MAILLIST(0.00)[]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; RCVD_TLS_LAST(0.00)[]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; MIME_TRACE(0.00)[0:+]; TAGGED_FROM(0.00)[bounces-23268-noreply=patchwork.local]; ASN(0.00)[asn:63949, ipnet:172.232.128.0/19, country:SG]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 9A3F21C053C X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The function to set the pinmux for the Port C SPI0 pins was looking more like a logic puzzle from a magazine than something that readers could understand and extend. Replace the convoluted pinmux setup, grouped by pin, with a simple array of the four pins involved, and just initialise this array at build time, based on the selected SoC. This makes it easy to see which pins are needed, and even easier to extend. Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/spl_spi_sunxi.c | 43 ++++++++++++----------------- 1 file changed, 18 insertions(+), 25 deletions(-) diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 5f72e809952..905a7db2a77 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -105,35 +105,28 @@ /* * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting - * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3. - * The H6 uses PC0, PC2, PC3, PC5, the H616 PC0, PC2, PC3, PC4. + * from SPI Flash, later SoCs are using pins PC0,PC1,PC2,PC3. + * Newer SoCs are all over the place. */ static void spi0_pinmux_setup(unsigned int pin_function) { - /* All chips use PC2. And all chips use PC0, except R528/T113 */ - if (!IS_ENABLED(CONFIG_MACH_SUN8I_R528)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); - - sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function); + const u16 spi0_pc_pins[4] = { +#if IS_ENABLED(CONFIG_MACH_SUN8I_R528) + SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4), SUNXI_GPC(5) +#elif IS_ENABLED(CONFIG_MACH_SUN50I_H616) + SUNXI_GPC(0), SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4) +#elif IS_ENABLED(CONFIG_MACH_SUN50I_H6) + SUNXI_GPC(0), SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(5) +#elif IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN5I) || \ + IS_ENABLED(CONFIG_MACH_SUN7I) || IS_ENABLED(CONFIG_MACH_SUN8I_R40) + SUNXI_GPC(0), SUNXI_GPC(1), SUNXI_GPC(2), SUNXI_GPC(23) +#else + SUNXI_GPC(0), SUNXI_GPC(1), SUNXI_GPC(2), SUNXI_GPC(3) +#endif + }; - /* All chips except H6/H616/R528/T113 use PC1. */ - if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) && - !IS_ENABLED(CONFIG_MACH_SUN8I_R528)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function); - - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6) || - IS_ENABLED(CONFIG_MACH_SUN8I_R528)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function); - if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) || - IS_ENABLED(CONFIG_MACH_SUN8I_R528)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(4), pin_function); - - /* Older generations use PC23 for CS, newer ones use PC3. */ - if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) || - IS_ENABLED(CONFIG_MACH_SUN8I_R40)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function); - else - sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function); + for (int i = 0; i < 4; i++) + sunxi_gpio_set_cfgpin(spi0_pc_pins[i], pin_function); } static bool is_sun6i_gen_spi(void) From patchwork Mon May 11 21:37:11 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 2222 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id F3BC41C06A8 for ; Mon, 11 May 2026 23:38:30 +0200 (CEST) Authentication-Results: mxe881; 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arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 62A462C3A; Mon, 11 May 2026 14:37:59 -0700 (PDT) Received: from ryzen.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 283E63F85F; Mon, 11 May 2026 14:38:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778535484; bh=ZuebneHLwwjWV2c6b/QFWASPVQ443WhMKbY6rAlQSdk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZvNfaJBIhWMFOXsxc3e1P7BZIFzF/wlocnorJc+Abb1AfDNQ61ie1oTXBgnJemX/L FYlcczzh5WqVKXbuoNoULpnTcWGQLKWl+2IUUFymm8GplWIgO//YCbXvcjlWvufQji 7syzQ2ATwARrbfSsg6OA/mWEzcbdKA4k4hxm37CM= From: Andre Przywara To: u-boot@lists.denx.de Cc: Tom Rini , Jernej Skrabec , Chen-Yu Tsai , Paul Kocialkowski , linux-sunxi@lists.linux.dev Subject: [PATCH 3/5] sunxi: spl: spi: Add support for Allwinner A523 Date: Mon, 11 May 2026 23:37:11 +0200 Message-ID: <20260511213713.15943-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.4 In-Reply-To: <20260511213713.15943-1-andre.przywara@arm.com> References: <20260511213713.15943-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-0.66 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.234.253.10:from]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; MAILLIST(-0.15)[generic]; MIME_GOOD(-0.10)[text/plain]; BAD_REP_POLICIES(0.10)[]; HAS_LIST_UNSUB(-0.01)[]; PRECEDENCE_BULK(0.00)[]; TAGGED_RCPT(0.00)[]; FUZZY_BLOCKED(0.00)[rspamd.com]; FREEMAIL_CC(0.00)[konsulko.com,gmail.com,kernel.org,paulk.fr,lists.linux.dev]; DBL_BLOCKED_OPENRESOLVER(0.00)[arm.com:email,arm.com:dkim,sea.lore.kernel.org:rdns,sea.lore.kernel.org:helo]; FROM_HAS_DN(0.00)[]; RCVD_COUNT_FIVE(0.00)[6]; R_DKIM_ALLOW(0.00)[arm.com:s=foss]; FROM_NEQ_ENVFROM(0.00)[andre.przywara@arm.com,linux-sunxi@lists.linux.dev]; DKIM_TRACE(0.00)[arm.com:+]; DMARC_POLICY_ALLOW(0.00)[arm.com,none]; RCPT_COUNT_FIVE(0.00)[6]; TO_DN_SOME(0.00)[]; R_SPF_ALLOW(0.00)[+ip4:172.234.253.10:c]; FORGED_SENDER_MAILLIST(0.00)[]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; RCVD_TLS_LAST(0.00)[]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; MIME_TRACE(0.00)[0:+]; TAGGED_FROM(0.00)[bounces-23269-noreply=patchwork.local]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: F3BC41C06A8 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The SPI IP in the Allwinner A523 is mostly compatible to the later generation used in other Allwinner SoCs, at least as far as the SPL driver is concerned. Just add the pinmux configuration for SPI0 on PortC, as used by the BROM. This enables SPI (NOR) boot on A523/A527/T527 boards. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- arch/arm/mach-sunxi/spl_spi_sunxi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 905a7db2a77..25878026891 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -113,6 +113,8 @@ static void spi0_pinmux_setup(unsigned int pin_function) const u16 spi0_pc_pins[4] = { #if IS_ENABLED(CONFIG_MACH_SUN8I_R528) SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4), SUNXI_GPC(5) +#elif IS_ENABLED(CONFIG_MACH_SUN55I_A523) + SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4), SUNXI_GPC(12) #elif IS_ENABLED(CONFIG_MACH_SUN50I_H616) SUNXI_GPC(0), SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4) #elif IS_ENABLED(CONFIG_MACH_SUN50I_H6) @@ -250,7 +252,8 @@ static void spi0_init(void) unsigned int pin_function = SUNXI_GPC_SPI0; if (IS_ENABLED(CONFIG_MACH_SUN50I) || - IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + IS_ENABLED(CONFIG_SUN50I_GEN_H6) || + IS_ENABLED(CONFIG_MACH_SUN55I_A523)) pin_function = SUN50I_GPC_SPI0; else if (IS_ENABLED(CONFIG_MACH_SUNIV) || IS_ENABLED(CONFIG_MACH_SUN8I_R528)) From patchwork Mon May 11 21:37:12 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 2223 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 8414B1C053C for ; Mon, 11 May 2026 23:38:31 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=arm.com; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-23270-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; envelope-from=linux-sunxi+bounces-23270-noreply=patchwork.local@lists.linux.dev; helo=sea.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sea.lore.kernel.org (Postfix) with ESMTP id E54123018BC9 for ; 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Mon, 11 May 2026 14:38:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778535486; bh=zKVZ1Uq5tRG9JVDHJ0m8JodzcEX9GicGfsuneK0h/tY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i+fqgG3ZuUAnpgRJZBJefTlBSOKOda8Q6y2/0/yWuwEAKupgTqO/QxLgXoBGBtJVn iPUnucU9jJHfCclspnAbjRaXdIiXL1ZE8OlS0WO9StR7IikRRA05l/d4/aXVZA6krG BL1WWbaokkRMkGJ8Sz7OgBQUrp7K6f+OoMU5Zm6U= From: Andre Przywara To: u-boot@lists.denx.de Cc: Tom Rini , Jernej Skrabec , Chen-Yu Tsai , Paul Kocialkowski , linux-sunxi@lists.linux.dev Subject: [PATCH 4/5] sunxi: configs: Radxa Cubie A5E: enable SPI Date: Mon, 11 May 2026 23:37:12 +0200 Message-ID: <20260511213713.15943-5-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.4 In-Reply-To: <20260511213713.15943-1-andre.przywara@arm.com> References: <20260511213713.15943-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-0.66 / 15.00]; BAYES_HAM(-5.50)[99.99%]; RBL_SENDERSCORE(2.00)[172.234.253.10:from]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; MAILLIST(-0.15)[generic]; MIME_GOOD(-0.10)[text/plain]; BAD_REP_POLICIES(0.10)[]; HAS_LIST_UNSUB(-0.01)[]; PRECEDENCE_BULK(0.00)[]; TAGGED_RCPT(0.00)[]; FUZZY_BLOCKED(0.00)[rspamd.com]; FREEMAIL_CC(0.00)[konsulko.com,gmail.com,kernel.org,paulk.fr,lists.linux.dev]; DBL_BLOCKED_OPENRESOLVER(0.00)[sea.lore.kernel.org:rdns,sea.lore.kernel.org:helo,arm.com:email,arm.com:dkim]; FROM_HAS_DN(0.00)[]; RCVD_COUNT_FIVE(0.00)[6]; R_DKIM_ALLOW(0.00)[arm.com:s=foss]; FROM_NEQ_ENVFROM(0.00)[andre.przywara@arm.com,linux-sunxi@lists.linux.dev]; DKIM_TRACE(0.00)[arm.com:+]; DMARC_POLICY_ALLOW(0.00)[arm.com,none]; RCPT_COUNT_FIVE(0.00)[6]; TO_DN_SOME(0.00)[]; R_SPF_ALLOW(0.00)[+ip4:172.234.253.10:c]; FORGED_SENDER_MAILLIST(0.00)[]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; RCVD_TLS_LAST(0.00)[]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; MIME_TRACE(0.00)[0:+]; TAGGED_FROM(0.00)[bounces-23270-noreply=patchwork.local]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 8414B1C053C X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The Radxa Cubie A5E ships with SPI NOR flash, so enable the SPI and flash drivers, also the SPL version, for SPI booting. Sync the defconfig file with the version from savedefconfig on the way. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec --- configs/radxa-cubie-a5e_defconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/configs/radxa-cubie-a5e_defconfig b/configs/radxa-cubie-a5e_defconfig index 84bc4e3d4a9..2a66d0e0866 100644 --- a/configs/radxa-cubie-a5e_defconfig +++ b/configs/radxa-cubie-a5e_defconfig @@ -15,6 +15,7 @@ CONFIG_DRAM_SUNXI_TPR12=0x3533302f CONFIG_MACH_SUN55I_A523=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_R_I2C_ENABLE=y +CONFIG_SPL_SPI_SUNXI=y CONFIG_SPL_SUNXI_LED_STATUS=y CONFIG_SPL_SUNXI_LED_STATUS_GPIO=356 # CONFIG_SPL_SUNXI_LED_STATUS_ACTIVE_HIGH is not set @@ -25,11 +26,14 @@ CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_PHY_REALTEK=y +CONFIG_MTD=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y +CONFIG_PHY_REALTEK=y CONFIG_REGULATOR_AXP=y CONFIG_AXP717_POWER=y CONFIG_AXP_DCDC2_VOLT=920 CONFIG_AXP_DCDC3_VOLT=1100 +CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y From patchwork Mon May 11 21:37:13 2026 Content-Type: text/plain; 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smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=LvWo6Ep2; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 33AE22C3E; Mon, 11 May 2026 14:38:03 -0700 (PDT) Received: from ryzen.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EEE153F85F; Mon, 11 May 2026 14:38:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778535488; bh=At/1nIifhhzvbnxRMbf6B3uI+EgQ52jNjzfb7fwRWrE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LvWo6Ep28QfP0sQLzL5K4eArgpGqU5zfaL56X5GnKWTWEf/SWpDYAkyuyOrQf8Mlc 8aUYVNOPbxRgq8UVU+hbbPC8yZROcIudKkwCO1eNGz2Ak8mCBvOlE3hOxZZlDPl0jM VtbcYbeLjFCROW7JJwLtTT5gPS3AmIhB/ZtfvfoY= From: Andre Przywara To: u-boot@lists.denx.de Cc: Tom Rini , Jernej Skrabec , Chen-Yu Tsai , Paul Kocialkowski , linux-sunxi@lists.linux.dev Subject: [PATCH 5/5] sunxi: configs: OrangePi 4A: enable SPI Date: Mon, 11 May 2026 23:37:13 +0200 Message-ID: <20260511213713.15943-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.4 In-Reply-To: <20260511213713.15943-1-andre.przywara@arm.com> References: <20260511213713.15943-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-0.66 / 15.00]; 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TAGGED_FROM(0.00)[bounces-23271-noreply=patchwork.local]; ASN(0.00)[asn:63949, ipnet:172.232.128.0/19, country:SG]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: F3E5E1C053C X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The OrangePi 4A board ships with SPI NOR flash, so enable the SPI and flash drivers, also the SPL version, for SPI booting. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec --- configs/orangepi_4a_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/orangepi_4a_defconfig b/configs/orangepi_4a_defconfig index 6a44dd97959..2d36757ba11 100644 --- a/configs/orangepi_4a_defconfig +++ b/configs/orangepi_4a_defconfig @@ -16,6 +16,7 @@ CONFIG_DRAM_SUNXI_TPR12=0x3a373233 CONFIG_MACH_SUN55I_A523=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_R_I2C_ENABLE=y +CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y @@ -23,10 +24,13 @@ CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MTD=y +CONFIG_SPI_FLASH_XMC=y CONFIG_REGULATOR_AXP=y CONFIG_AXP717_POWER=y CONFIG_AXP_I2C_ADDRESS=0x35 CONFIG_AXP_DCDC2_VOLT=920 CONFIG_AXP_DCDC3_VOLT=1160 +CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y