From patchwork Fri May 15 23:45:57 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 2257 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114]) by mxe881.netcup.net (Postfix) with ESMTPS id 8DC3C1C0759 for ; Sat, 16 May 2026 01:47:05 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=arm.com; spf=pass (sender IP is 172.105.105.114) smtp.mailfrom=linux-sunxi+bounces-23380-noreply=patchwork.local@lists.linux.dev smtp.helo=tor.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.105.105.114 as permitted sender) client-ip=172.105.105.114; envelope-from=linux-sunxi+bounces-23380-noreply=patchwork.local@lists.linux.dev; helo=tor.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by tor.lore.kernel.org (Postfix) with ESMTP id 002D7300F798 for ; Fri, 15 May 2026 23:46:50 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C39F12ED848; Fri, 15 May 2026 23:46:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="F8y0dypX" X-Original-To: linux-sunxi@lists.linux.dev Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 26C29405C5B for ; Fri, 15 May 2026 23:46:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778888809; cv=none; b=KmXAXv8zB63v79MhsrkG99sliQqxGvSCM3lgPuBC2fgLdgcYJVZ1N9XBA81S0CqAaHjPyCbKhQsNCov/V9OG4w5QdVBpPZmvGmQAj0n7/yRSz03wx6RSQvd0iEr/7nuYRGirZD3R6UnEKfTuQojQkyXdhFlrrU/tWkG36UCFFEk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778888809; c=relaxed/simple; bh=vGaY96z3+CdzTHUsRA640EFQXAQoGZMYdPR5gqmMj74=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lzF0HRntxCyT7ix44BouQN64muMqGpS/SVqqZnCuA2nIihXhysRv71pQgp31KWQAJcvv+khV6iCfpvkCa+34XKALVc3oAhKxR/0xs985NwBaofSLUDHum0AJYBlCm6bn6p9F74mR8fp2cYibMruOiYCT9CJNrI5CdbrZqZRFGbk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=F8y0dypX; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4BF3C35ED; Fri, 15 May 2026 16:46:42 -0700 (PDT) Received: from ryzen.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3FE0B3F85F; Fri, 15 May 2026 16:46:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778888807; bh=vGaY96z3+CdzTHUsRA640EFQXAQoGZMYdPR5gqmMj74=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F8y0dypXACVOsN1hwrekfmA51RYuoQlmdkj0KfQZczvVH9TMzSKKcbPJ7Qtr97aBA XJfEEB/8KUU9Q4tkiKERnJP/y72nwlgy68HeT6yRBo/agrCSlTa15qyf4DibTpxtRm B27tOviU4gF1j5+6B8MPXWxVn6pdIyYva0+rFM50= From: Andre Przywara To: u-boot@lists.denx.de Cc: Tom Rini , Jernej Skrabec , Chen-Yu Tsai , Paul Kocialkowski , linux-sunxi@lists.linux.dev Subject: [PATCH v2 1/5] spi: sunxi: add support for A523 SPI controller Date: Sat, 16 May 2026 01:45:57 +0200 Message-ID: <20260515234601.15431-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.4 In-Reply-To: <20260515234601.15431-1-andre.przywara@arm.com> References: <20260515234601.15431-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The SPI controllers in the Allwinner A523/A527/T527 SoCs is very close to the one used in the R329 and D1 generation, definitely as far as our driver is concerned. Add the new compatible string, but use the existing config section from the previous SoC generation. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec --- drivers/spi/spi-sunxi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c index 08b603f04a2..4e91cf6b7fd 100644 --- a/drivers/spi/spi-sunxi.c +++ b/drivers/spi/spi-sunxi.c @@ -587,6 +587,10 @@ static const struct udevice_id sun4i_spi_ids[] = { .compatible = "allwinner,sun50i-r329-spi", .data = (ulong)&sun50i_r329_spi_variant, }, + { + .compatible = "allwinner,sun55i-a523-spi", + .data = (ulong)&sun50i_r329_spi_variant, + }, { /* sentinel */ } }; From patchwork Fri May 15 23:45:58 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 2258 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114]) by mxe881.netcup.net (Postfix) with ESMTPS id D4E5E1C0759 for ; Sat, 16 May 2026 01:47:06 +0200 (CEST) Authentication-Results: mxe881; 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Fri, 15 May 2026 23:46:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778888811; cv=none; b=PJXdcqomOobKv2CqBSyXYAwDaRzIGCwEe9B8/au0MPtqHEs9KEme6X5MH6sPtdkSOWSkpc1wo18G2l/IQlbcwy9ZYydH3qRiM1wlKme5UPU6tDa2maS46pfM7XK0F70kckHzrcIJ9Epe8PZk76snnpVuGBx2kw0p+O/sjmShOFM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778888811; c=relaxed/simple; bh=BViCz6WCvGbkaASTXNqFznvXjvanjPWZ7kIExj80CCI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nsiNmPMMlAomTJgpdc9+k5I4DpwBQGa3S2pUMhCUhblc7vJFyIPGadc/JZ513yNQDb3dBCoOysS3lLMXs0lwnL9Yt8aox4VLE5p4BYADHoHlKahwWlJpfMODFQUZzE5rv3UJkR7dLqpr2ijjYYjbXiMN+uFH7Gg/eh+QoKb4JKo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=HnD/uNDU; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E528735EF; Fri, 15 May 2026 16:46:43 -0700 (PDT) Received: from ryzen.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D8C6C3F85F; Fri, 15 May 2026 16:46:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778888809; bh=BViCz6WCvGbkaASTXNqFznvXjvanjPWZ7kIExj80CCI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HnD/uNDUwgTg3NFv0fNTIOUd7u05AUq9yKg3D674L5qpJW3wfr058gI30zGkqTFpG CfsfMWKac7eKRZj8+3ajOajXzj8ME4o9zq+HwdgdamyE0BRPBKnwh/UJ9WhULlfThZ CC7OBbmpAzl6+vdK+e4CTuXHetrjLeuDqr7Bitew= From: Andre Przywara To: u-boot@lists.denx.de Cc: Tom Rini , Jernej Skrabec , Chen-Yu Tsai , Paul Kocialkowski , linux-sunxi@lists.linux.dev Subject: [PATCH v2 2/5] sunxi: spl: spi: Clean up SPI0 pinmux setting Date: Sat, 16 May 2026 01:45:58 +0200 Message-ID: <20260515234601.15431-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.4 In-Reply-To: <20260515234601.15431-1-andre.przywara@arm.com> References: <20260515234601.15431-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The function to set the pinmux for the Port C SPI0 pins was looking more like a logic puzzle from a magazine than something that readers could understand and extend. Replace the convoluted pinmux setup, grouped by pin, with a simple array of the four pins involved, and just initialise this array at build time, based on the selected SoC. This makes it easy to see which pins are needed, and even easier to extend. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- arch/arm/mach-sunxi/spl_spi_sunxi.c | 43 ++++++++++++----------------- 1 file changed, 18 insertions(+), 25 deletions(-) diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 5f72e809952..5cdf155d76a 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -105,35 +105,28 @@ /* * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting - * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3. - * The H6 uses PC0, PC2, PC3, PC5, the H616 PC0, PC2, PC3, PC4. + * from SPI Flash, later SoCs are using pins PC0,PC1,PC2,PC3. + * Newer SoCs are all over the place. */ static void spi0_pinmux_setup(unsigned int pin_function) { - /* All chips use PC2. And all chips use PC0, except R528/T113 */ - if (!IS_ENABLED(CONFIG_MACH_SUN8I_R528)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); - - sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function); + const u16 spi0_pc_pins[4] = { +#if IS_ENABLED(CONFIG_MACH_SUN8I_R528) + SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4), SUNXI_GPC(5) +#elif IS_ENABLED(CONFIG_MACH_SUN50I_H616) + SUNXI_GPC(0), SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4) +#elif IS_ENABLED(CONFIG_MACH_SUN50I_H6) + SUNXI_GPC(0), SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(5) +#elif IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) || \ + IS_ENABLED(CONFIG_MACH_SUN8I_R40) + SUNXI_GPC(0), SUNXI_GPC(1), SUNXI_GPC(2), SUNXI_GPC(23) +#else + SUNXI_GPC(0), SUNXI_GPC(1), SUNXI_GPC(2), SUNXI_GPC(3) +#endif + }; - /* All chips except H6/H616/R528/T113 use PC1. */ - if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) && - !IS_ENABLED(CONFIG_MACH_SUN8I_R528)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function); - - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6) || - IS_ENABLED(CONFIG_MACH_SUN8I_R528)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function); - if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) || - IS_ENABLED(CONFIG_MACH_SUN8I_R528)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(4), pin_function); - - /* Older generations use PC23 for CS, newer ones use PC3. */ - if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) || - IS_ENABLED(CONFIG_MACH_SUN8I_R40)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function); - else - sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function); + for (int i = 0; i < 4; i++) + sunxi_gpio_set_cfgpin(spi0_pc_pins[i], pin_function); } static bool is_sun6i_gen_spi(void) From patchwork Fri May 15 23:45:59 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 2255 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sto.lore.kernel.org (sto.lore.kernel.org [172.232.135.74]) by mxe881.netcup.net (Postfix) with ESMTPS id 069541C0759 for ; Sat, 16 May 2026 01:47:03 +0200 (CEST) Authentication-Results: mxe881; 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arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8D6E535EA; Fri, 15 May 2026 16:46:45 -0700 (PDT) Received: from ryzen.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7BBF43F85F; Fri, 15 May 2026 16:46:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778888810; bh=/NquZCMpDtl2WHUGjub+KUXRUFIT5Xv4Qr8cMNgBzUw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qjjC6OCCG+OKETa9Pgfa+gsDR9+gKhH3c5/raYpCfYuxQNQzfpe8z7nFaXWoLi6Wj 49/IqbxXfHNnh4s/auRF58qbpL6WU68NSWerv7WxDN1yOYWeu7f75iTDUbTaSe8JtQ jU2tCMhw47fKsc01O+5H745lH5UALuuMXDyqabgw= From: Andre Przywara To: u-boot@lists.denx.de Cc: Tom Rini , Jernej Skrabec , Chen-Yu Tsai , Paul Kocialkowski , linux-sunxi@lists.linux.dev Subject: [PATCH v2 3/5] sunxi: spl: spi: Add support for Allwinner A523 Date: Sat, 16 May 2026 01:45:59 +0200 Message-ID: <20260515234601.15431-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.4 In-Reply-To: <20260515234601.15431-1-andre.przywara@arm.com> References: <20260515234601.15431-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-0.66 / 15.00]; BAYES_HAM(-5.50)[99.99%]; RBL_SENDERSCORE(2.00)[172.232.135.74:from]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; MAILLIST(-0.15)[generic]; MIME_GOOD(-0.10)[text/plain]; BAD_REP_POLICIES(0.10)[]; HAS_LIST_UNSUB(-0.01)[]; PRECEDENCE_BULK(0.00)[]; TAGGED_RCPT(0.00)[]; FUZZY_BLOCKED(0.00)[rspamd.com]; FREEMAIL_CC(0.00)[konsulko.com,gmail.com,kernel.org,paulk.fr,lists.linux.dev]; DBL_BLOCKED_OPENRESOLVER(0.00)[sto.lore.kernel.org:rdns,sto.lore.kernel.org:helo,arm.com:email,arm.com:dkim]; FROM_HAS_DN(0.00)[]; R_DKIM_ALLOW(0.00)[arm.com:s=foss]; RCVD_COUNT_FIVE(0.00)[6]; FROM_NEQ_ENVFROM(0.00)[andre.przywara@arm.com,linux-sunxi@lists.linux.dev]; DKIM_TRACE(0.00)[arm.com:+]; DMARC_POLICY_ALLOW(0.00)[arm.com,none]; RCPT_COUNT_FIVE(0.00)[6]; TO_DN_SOME(0.00)[]; R_SPF_ALLOW(0.00)[+ip4:172.232.135.74]; FORGED_SENDER_MAILLIST(0.00)[]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; RCVD_TLS_LAST(0.00)[]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; MIME_TRACE(0.00)[0:+]; TAGGED_FROM(0.00)[bounces-23382-noreply=patchwork.local]; ASN(0.00)[asn:63949, ipnet:172.232.128.0/19, country:SG]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 069541C0759 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The SPI IP in the Allwinner A523 is mostly compatible to the later generation used in other Allwinner SoCs, at least as far as the SPL driver is concerned. Just add the pinmux configuration for SPI0 on PortC, as used by the BROM. This enables SPI (NOR) boot on A523/A527/T527 boards. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- arch/arm/mach-sunxi/spl_spi_sunxi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 5cdf155d76a..6c9937128b9 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -113,6 +113,8 @@ static void spi0_pinmux_setup(unsigned int pin_function) const u16 spi0_pc_pins[4] = { #if IS_ENABLED(CONFIG_MACH_SUN8I_R528) SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4), SUNXI_GPC(5) +#elif IS_ENABLED(CONFIG_MACH_SUN55I_A523) + SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4), SUNXI_GPC(12) #elif IS_ENABLED(CONFIG_MACH_SUN50I_H616) SUNXI_GPC(0), SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4) #elif IS_ENABLED(CONFIG_MACH_SUN50I_H6) @@ -250,7 +252,8 @@ static void spi0_init(void) unsigned int pin_function = SUNXI_GPC_SPI0; if (IS_ENABLED(CONFIG_MACH_SUN50I) || - IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + IS_ENABLED(CONFIG_SUN50I_GEN_H6) || + IS_ENABLED(CONFIG_MACH_SUN55I_A523)) pin_function = SUN50I_GPC_SPI0; else if (IS_ENABLED(CONFIG_MACH_SUNIV) || IS_ENABLED(CONFIG_MACH_SUN8I_R528)) From patchwork Fri May 15 23:46:00 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 2256 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sto.lore.kernel.org (sto.lore.kernel.org [172.232.135.74]) by mxe881.netcup.net (Postfix) with ESMTPS id 262961C0759 for ; Sat, 16 May 2026 01:47:04 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=arm.com; spf=pass (sender IP is 172.232.135.74) smtp.mailfrom=linux-sunxi+bounces-23383-noreply=patchwork.local@lists.linux.dev smtp.helo=sto.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.232.135.74 as permitted sender) client-ip=172.232.135.74; envelope-from=linux-sunxi+bounces-23383-noreply=patchwork.local@lists.linux.dev; helo=sto.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sto.lore.kernel.org (Postfix) with ESMTP id 0204E3006B43 for ; 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Fri, 15 May 2026 16:46:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778888812; bh=L7I0yEnYamMLFcfbXu88XCxYp9zDs5qhnpfq4ykAZwM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Iuba++lm5jB5/N7ZOV3Q4ANuKne5ZevKBDmN/nPGd8FX7cg7seqtLwUdLlPljL6wu Ss0JMM2D5d9IlDBroVGlNIKqtD/5Vtbe8i7q1lqcL2pHV/umSEcDV/h/4IJQIKoAW5 dql57RP8gFqwwvIKFMD92Qv4SqYstLG1hfi6ODAo= From: Andre Przywara To: u-boot@lists.denx.de Cc: Tom Rini , Jernej Skrabec , Chen-Yu Tsai , Paul Kocialkowski , linux-sunxi@lists.linux.dev Subject: [PATCH v2 4/5] sunxi: configs: Radxa Cubie A5E: enable SPI Date: Sat, 16 May 2026 01:46:00 +0200 Message-ID: <20260515234601.15431-5-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.4 In-Reply-To: <20260515234601.15431-1-andre.przywara@arm.com> References: <20260515234601.15431-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-0.66 / 15.00]; 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TAGGED_FROM(0.00)[bounces-23383-noreply=patchwork.local]; ASN(0.00)[asn:63949, ipnet:172.232.128.0/19, country:SG]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 262961C0759 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The Radxa Cubie A5E ships with SPI NOR flash, so enable the SPI and flash drivers, also the SPL version, for SPI booting. Sync the defconfig file with the version from savedefconfig on the way. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec --- configs/radxa-cubie-a5e_defconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/configs/radxa-cubie-a5e_defconfig b/configs/radxa-cubie-a5e_defconfig index 84bc4e3d4a9..2a66d0e0866 100644 --- a/configs/radxa-cubie-a5e_defconfig +++ b/configs/radxa-cubie-a5e_defconfig @@ -15,6 +15,7 @@ CONFIG_DRAM_SUNXI_TPR12=0x3533302f CONFIG_MACH_SUN55I_A523=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_R_I2C_ENABLE=y +CONFIG_SPL_SPI_SUNXI=y CONFIG_SPL_SUNXI_LED_STATUS=y CONFIG_SPL_SUNXI_LED_STATUS_GPIO=356 # CONFIG_SPL_SUNXI_LED_STATUS_ACTIVE_HIGH is not set @@ -25,11 +26,14 @@ CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_PHY_REALTEK=y +CONFIG_MTD=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y +CONFIG_PHY_REALTEK=y CONFIG_REGULATOR_AXP=y CONFIG_AXP717_POWER=y CONFIG_AXP_DCDC2_VOLT=920 CONFIG_AXP_DCDC3_VOLT=1100 +CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y From patchwork Fri May 15 23:46:01 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 2259 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sin.lore.kernel.org (sin.lore.kernel.org [104.64.211.4]) by mxe881.netcup.net (Postfix) with ESMTPS id 5641D1C0759 for ; Sat, 16 May 2026 01:47:09 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=arm.com; spf=pass (sender IP is 104.64.211.4) smtp.mailfrom=linux-sunxi+bounces-23384-noreply=patchwork.local@lists.linux.dev smtp.helo=sin.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 104.64.211.4 as permitted sender) client-ip=104.64.211.4; envelope-from=linux-sunxi+bounces-23384-noreply=patchwork.local@lists.linux.dev; helo=sin.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sin.lore.kernel.org (Postfix) with ESMTP id 57CF7300869C for ; Fri, 15 May 2026 23:46:58 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 10503405C5B; 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smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=QI/pa8EE; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CBF9635EA; Fri, 15 May 2026 16:46:48 -0700 (PDT) Received: from ryzen.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B4F4D3F85F; Fri, 15 May 2026 16:46:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778888814; bh=nLDTuVbhTgVT5ndWtc8btISM+g8RvdapSxasLBQYkLs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QI/pa8EEPBGbXhMnwkwgRoKGaFSunbKOLYVzxZp3Hh5RzkxHtaEneAcQiiiXx2Jqn xzQ7ggDZ2ru5xGtcgVvGw6lcBB2p8v0JX1Ekm23BNL79RifyBdsL2XOk1dNqATqxJE cbxChwSEgiJfhV1nS2B17Smarm+yFjmOT4I7h/Gg= From: Andre Przywara To: u-boot@lists.denx.de Cc: Tom Rini , Jernej Skrabec , Chen-Yu Tsai , Paul Kocialkowski , linux-sunxi@lists.linux.dev Subject: [PATCH v2 5/5] sunxi: configs: OrangePi 4A: enable SPI Date: Sat, 16 May 2026 01:46:01 +0200 Message-ID: <20260515234601.15431-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.4 In-Reply-To: <20260515234601.15431-1-andre.przywara@arm.com> References: <20260515234601.15431-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The OrangePi 4A board ships with SPI NOR flash, so enable the SPI and flash drivers, also the SPL version, for SPI booting. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec --- configs/orangepi_4a_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/orangepi_4a_defconfig b/configs/orangepi_4a_defconfig index 6a44dd97959..2d36757ba11 100644 --- a/configs/orangepi_4a_defconfig +++ b/configs/orangepi_4a_defconfig @@ -16,6 +16,7 @@ CONFIG_DRAM_SUNXI_TPR12=0x3a373233 CONFIG_MACH_SUN55I_A523=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_R_I2C_ENABLE=y +CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y @@ -23,10 +24,13 @@ CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MTD=y +CONFIG_SPI_FLASH_XMC=y CONFIG_REGULATOR_AXP=y CONFIG_AXP717_POWER=y CONFIG_AXP_I2C_ADDRESS=0x35 CONFIG_AXP_DCDC2_VOLT=920 CONFIG_AXP_DCDC3_VOLT=1160 +CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y