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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84164fe0bb8sm1338786b3a.51.2026.05.22.02.55.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 May 2026 02:55:57 -0700 (PDT) From: phucduc.bui@gmail.com To: broonie@kernel.org Cc: codekipper@gmail.com, jernej.skrabec@gmail.com, lgirdwood@gmail.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, linux-sunxi@lists.linux.dev, nichen@iscas.ac.cn, perex@perex.cz, samuel@sholland.org, tiwai@suse.com, wens@kernel.org, bui duc phuc Subject: [PATCH] ASoC: sunxi: sun50i-dmic: Reorder clock enable sequence Date: Fri, 22 May 2026 16:55:39 +0700 Message-ID: <20260522095539.73025-1-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-0.66 / 15.00]; BAYES_HAM(-5.50)[99.99%]; RBL_SENDERSCORE(2.00)[172.234.253.10:from]; SUSPICIOUS_RECIPS(1.50)[]; DMARC_POLICY_SOFTFAIL(1.00)[gmail.com : SPF not aligned (relaxed), No valid DKIM,none]; R_MISSING_CHARSET(0.50)[]; MAILLIST(-0.15)[generic]; BAD_REP_POLICIES(0.10)[]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; FROM_NO_DN(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[sea.lore.kernel.org:rdns,sea.lore.kernel.org:helo]; FUZZY_BLOCKED(0.00)[rspamd.com]; RCPT_COUNT_TWELVE(0.00)[14]; FORGED_SENDER_MAILLIST(0.00)[]; FREEMAIL_CC(0.00)[gmail.com,lists.infradead.org,vger.kernel.org,lists.linux.dev,iscas.ac.cn,perex.cz,sholland.org,suse.com,kernel.org]; TAGGED_RCPT(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; RCVD_COUNT_FIVE(0.00)[6]; FREEMAIL_FROM(0.00)[gmail.com]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; R_SPF_ALLOW(0.00)[+ip4:172.234.253.10:c]; TO_DN_SOME(0.00)[]; PRECEDENCE_BULK(0.00)[]; MIME_TRACE(0.00)[0:+]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; FROM_NEQ_ENVFROM(0.00)[phucducbui@gmail.com,linux-sunxi@lists.linux.dev]; RCVD_TLS_LAST(0.00)[]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; TAGGED_FROM(0.00)[bounces-23607-noreply=patchwork.local]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: AD4D21C07FA X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= From: bui duc phuc Enable the bus clock before the DMIC module clock during runtime resume. The bus clock provides the register access interface and should be enabled before the module clock. Signed-off-by: bui duc phuc --- sound/soc/sunxi/sun50i-dmic.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sound/soc/sunxi/sun50i-dmic.c b/sound/soc/sunxi/sun50i-dmic.c index eddfebe16616..7aff1afdf265 100644 --- a/sound/soc/sunxi/sun50i-dmic.c +++ b/sound/soc/sunxi/sun50i-dmic.c @@ -323,16 +323,16 @@ static int sun50i_dmic_runtime_suspend(struct device *dev) static int sun50i_dmic_runtime_resume(struct device *dev) { - struct sun50i_dmic_dev *host = dev_get_drvdata(dev); + struct sun50i_dmic_dev *host = dev_get_drvdata(dev); int ret; - ret = clk_prepare_enable(host->dmic_clk); + ret = clk_prepare_enable(host->bus_clk); if (ret) return ret; - ret = clk_prepare_enable(host->bus_clk); + ret = clk_prepare_enable(host->dmic_clk); if (ret) { - clk_disable_unprepare(host->dmic_clk); + clk_disable_unprepare(host->bus_clk); return ret; }