From patchwork Sun Jun 21 21:40:54 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuanshen Cao X-Patchwork-Id: 2451 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 4C5641C007A for ; Sun, 21 Jun 2026 23:43:25 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=gmail.com; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-23891-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; envelope-from=linux-sunxi+bounces-23891-noreply=patchwork.local@lists.linux.dev; helo=sea.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sea.lore.kernel.org (Postfix) with ESMTP id 698FD302D5E4 for ; Sun, 21 Jun 2026 21:41:33 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1C100371D05; Sun, 21 Jun 2026 21:41:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="J7q2TkfL" X-Original-To: linux-sunxi@lists.linux.dev Received: from mail-qv1-f51.google.com (mail-qv1-f51.google.com [209.85.219.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84DB2371867 for ; Sun, 21 Jun 2026 21:41:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782078093; cv=none; b=ChdCcVNLUa/pE6BEuXgZpV5mOIfVcPtRV2cQ0J221jk0BiITgCZKrCfOM60/v9z5OGo5xiFagiKNoUH+yKrzr2AbHQsbb4KQipmADOh1/3eXFchk4q5LdzZ5S9ZjvDGgkkbdEetDQE+JO2w9D9FbtRaFT9GhNhcu3VrYiKlnqUE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782078093; c=relaxed/simple; bh=sQ1wAjFR9295YnMlB9Sz4W7s2bJ8gyMgINXaeA5IRQs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=geFBh8EcDoLWnIkqV0EOwz2jPFIKE+whe6HW1JjQCYKk3dHt2F7L0euaueTt9qFiLgXXJpq4sCLBIyJ2IbOXe4XmIPWXqEJPctxnZOMFu510q/g5WXBTt+25gmLrvXtneYKYOVQK7/kaS2t0D/ExdxEYlc8nTKIG0DgK90L9998= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=J7q2TkfL; arc=none smtp.client-ip=209.85.219.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-qv1-f51.google.com with SMTP id 6a1803df08f44-8dd94941c21so34570216d6.1 for ; Sun, 21 Jun 2026 14:41:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1782078091; x=1782682891; darn=lists.linux.dev; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=XMh31ZzkY75rM1uCI6Py4J/7TBsM66ozEJNyE9b7Chg=; b=J7q2TkfLz49gjuywZqwsVyUuFPTzTw26C3x85qz1u18/jCBPIlu75uHNMRvXGD2JQ/ zC5HL4+6R/9hHZRZWPWRDyTE/1YYyfppPv2uYGma0Qf6aT+oprgwmfTtuDyDvm79Eztx WhSqb7VI5ZXABpJTuIwNhks5PSjGUUlfsIafoyc79QgzE3TaCam4S5HykkKUqFKPZ6hN WHZax1kEkX6IJ2l6G1Vd9exvBeP09hoMziYnaSTCZMvl+sL9fp1FJMkdChzmftZIX+oB bfYOQuyWph5XkuzjLj+0nE9XiWhCZBn6XckBeh+rPvSHa4D2fGwaCM8/NXDh3epdb/Nz 3XSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782078091; x=1782682891; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=XMh31ZzkY75rM1uCI6Py4J/7TBsM66ozEJNyE9b7Chg=; b=XbpDrvCTBUntbnqlJhB/FDPoVPAJtifacL06iWrN7cMnyI/ccazPIE8sp1QTNlmvaA RqQsgKWcXazGQsaRmrbrYvOtne89vW7k4u8PtH6xKrn8AFrR/3DNlcJdVEOrljdsA8Nl aVkbtkTSihIf2N1XAPacE3sGuKbFggDcXz4llMdANWB8BDnZpZwHMDiHLUGL/KTaZrXK ke2qPzFbnxcgodlaPIMwCgqf5b+qcSow/wnOkbbs8gYWEBuXGbl2+iTuCcWyNEca/P6n C+h/RllI1ZtT5inGqxqg54ho8etOaW9YBNEpxVVX3onii9U1rDVBnwq7PTH7j+5Kvzng 61sQ== X-Forwarded-Encrypted: i=1; AHgh+RqDWyU6MP4EWKhc9XSYRqPHkSeEZNHQPLnNxG4XHNxznrcReBEIz3MrKwzoMkzWV3zf1C4dexaquasOqw==@lists.linux.dev X-Gm-Message-State: AOJu0Yx+rM89pF9va7N2ej6g/crqBgGrwqfIpcK/yFQgJjAUpOaWYF+Y FMb9di3g4fl+mP/JB2chLKHVqEhG3cXi9RUxubNVi0Yt5hToEe+iqlOD X-Gm-Gg: AfdE7ckazfeYmWxLcf83EnfAqaT8K8MNrRva095dkcWttivEkhiUNfDdStRVXUsZOFA WiSWJHIn4dxLBA62602gQ7Ro1v+WfJFV1d83YxEeKsFvC0HL7ElnV1F2iNawZx1QkTM7bKRhyOt jXhJzhpv6ld+STGETjzYxjm7uCb1h0lXPuJx5BDOVIG36zu45pQa0jLSFDj5xwJ889BXvPgCbjc Z4F9No/eSdMjkHbTyBQFCrsdNudsoaXnRHnTExLGayu4xFD02xe7FlkjhbHQP+OXnBlUfsDJFXb 7wxrPleTiKNxrvPIK+uATDy9LcuXSB7cFbYTsFD7bbv+E4V8iQ7GkQXWHGrY7fkR4M+ANmXk4Zc Izqd28+aD+/a4ELjY7XqCCLz7AQ1fN+aGXPZ7lBWpzG5dEUihtFgixzkBuMhcV7oKPCy07QdiOP zLiXKJb4iGg2E/2g== X-Received: by 2002:a05:6214:1bc6:b0:8cc:ed49:bdc9 with SMTP id 6a1803df08f44-8de3b43e008mr217413546d6.5.1782078090586; Sun, 21 Jun 2026 14:41:30 -0700 (PDT) Received: from [172.17.0.2] ([138.28.231.64]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8df81cde9ecsm76274676d6.24.2026.06.21.14.41.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2026 14:41:30 -0700 (PDT) From: Yuanshen Cao Date: Sun, 21 Jun 2026 21:40:54 +0000 Subject: [PATCH v2 1/5] dmaengine: sun6i-dma: Refactor to support A733 interrupt and register handling Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260621-sun60i-a733-dma-v2-1-340f205891cc@gmail.com> References: <20260621-sun60i-a733-dma-v2-0-340f205891cc@gmail.com> In-Reply-To: <20260621-sun60i-a733-dma-v2-0-340f205891cc@gmail.com> To: Vinod Koul , Frank Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: Yuanshen Cao , dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.15.2 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Refactor to support the Allwinner A733 DMA controller. Currently, the `sun6i-dma` driver has several functions related to interrupt handling (reading/writing interrupt enable and status registers) and register dumping that are hardcoded. To support the A733, which has different register layouts and interrupt handling logic, these functions are being moved into the `sun6i_dma_config` structure as function pointers. This allows the driver to use a polymorphic approach where the specific implementation is determined by the hardware configuration assigned during device probing. Changes: - Added function pointers to `struct sun6i_dma_config` for: - `dump_com_regs` - `read_irq_en` - `write_irq_en` - `read_irq_stat` - `write_irq_stat` - Implemented generic `sun6i_read/write_irq_*` functions for existing hardware. - Added a macro and updated existing `sun6i_dma_config` instances (A31, A23, H3, A64, A100, H6, V3S) to use these new function pointers. Signed-off-by: Yuanshen Cao Reviewed-by: Frank Li --- drivers/dma/sun6i-dma.c | 50 ++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 45 insertions(+), 5 deletions(-) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index a9a254dbf8cb..ef3052c4ab36 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -138,6 +138,11 @@ struct sun6i_dma_config { void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst); void (*set_drq)(u32 *p_cfg, s8 src_drq, s8 dst_drq); void (*set_mode)(u32 *p_cfg, s8 src_mode, s8 dst_mode); + void (*dump_com_regs)(struct sun6i_dma_dev *sdev); + u32 (*read_irq_en)(struct sun6i_dma_dev *sdev, u32 irq_reg); + void (*write_irq_en)(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 irq_val); + u32 (*read_irq_stat)(struct sun6i_dma_dev *sdev, u32 irq_reg); + void (*write_irq_stat)(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 status); u32 src_burst_lengths; u32 dst_burst_lengths; u32 src_addr_widths; @@ -347,6 +352,26 @@ static void sun6i_set_mode_h6(u32 *p_cfg, s8 src_mode, s8 dst_mode) DMA_CHAN_CFG_DST_MODE_H6(dst_mode); } +static u32 sun6i_read_irq_en(struct sun6i_dma_dev *sdev, u32 irq_reg) +{ + return readl(sdev->base + DMA_IRQ_EN(irq_reg)); +} + +static void sun6i_write_irq_en(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 irq_val) +{ + writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg)); +} + +static u32 sun6i_read_irq_stat(struct sun6i_dma_dev *sdev, u32 irq_reg) +{ + return readl(sdev->base + DMA_IRQ_STAT(irq_reg)); +} + +static void sun6i_write_irq_stat(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 status) +{ + writel(status, sdev->base + DMA_IRQ_STAT(irq_reg)); +} + static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan) { struct sun6i_desc *txd = pchan->desc; @@ -460,16 +485,16 @@ static int sun6i_dma_start_desc(struct sun6i_vchan *vchan) vchan->irq_type = vchan->cyclic ? DMA_IRQ_PKG : DMA_IRQ_QUEUE; - irq_val = readl(sdev->base + DMA_IRQ_EN(irq_reg)); + irq_val = sdev->cfg->read_irq_en(sdev, irq_reg); irq_val &= ~((DMA_IRQ_HALF | DMA_IRQ_PKG | DMA_IRQ_QUEUE) << (irq_offset * DMA_IRQ_CHAN_WIDTH)); irq_val |= vchan->irq_type << (irq_offset * DMA_IRQ_CHAN_WIDTH); - writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg)); + sdev->cfg->write_irq_en(sdev, irq_reg, irq_val); writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR); writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE); - sun6i_dma_dump_com_regs(sdev); + sdev->cfg->dump_com_regs(sdev); sun6i_dma_dump_chan_regs(sdev, pchan); return 0; @@ -549,14 +574,14 @@ static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id) u32 status; for (i = 0; i < sdev->num_pchans / DMA_IRQ_CHAN_NR; i++) { - status = readl(sdev->base + DMA_IRQ_STAT(i)); + status = sdev->cfg->read_irq_stat(sdev, i); if (!status) continue; dev_dbg(sdev->slave.dev, "DMA irq status %s: 0x%x\n", str_high_low(i), status); - writel(status, sdev->base + DMA_IRQ_STAT(i)); + sdev->cfg->write_irq_stat(sdev, i, status); for (j = 0; (j < DMA_IRQ_CHAN_NR) && status; j++) { pchan = sdev->pchans + j; @@ -1101,6 +1126,13 @@ static inline void sun6i_dma_free(struct sun6i_dma_dev *sdev) } } +#define SUN6I_DMA_IRQ_A31_COMMON_OPS \ + .dump_com_regs = sun6i_dma_dump_com_regs, \ + .read_irq_en = sun6i_read_irq_en, \ + .write_irq_en = sun6i_write_irq_en, \ + .read_irq_stat = sun6i_read_irq_stat, \ + .write_irq_stat = sun6i_write_irq_stat, + /* * For A31: * @@ -1132,6 +1164,7 @@ static struct sun6i_dma_config sun6i_a31_dma_cfg = { .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_OPS }; /* @@ -1155,6 +1188,7 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = { .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_OPS }; static struct sun6i_dma_config sun8i_a83t_dma_cfg = { @@ -1173,6 +1207,7 @@ static struct sun6i_dma_config sun8i_a83t_dma_cfg = { .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_OPS }; /* @@ -1200,6 +1235,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_OPS }; /* @@ -1221,6 +1257,7 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_OPS }; /* @@ -1244,6 +1281,7 @@ static struct sun6i_dma_config sun50i_a100_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), .has_high_addr = true, .has_mbus_clk = true, + SUN6I_DMA_IRQ_A31_COMMON_OPS }; /* @@ -1266,6 +1304,7 @@ static struct sun6i_dma_config sun50i_h6_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), .has_mbus_clk = true, + SUN6I_DMA_IRQ_A31_COMMON_OPS }; /* @@ -1289,6 +1328,7 @@ static struct sun6i_dma_config sun8i_v3s_dma_cfg = { .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_OPS }; static const struct of_device_id sun6i_dma_match[] = { From patchwork Sun Jun 21 21:40:55 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuanshen Cao X-Patchwork-Id: 2452 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 730991C007A for ; Sun, 21 Jun 2026 23:43:57 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=gmail.com; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-23892-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; envelope-from=linux-sunxi+bounces-23892-noreply=patchwork.local@lists.linux.dev; helo=sea.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sea.lore.kernel.org (Postfix) with ESMTP id 94A55303CA53 for ; Sun, 21 Jun 2026 21:41:35 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D8E09371D0A; Sun, 21 Jun 2026 21:41:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ckg0/mSi" X-Original-To: linux-sunxi@lists.linux.dev Received: from mail-qv1-f45.google.com (mail-qv1-f45.google.com [209.85.219.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE8CF371CEC for ; Sun, 21 Jun 2026 21:41:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782078094; cv=none; b=P7Rd3uuQjpnw0+8OdvxJg1z7aiXyN0DEbBiLcmKhjU0hPD1A9yjbU9J+GOOsbG8wBzsLDm81Ib34oI0AOhVAZ58yjIMYwoS/xEDKrM+WWuoWmOrIE0OEr3Z6majHfYSkLhucAJOIU0H6qjwEBgyUAMPLapHPz3xHAlw1VjMlflM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782078094; c=relaxed/simple; bh=dQJRxOtJBIdsX16Td7qmdew1G14whihD+vf5uq3M+Yk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oZObZPyTq9MMHn+NE1xlM6Neig4ZP//ThjMwrqEjKeYuM0SeeS3vZD62uDfUfyRXpjxXOg8EHflsRKVH2TqMaII4zeC7JgAlL2Jw3oFerxHZY8SEEcTbrVUr1pQz4oktXiaONi4eXSMt0BDy70WmPQv9i8Xb5e9Dp/en34EU7Ws= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ckg0/mSi; arc=none smtp.client-ip=209.85.219.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-qv1-f45.google.com with SMTP id 6a1803df08f44-8de2adc59d8so29341606d6.1 for ; Sun, 21 Jun 2026 14:41:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1782078092; x=1782682892; darn=lists.linux.dev; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=gDRD6LBgJnjsi6QsqIJwMXkO05zRf+ayGk9t0C1JISo=; b=ckg0/mSiqXczLZwGrJEJzuu99OAJzU/i/g3g5KrJMIZdVSrJfsaYc3XphCO7ALXZ3p T51E5Uz1q94ojbFTecVXE7EYXA2w7QdJR+SZaYxn5lXN/0GACqVIWBTL5Qr4PLMZrtpb +yhpNkcd3EdAbBARVmni/Ulb5KgHzKPH41kgmlsfj0bh7Ble+krcmdChoEEQ5DXBh/Cj ojDc+adoZBXmlhLeO6OKsfn13QhpKYXDoD0WG79InZb2Rh2owW9aSccnYu/eYPBJyDK1 tF5k8V5QVUPhmNDQa/rVLnockCwR93bdTIMulO2adqEso3Lol0l1wWL5YCvojakWnLPp hhzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782078092; x=1782682892; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=gDRD6LBgJnjsi6QsqIJwMXkO05zRf+ayGk9t0C1JISo=; b=glHB0i/2/M3WD2v1zm9HhsuzkTh8X7g1GWUz4pyAdXEubLlUveIdtHlgoznJRtJqvY MA91QtweMtnixM2WYJJwKQip77TGbv3mFWJdi3wsWbQJudt8pNG1kXJFQMPBJAbkcoNz hcF4Ayq8mr9XfSJmxbLN1qcvJONq1472DHNpkzWtwuh8XMZT/7RH01nB5unOS4tEFCKh 9RiTGswWrpgZChOlnckg56tc6pJ4EMzE7IxA/gDXJrU2r6CvpL/t5jCNOXKASeNkbQH6 cURGWpzR7WcXv7WX8SqftHdiGgakLb1C6W6E02/12a6K5KO/F1iEae74O178Xq6SDvgr XhEg== X-Forwarded-Encrypted: i=1; AHgh+RqBFaLGAukT7QmSYF4xazR7K0gpUSvn83iHu35DQOslLoAIYmo8gQh2WrVPtdcc5F/50efJ/krrn+H1Rg==@lists.linux.dev X-Gm-Message-State: AOJu0YzuBhOVQlZwYovsOugO15bA7pALU4ME1N7tDP9BZ9C1qNAMelgq gy+mn6K+zzIpTl5tBfExIoj4twPq2/igRRZwvVhhC/ZuNsf1V39eHXan X-Gm-Gg: AfdE7cmvqCV7VxfUAP4OTTISUuxDmCzUgfu+JU5UixaTaawMog+J3gePJIuNSFZcdDd CWJComPZhKI3HarXb/YnWzRWc++1ya3Ft2oOAtX2atbq2c/7UzyK0ZlPY+GLI4FVEZF3dqwts3j 3ofh6osfgD2uYPxw98qHCZbTfr761OKt0LjawZGBBg6uHzEVJHgvHooAzOMWl3hATdjsOBLqVQW JiFSt38vvzd3WGhTxyLNsI3ESe+a31AlLxGW/9dyt9I6z+Gq4w7Rr6JyagnoT+yPic8QfjKEsjD ZUN5nPPHzOUX0j92Bd4R70aTNlO+mCkHF7g3Z66+Nwh+dmp3QvhX53Uc0SPKMv+airboCQZPwq4 RX1f4Hh8Hnbs1n8C9JamM3ksDUtrwCFQ/vS5SKL83VV+O035f4D6OSSJwhjdj3CwjfX8/8rPu+1 yNOZAJ/VooRj/FUA== X-Received: by 2002:a0c:e004:0:b0:8cc:f3a0:20aa with SMTP id 6a1803df08f44-8de4c46b4admr132602906d6.20.1782078091871; Sun, 21 Jun 2026 14:41:31 -0700 (PDT) Received: from [172.17.0.2] ([138.28.231.64]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8df81cde9ecsm76274676d6.24.2026.06.21.14.41.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2026 14:41:31 -0700 (PDT) From: Yuanshen Cao Date: Sun, 21 Jun 2026 21:40:55 +0000 Subject: [PATCH v2 2/5] dmaengine: sun6i-dma: Add set_addr function pointer for variable address widths Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260621-sun60i-a733-dma-v2-2-340f205891cc@gmail.com> References: <20260621-sun60i-a733-dma-v2-0-340f205891cc@gmail.com> In-Reply-To: <20260621-sun60i-a733-dma-v2-0-340f205891cc@gmail.com> To: Vinod Koul , Frank Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: Yuanshen Cao , dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.15.2 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-1.16 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.234.253.10:from]; SUSPICIOUS_RECIPS(1.50)[]; DMARC_POLICY_SOFTFAIL(1.00)[gmail.com : SPF not aligned (relaxed), No valid DKIM,none]; MAILLIST(-0.15)[generic]; BAD_REP_POLICIES(0.10)[]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; TAGGED_RCPT(0.00)[dt]; PRECEDENCE_BULK(0.00)[]; RCPT_COUNT_TWELVE(0.00)[15]; FUZZY_BLOCKED(0.00)[rspamd.com]; FORGED_SENDER_MAILLIST(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[sea.lore.kernel.org:rdns,sea.lore.kernel.org:helo]; FREEMAIL_CC(0.00)[gmail.com,vger.kernel.org,lists.infradead.org,lists.linux.dev]; TO_DN_SOME(0.00)[]; R_SPF_ALLOW(0.00)[+ip4:172.234.253.10]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; FREEMAIL_FROM(0.00)[gmail.com]; MIME_TRACE(0.00)[0:+]; RCVD_TLS_LAST(0.00)[]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; FREEMAIL_TO(0.00)[kernel.org,gmail.com,sholland.org]; FROM_HAS_DN(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; TAGGED_FROM(0.00)[bounces-23892-noreply=patchwork.local]; RCVD_COUNT_FIVE(0.00)[6]; FROM_NEQ_ENVFROM(0.00)[alexcaoys@gmail.com,linux-sunxi@lists.linux.dev]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 730991C007A X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The A733 DMA controller supports higher address (up to 32G) compared to previous generations. The existing `sun6i_dma_set_addr` function uses a hardcoded logic for setting the high-address bits in the LLI parameters. By moving `set_addr` into the `sun6i_dma_config` structure, we can provide specialized implementations for different hardware. This allows the A733 to use a version of `set_addr` that correctly handles its specific `SRC_HIGH_ADDR_32G` and `DST_HIGH_ADDR_32G` in the `set_addr` register later in the series. Changes: - Added `set_addr` function pointer to `struct sun6i_dma_config`. - Refactored `sun6i_dma_set_addr` and introduced `sun6i_dma_set_addr_a31/a100` (keeping the logic for previous generations). - Updated all existing configuration structs to include the new `set_addr` pointer. - Removed `has_high_addr` since the logic is replaced by `sun6i_dma_set_addr_a100`. Signed-off-by: Yuanshen Cao Reviewed-by: Frank Li --- drivers/dma/sun6i-dma.c | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index ef3052c4ab36..9984b9033cbb 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -112,6 +112,7 @@ /* forward declaration */ struct sun6i_dma_dev; +struct sun6i_dma_lli; /* * Hardware channels / ports representation @@ -138,6 +139,8 @@ struct sun6i_dma_config { void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst); void (*set_drq)(u32 *p_cfg, s8 src_drq, s8 dst_drq); void (*set_mode)(u32 *p_cfg, s8 src_mode, s8 dst_mode); + void (*set_addr)(struct sun6i_dma_dev *sdev, struct sun6i_dma_lli *v_lli, + dma_addr_t src, dma_addr_t dst); void (*dump_com_regs)(struct sun6i_dma_dev *sdev); u32 (*read_irq_en)(struct sun6i_dma_dev *sdev, u32 irq_reg); void (*write_irq_en)(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 irq_val); @@ -147,7 +150,6 @@ struct sun6i_dma_config { u32 dst_burst_lengths; u32 src_addr_widths; u32 dst_addr_widths; - bool has_high_addr; bool has_mbus_clk; }; @@ -673,16 +675,30 @@ static int set_config(struct sun6i_dma_dev *sdev, return 0; } -static inline void sun6i_dma_set_addr(struct sun6i_dma_dev *sdev, +static void sun6i_dma_set_addr_a31(struct sun6i_dma_dev *sdev, + struct sun6i_dma_lli *v_lli, + dma_addr_t src, dma_addr_t dst) +{ + v_lli->src = lower_32_bits(src); + v_lli->dst = lower_32_bits(dst); +} + +static void sun6i_dma_set_addr_a100(struct sun6i_dma_dev *sdev, struct sun6i_dma_lli *v_lli, dma_addr_t src, dma_addr_t dst) { v_lli->src = lower_32_bits(src); v_lli->dst = lower_32_bits(dst); - if (sdev->cfg->has_high_addr) - v_lli->para |= SRC_HIGH_ADDR(upper_32_bits(src)) | - DST_HIGH_ADDR(upper_32_bits(dst)); + v_lli->para |= SRC_HIGH_ADDR(upper_32_bits(src)) | + DST_HIGH_ADDR(upper_32_bits(dst)); +} + +static inline void sun6i_dma_set_addr(struct sun6i_dma_dev *sdev, + struct sun6i_dma_lli *v_lli, + dma_addr_t src, dma_addr_t dst) +{ + sdev->cfg->set_addr(sdev, v_lli, src, dst); } static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy( @@ -1156,6 +1172,7 @@ static struct sun6i_dma_config sun6i_a31_dma_cfg = { .set_burst_length = sun6i_set_burst_length_a31, .set_drq = sun6i_set_drq_a31, .set_mode = sun6i_set_mode_a31, + .set_addr = sun6i_dma_set_addr_a31, .src_burst_lengths = BIT(1) | BIT(8), .dst_burst_lengths = BIT(1) | BIT(8), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | @@ -1180,6 +1197,7 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = { .set_burst_length = sun6i_set_burst_length_a31, .set_drq = sun6i_set_drq_a31, .set_mode = sun6i_set_mode_a31, + .set_addr = sun6i_dma_set_addr_a31, .src_burst_lengths = BIT(1) | BIT(8), .dst_burst_lengths = BIT(1) | BIT(8), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | @@ -1199,6 +1217,7 @@ static struct sun6i_dma_config sun8i_a83t_dma_cfg = { .set_burst_length = sun6i_set_burst_length_a31, .set_drq = sun6i_set_drq_a31, .set_mode = sun6i_set_mode_a31, + .set_addr = sun6i_dma_set_addr_a31, .src_burst_lengths = BIT(1) | BIT(8), .dst_burst_lengths = BIT(1) | BIT(8), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | @@ -1225,6 +1244,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { .set_burst_length = sun6i_set_burst_length_h3, .set_drq = sun6i_set_drq_a31, .set_mode = sun6i_set_mode_a31, + .set_addr = sun6i_dma_set_addr_a31, .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | @@ -1247,6 +1267,7 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg = { .set_burst_length = sun6i_set_burst_length_h3, .set_drq = sun6i_set_drq_a31, .set_mode = sun6i_set_mode_a31, + .set_addr = sun6i_dma_set_addr_a31, .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | @@ -1269,6 +1290,7 @@ static struct sun6i_dma_config sun50i_a100_dma_cfg = { .set_burst_length = sun6i_set_burst_length_h3, .set_drq = sun6i_set_drq_h6, .set_mode = sun6i_set_mode_h6, + .set_addr = sun6i_dma_set_addr_a100, .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | @@ -1279,7 +1301,6 @@ static struct sun6i_dma_config sun50i_a100_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), - .has_high_addr = true, .has_mbus_clk = true, SUN6I_DMA_IRQ_A31_COMMON_OPS }; @@ -1293,6 +1314,7 @@ static struct sun6i_dma_config sun50i_h6_dma_cfg = { .set_burst_length = sun6i_set_burst_length_h3, .set_drq = sun6i_set_drq_h6, .set_mode = sun6i_set_mode_h6, + .set_addr = sun6i_dma_set_addr_a31, .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | @@ -1320,6 +1342,7 @@ static struct sun6i_dma_config sun8i_v3s_dma_cfg = { .set_burst_length = sun6i_set_burst_length_a31, .set_drq = sun6i_set_drq_a31, .set_mode = sun6i_set_mode_a31, + .set_addr = sun6i_dma_set_addr_a31, .src_burst_lengths = BIT(1) | BIT(8), .dst_burst_lengths = BIT(1) | BIT(8), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | From patchwork Sun Jun 21 21:40:56 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuanshen Cao X-Patchwork-Id: 2454 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 7901E1C007A for ; Sun, 21 Jun 2026 23:45:26 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=gmail.com; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-23894-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; envelope-from=linux-sunxi+bounces-23894-noreply=patchwork.local@lists.linux.dev; helo=sea.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sea.lore.kernel.org (Postfix) with ESMTP id 3FEAA304A8D1 for ; Sun, 21 Jun 2026 21:41:41 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 99740371D19; Sun, 21 Jun 2026 21:41:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JeMbfw13" X-Original-To: linux-sunxi@lists.linux.dev Received: from mail-qt1-f180.google.com (mail-qt1-f180.google.com [209.85.160.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FCAF371CE3 for ; Sun, 21 Jun 2026 21:41:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782078098; cv=none; b=Ngbuz2ch2a7p6C3CGerQbMpDroDXBUYdUpjMFF2UzUR8jgRjdj7G/nWGIiavyNbe+Ki6zKd8qEMJZRa4YrC2QNg79q2wntrc8XhhHLT5a97m7rA1crvinRNgGbPjNBLKKeUKWm8B+pwyFFVugdD1aZncXfe5mbhbofD9DSKjfcA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782078098; c=relaxed/simple; bh=nx3mp9nLCWLGwwhXcXHx8zANBb94IT7PqVcAiE3F6PQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lDS6NxbtIupFrkYsR6GscmZF2TdLhSXexsEyMg+IQ7Ra2alPQ+3ktjxxKm0lnJzhVCmMAyrR2019VSDVf/61UzbSdTFhq2s8EQ8xlRGn6JiCAKWyPXCqF20lxhHebavcAVzhpNI3YlUVW6GSux9zz9iZg3/WlYCrE/90lHhJ+IA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=JeMbfw13; arc=none smtp.client-ip=209.85.160.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-qt1-f180.google.com with SMTP id d75a77b69052e-517de710886so29997061cf.3 for ; Sun, 21 Jun 2026 14:41:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1782078093; x=1782682893; darn=lists.linux.dev; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=WoB3WtpCVismpnSqyX/NJ4l5EF9+u+wVTQ5wN075Edc=; b=JeMbfw13jOt/PWmQrC9RllPXo33d1gykxybY07x/Dp4AMTJKLiQWA109/+1CgWel4a PYtLe2bLVqDoXALcIOHFVpbEV08xhOgH5d1w58kIToj4drLlIGYs8lcTc2pdX0d7QZlc qb4VM6GwC3kHLF92NO77Q/gjY+q3kpxElP+wM5haL/u9XuqS5aPZYqqnlQDV7le/if+R FN9aECdCIK3E9zjKOblqi63mg/8qLhI41UT1w1qSXRF6YIXz8X6O467WjptCGimggQSq w5m+PQulN4qiyqIU09Tu0HF94QiNmy8IDMzJqNdMjbYaC+6crEVM8KhglIC87vzgTU4c vaxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782078093; x=1782682893; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=WoB3WtpCVismpnSqyX/NJ4l5EF9+u+wVTQ5wN075Edc=; b=S5t89sElAUGTxMRomRvn8iCtoHl+qEA7yBB9GjACIpn9a269C5lFlO6vkF2XrW4dv3 IXSt4elqdRIYWW25uWVGm5pT7brvooIhhe9WItdc60nge37eNdGSr+B0lAhYqVcBsJGl 68USP4s+wU5rvnY9rLf69YgLWWL1bO0/insLqfvH/yjR/ak6TzVwvbSuSanO4/wW/tzm h/apx8F/+lxor4IfFuVNxF5GX9EmodQd+sqvU303xT7Fjb9KZwaaiEYrm605S5Nd4rtC YkqGshh4o209L6203cLgFMysspC9O0OdaC7zRCnsyt06Hgi4p8TpNx2oQ5mv+Sz7EErc N5eg== X-Forwarded-Encrypted: i=1; AFNElJ8TBwNpYUWXIxO5CRfOezneULWN/El+GEPuE6blY6cuYX3iUV1Q9UDf+4WKLXT3D6WN6BvAWpQ7xpTtMQ==@lists.linux.dev X-Gm-Message-State: AOJu0YxjinF+97uii/ft1JoOirc/sYG1XhABK6E72gLYW+dgM/fYCpSs bhSUjBkIbXc2xOmfm33+wIt16dSWi00V9SDbzsKReQm/anvN9fWOtO09 X-Gm-Gg: AfdE7cmd78QfDFKOGe0+3RGA/PCEvR1kaq7PCb9TzoHPZMVIz7auzIHXD492RwJw9jQ TeyQPTf3mz8Blx3HD4QZAsF29q9Qg2MEGGmf/w6ZQtleWWYWQfJjxCdhpkoPlkZomCrxHcQmpPD iQJrdKSVNRnOLzkgjk+KmZhUHpYY69CUAW+7G39VP+gGv3eiNnL05rdvfRQnQVhVOJqDRrBiYT+ XXLo0vpzEPqIkkU5SafHCawhRCSl7xmtPz1ouFcvrhQ/twIZuod2Imu8NIFe8PeP5eK+IwM5VH9 VmNymsqF8v65YRosSVv4O8XS+ShYN2+NjWGZ7n7RizHWVLzEdhdyIcA0JnZFn4c5DzLTnVLRE58 618/8MNAPSGPbd7ZgXuZx/Yan9T86qg8Db8vBYPq0y8QcqvyDhZZRK0oHw1Aq59ZPjoMarGgwLt /ktAG0bb5o4ueKSw== X-Received: by 2002:ac8:5806:0:b0:517:a02f:171e with SMTP id d75a77b69052e-519f04913d6mr162441741cf.30.1782078093134; Sun, 21 Jun 2026 14:41:33 -0700 (PDT) Received: from [172.17.0.2] ([138.28.231.64]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8df81cde9ecsm76274676d6.24.2026.06.21.14.41.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2026 14:41:32 -0700 (PDT) From: Yuanshen Cao Date: Sun, 21 Jun 2026 21:40:56 +0000 Subject: [PATCH v2 3/5] dmaengine: sun6i-dma: Add num_channels_per_reg for flexible interrupt mapping Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260621-sun60i-a733-dma-v2-3-340f205891cc@gmail.com> References: <20260621-sun60i-a733-dma-v2-0-340f205891cc@gmail.com> In-Reply-To: <20260621-sun60i-a733-dma-v2-0-340f205891cc@gmail.com> To: Vinod Koul , Frank Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: Yuanshen Cao , dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.15.2 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The previous implementation of `sun6i-dma` had some implicit assumptions about the number of channels per interrupt register. Specifically, functions like `sun6i_kill_tasklet` were hardcoded to only disable interrupts for IRQ 0 and 1. `DMA_MAX_CHANNELS` is also not in used in the past, and the old SoCs never has more than 16 channels. The A733 has a different interrupt structure where the number of channels per register may differ. This patch introduces `num_channels_per_reg` to the `sun6i_dma_config`, similar to BSP, to make the interrupt handling logic hardware-agnostic. It also sets `DMA_MAX_CHANNELS` to 16 to align with the new BSP code and ensure loops over interrupts are correctly bounded. Changes: - Change `DMA_MAX_CHANNELS` definition to 16. - Added `num_channels_per_reg` to `struct sun6i_dma_config`. - Replaced hardcoded IRQ register calculations with values from `sdev->cfg->num_channels_per_reg`. - Updated `sun6i_kill_tasklet` to loop through all possible interrupt registers based on `DMA_MAX_CHANNELS` and the configuration. Signed-off-by: Yuanshen Cao Reviewed-by: Frank Li --- drivers/dma/sun6i-dma.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index 9984b9033cbb..196a0d73b221 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -41,7 +41,7 @@ #define DMA_STAT 0x30 /* Offset between DMA_IRQ_EN and DMA_IRQ_STAT limits number of channels */ -#define DMA_MAX_CHANNELS (DMA_IRQ_CHAN_NR * 0x10 / 4) +#define DMA_MAX_CHANNELS 16 /* * sun8i specific registers @@ -151,6 +151,7 @@ struct sun6i_dma_config { u32 src_addr_widths; u32 dst_addr_widths; bool has_mbus_clk; + u32 num_channels_per_reg; }; /* @@ -482,8 +483,8 @@ static int sun6i_dma_start_desc(struct sun6i_vchan *vchan) sun6i_dma_dump_lli(vchan, pchan->desc->v_lli, pchan->desc->p_lli); - irq_reg = pchan->idx / DMA_IRQ_CHAN_NR; - irq_offset = pchan->idx % DMA_IRQ_CHAN_NR; + irq_reg = pchan->idx / sdev->cfg->num_channels_per_reg; + irq_offset = pchan->idx % sdev->cfg->num_channels_per_reg; vchan->irq_type = vchan->cyclic ? DMA_IRQ_PKG : DMA_IRQ_QUEUE; @@ -575,7 +576,7 @@ static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id) int i, j, ret = IRQ_NONE; u32 status; - for (i = 0; i < sdev->num_pchans / DMA_IRQ_CHAN_NR; i++) { + for (i = 0; i < sdev->num_pchans / sdev->cfg->num_channels_per_reg; i++) { status = sdev->cfg->read_irq_stat(sdev, i); if (!status) continue; @@ -585,7 +586,7 @@ static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id) sdev->cfg->write_irq_stat(sdev, i, status); - for (j = 0; (j < DMA_IRQ_CHAN_NR) && status; j++) { + for (j = 0; (j < sdev->cfg->num_channels_per_reg) && status; j++) { pchan = sdev->pchans + j; vchan = pchan->vchan; if (vchan && (status & vchan->irq_type)) { @@ -1116,9 +1117,11 @@ static struct dma_chan *sun6i_dma_of_xlate(struct of_phandle_args *dma_spec, static inline void sun6i_kill_tasklet(struct sun6i_dma_dev *sdev) { + int i; + /* Disable all interrupts from DMA */ - writel(0, sdev->base + DMA_IRQ_EN(0)); - writel(0, sdev->base + DMA_IRQ_EN(1)); + for (i = 0; i < DMA_MAX_CHANNELS / sdev->cfg->num_channels_per_reg; i++) + sdev->cfg->write_irq_en(sdev, i, 0); /* Prevent spurious interrupts from scheduling the tasklet */ atomic_inc(&sdev->tasklet_shutdown); @@ -1181,6 +1184,7 @@ static struct sun6i_dma_config sun6i_a31_dma_cfg = { .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + .num_channels_per_reg = DMA_IRQ_CHAN_NR, SUN6I_DMA_IRQ_A31_COMMON_OPS }; @@ -1206,6 +1210,7 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = { .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + .num_channels_per_reg = DMA_IRQ_CHAN_NR, SUN6I_DMA_IRQ_A31_COMMON_OPS }; @@ -1226,6 +1231,7 @@ static struct sun6i_dma_config sun8i_a83t_dma_cfg = { .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + .num_channels_per_reg = DMA_IRQ_CHAN_NR, SUN6I_DMA_IRQ_A31_COMMON_OPS }; @@ -1255,6 +1261,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), + .num_channels_per_reg = DMA_IRQ_CHAN_NR, SUN6I_DMA_IRQ_A31_COMMON_OPS }; @@ -1278,6 +1285,7 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), + .num_channels_per_reg = DMA_IRQ_CHAN_NR, SUN6I_DMA_IRQ_A31_COMMON_OPS }; @@ -1301,6 +1309,7 @@ static struct sun6i_dma_config sun50i_a100_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), + .num_channels_per_reg = DMA_IRQ_CHAN_NR, .has_mbus_clk = true, SUN6I_DMA_IRQ_A31_COMMON_OPS }; @@ -1325,6 +1334,7 @@ static struct sun6i_dma_config sun50i_h6_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), + .num_channels_per_reg = DMA_IRQ_CHAN_NR, .has_mbus_clk = true, SUN6I_DMA_IRQ_A31_COMMON_OPS }; @@ -1351,6 +1361,7 @@ static struct sun6i_dma_config sun8i_v3s_dma_cfg = { .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + .num_channels_per_reg = DMA_IRQ_CHAN_NR, SUN6I_DMA_IRQ_A31_COMMON_OPS }; From patchwork Sun Jun 21 21:40:57 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuanshen Cao X-Patchwork-Id: 2453 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 66B341C007A for ; Sun, 21 Jun 2026 23:45:24 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=gmail.com; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-23893-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; envelope-from=linux-sunxi+bounces-23893-noreply=patchwork.local@lists.linux.dev; helo=sea.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sea.lore.kernel.org (Postfix) with ESMTP id 223103049977 for ; Sun, 21 Jun 2026 21:41:41 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8F40E372663; Sun, 21 Jun 2026 21:41:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FYHUN9Qa" X-Original-To: linux-sunxi@lists.linux.dev Received: from mail-qv1-f49.google.com (mail-qv1-f49.google.com [209.85.219.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 560E2371CE6 for ; Sun, 21 Jun 2026 21:41:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782078098; cv=none; b=I2DTyZ87e/YVik1Ugxeetta27JUSNJ/GZP/UdEjx+8fEZ/g6FjEAsd6WGZD83mpKrdY/1soTUKHr6TSGKW+odF4d4eN/RNW+LDYJ76FS6lqG/xKwe5u6h/PW31Hepo5QeubmR4tMpxj0uN0oSWuSk1+RJWoFNiPn8VMA4RfuST0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782078098; c=relaxed/simple; bh=snXtiK6PEmUwjwB87Qy4uEGoHKMvUL4i+B4X0NTiCQQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uQn/KbRVO9S/T8MkWPEt7B4t4o6x4dC9nWy8hRa7C8mbPZm9yDxwLcrPHrCijb2KODITuPq+/LzVBOEs7eRrr0omvDd4knRF/HfEioMwO0MOFh8jhtWHwi2p384HFVRC6McuzWY7op/ln0tG79MFwLTgkPcSHwPoET+sggbhOq4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=FYHUN9Qa; arc=none smtp.client-ip=209.85.219.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-qv1-f49.google.com with SMTP id 6a1803df08f44-8dea42b547eso39167486d6.1 for ; Sun, 21 Jun 2026 14:41:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1782078094; x=1782682894; darn=lists.linux.dev; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=HTAQ0YVnmRPUTpM5kMc2Jmb3ZZIxno5dgQysePNdwmo=; b=FYHUN9QaAmv54QSOb8vX6KOaMP3UNYtYlyAZ2pgfIGU/CU6Nhtqq5qyyTt7HYovsvy n0Z+UlKTAAn3ftm/ohHicAaB5U7Z/PbnjkRdewGMWrnu7Cp0oqQ9dy0JT4XIxtH4RS5B 0NoUhjwDbKEnig3J5iX6TnSz5TC9/3VzTGG2yclQ1LQDqb81dVqL8nwAIZ5qHQKeYhdq QT5ppVgRYyw/dS5wgptj+Vh+SIrWL9+fyZd2nS92LRvau1NzBZz5U2U7K/CMcUDBMF5q YQUm+yE5FUV+l2syxA/xjHcxukSxVtDsoC+2bc1vAwMSKdfushnqMrxa1GgFzo3bmJyf RFFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782078094; x=1782682894; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=HTAQ0YVnmRPUTpM5kMc2Jmb3ZZIxno5dgQysePNdwmo=; b=hrUm/eheca1sS3iS49mc8YkgjAjxI7sVVZxQA2N5dmU3/XwjAgPbURvbpXyQBmfztU JVrSjsVMMpU7Pdr00d+7e/D9rK/eJYswlOthxBEpA9R80PKc+f3Ln1wL2CX9PK6oDS/r TeQeU/05GCGJaiEqIlm02Aa7vBgUFZ2OE2HqSEV2vvNN7BJec6cUH+LH/VQ3B0UWcoVH ml/Rk4f0105Pp0InxcNkNOSwmM99bVQvgi3fO++MgfY22TKabkQNEA7sKXn84lUm8xSW lSoB4D6QoMfST3brx5YY9eKiUECBjdrsSNwkPLAmRsG/iivsY0hedQiSqy+fQDDUQV7O 3hFg== X-Forwarded-Encrypted: i=1; AHgh+RokQ4VuUVcT1ihhbouugb8kFUlv7Lb5qaiTJpf2ZcsYms4fERtE6Kwp5SFnxVXH8xIORkDNkId9liNUrA==@lists.linux.dev X-Gm-Message-State: AOJu0YyrISgtTIcMeF5ixkQr3xCqILPbPrhwWbZzfiofSohY3p/AFMvD EGIpkXXJsRqrS026+4FkpZbXtWxrZhGwMxU5bxgWImBfL8f6WrJhatZp X-Gm-Gg: AfdE7cn+5sbqMzBCzbFVZ06Ed8ZJMFgxdBb9xmsRpkpKCQwF09DNegQ90wJo1NFhit5 q0GsA4UHMmygIZap4yMzKTqinpLNjJyXVdadwGXDV1Yr8SlRDGM3oA4aQOn9rcLEGr34x9947OQ OSw+ltzphQDNjKiqNLs779v3YpSgn2UKfAqcBIFg+w7U8UR6fAPX3DNunpmtHQI8PXVJXEmQR2v zcY0R3KGdY/pWGQyytg+orJuBx4UMXDNVFgufDsiLqaKKl9PljD0hHsvo69NL0SNj0gD7yMhd7a Q5bkq3o9nrgpzrHUaVS1DnulBl+8ZRFlOHL/ej931zpsHS84S2G7x++Lwtdf/rrwSKV4vNdRevW LRxEfFGi4kNpgKDhHtq5M8UlhREe7v2VdqIsPpsx6sAIPc+yUFIYLXiiM6S123+iaeV/Rho7NLT sy1e5OZFAdFz2jFw== X-Received: by 2002:a05:6214:124a:b0:8a1:8b0a:6678 with SMTP id 6a1803df08f44-8de415cc13fmr219484556d6.31.1782078094430; Sun, 21 Jun 2026 14:41:34 -0700 (PDT) Received: from [172.17.0.2] ([138.28.231.64]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8df81cde9ecsm76274676d6.24.2026.06.21.14.41.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2026 14:41:34 -0700 (PDT) From: Yuanshen Cao Date: Sun, 21 Jun 2026 21:40:57 +0000 Subject: [PATCH v2 4/5] dt-bindings: dma: sun50i-a64-dma: Add allwinner,sun60i-a733-dma compatible string Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260621-sun60i-a733-dma-v2-4-340f205891cc@gmail.com> References: <20260621-sun60i-a733-dma-v2-0-340f205891cc@gmail.com> In-Reply-To: <20260621-sun60i-a733-dma-v2-0-340f205891cc@gmail.com> To: Vinod Koul , Frank Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: Yuanshen Cao , dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.15.2 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Add `allwinner,sun60i-a733-dma` to the list of compatible strings for the `sun50i-a64-dma` dtbinding documentation. While the A733 DMA controller shares many similarities with the sun50i-a64 DMA controller, it requires a specific configuration due to differences in: - Interrupt register layout and mapping. - Number of channels per interrupt register. - Support for higher (32G) address widths in LLI parameters. Signed-off-by: Yuanshen Cao Reviewed-by: Frank Li Acked-by: Conor Dooley --- Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml index c3e14eb6cfff..1cc3304b7414 100644 --- a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml +++ b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml @@ -25,6 +25,7 @@ properties: - allwinner,sun50i-a64-dma - allwinner,sun50i-a100-dma - allwinner,sun50i-h6-dma + - allwinner,sun60i-a733-dma - items: - const: allwinner,sun8i-r40-dma - const: allwinner,sun50i-a64-dma @@ -70,6 +71,7 @@ if: - allwinner,sun20i-d1-dma - allwinner,sun50i-a100-dma - allwinner,sun50i-h6-dma + - allwinner,sun60i-a733-dma then: properties: From patchwork Sun Jun 21 21:40:58 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuanshen Cao X-Patchwork-Id: 2455 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 826AE1C007A for ; Sun, 21 Jun 2026 23:45:31 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=gmail.com; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-23895-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; envelope-from=linux-sunxi+bounces-23895-noreply=patchwork.local@lists.linux.dev; helo=sea.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sea.lore.kernel.org (Postfix) with ESMTP id 7C029304B992 for ; Sun, 21 Jun 2026 21:41:41 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C2641371CE6; Sun, 21 Jun 2026 21:41:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gw3pDy45" X-Original-To: linux-sunxi@lists.linux.dev Received: from mail-qk1-f175.google.com (mail-qk1-f175.google.com [209.85.222.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D08D37188B for ; Sun, 21 Jun 2026 21:41:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.222.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782078098; cv=none; b=WD10UXB9CoCQa20V7Ud9UpHn5fv2DrVq9YZcapllPBRMT71zZjHE0xJci4KTglR5xRrqDRLGZDAbXBbWfhbuau96O150Lcgl8VR97SQdnAw5J8DVGC+mXQ4t00oPSzhTbwjL3JjNVYRMOz8d+vdvVLAgmnUyfV6J+qvdu5aYIc8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782078098; c=relaxed/simple; bh=18fWd7CDs9ATtKFp3tkSjs04Zj8nl/XFyKUyvkpg2Wg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SnNtEHB6DMY1IrYJbcTMvGdXOE5L/ib2BnCJ8bEzXV1b0liQy0vY9FDT+jakXR8PXJjyC8H9OyqDV/TS3k/qHcCghM+P9wnRJTwn5LyH+rhqBEgLjg1dL38hr9pU9x72+v+yu/eTYwqRMjx1gcBShiCyuSl6y/MuvaV7pX7Lhp8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=gw3pDy45; arc=none smtp.client-ip=209.85.222.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-qk1-f175.google.com with SMTP id af79cd13be357-9159da9bba5so279839085a.1 for ; Sun, 21 Jun 2026 14:41:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1782078096; x=1782682896; darn=lists.linux.dev; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=cUxclwCt1AeWLXTJW70zHjVOqZZDagaPH5nxyqxh7kU=; b=gw3pDy455Y5xErjFHfZ+9t05DqgOhwqcQTsQJ7+nIrqntuWSKxUm14l2NypePcDW4K 6cyXgkpFVuiAz90Mf2gVWop9n/XHjLx79z+aSnHAdlT42pKfWxnNHsbY5Ch++OuKPv1d bh/dUMtTH0Gsf1dLKj+4otyrxBGkNa6mTUGqSep2E20GcuFbQ2d/tXl+3cz76B60GuMv quvkVx0s871HbvbeDJmSPDtKYe/Uocizv81j7hi5ELxMosNaVTf5oUZ3meQVTYljO8wO wh2ctoaV19laMaZBXj+iOHOf6fZkeT7tMIYHhnkaJAN72Fj3JVQqgPNtg0LrpvvKrK14 qHEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782078096; x=1782682896; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=cUxclwCt1AeWLXTJW70zHjVOqZZDagaPH5nxyqxh7kU=; b=fU0QFyT4bugzVQS3MRYGFefF2wIgZVxR4gLW18o0lKCvoejoYDml6jimveQ0kD1Vv4 lhhaP3JwO/V+7xJwEAm3M0sPDZ691qyOHi4bL0T7n5q9k8rT3Wj0jpahQIyvCvNkw1o8 OVmUCfCG4BwMlN/xsCktKq/NWOU7qduvZ55V2Tf76rU8iur3K6Usjr4LgsoNR6HUBueh XZEEaY4lnJ+dldYXNsXzno6XTy4FkBFk/aIqiWxVnd4TyvbfTMDo5jOI9HvMVBBmjTo+ +DREeTpj/4NKGJpiE5wnSqxjGIVsfwMD9aPG5DMGGwCqI/TAqQE7DSqQ9+JegrpLzon2 K2Wg== X-Forwarded-Encrypted: i=1; AFNElJ8DLucUrNleeWwp+pFj8rJ0FBmlXzxfVW1F/yYzwIvoblCCmfPckkvhj4knNxckmL3UpOBN1+4mgPm3+Q==@lists.linux.dev X-Gm-Message-State: AOJu0YwkZ44au8UzRQqRS8/QS2YK6DJQItiHQG0LrvrKIe5x1cz7bNGN dyzJJJRV8Xk4KnN0uWs0LqFJD4cYS1+/9WasekyW/+/x7dtDKP+xuNuR X-Gm-Gg: AfdE7cmTDH1xeHTntq9o1cxhyPfp5VCxpVmT3DG1r/yrzVHZ5i6oTedpayJfNK6JqE7 YjRxxbEjB8S249anz4VX/Wrbefw7Qu8nePlK4MEaJSEkxjIuZAGwbO41mqWUVdv9ZHaytd79ED9 0h/bKwpyzJ9hoYZK5doU+egrvvK8Y/yaU2ALgNrv26ik0fePW8xYpNO9IDL+GxFdPXnXpdUVFFm y1bmu6AhwuL8FRO2tmPsNPnt+ytSqIfAU8UcZENUtWBMe89jdC46NFHpDAnq5cAIk+H69WlHPTC ItMfiJhVNrwYLXOmD/m58SLb9nz0qs0BaBPpVG2cHnyK80QI7Jjp4fjoXAHvbZYsjnzKtoiwWpY iciTrER9UlaRj6cPG/00csJ5qUgJSJDkiiQWJPo/xl0o3kgiEJMd+QhNaUs3NWc9e9NbUvDYRR1 hr4bp6Y5pPnkBWqA== X-Received: by 2002:a05:620a:28d2:b0:915:675d:a2d with SMTP id af79cd13be357-9208d7e7a14mr1998933585a.51.1782078095835; Sun, 21 Jun 2026 14:41:35 -0700 (PDT) Received: from [172.17.0.2] ([138.28.231.64]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8df81cde9ecsm76274676d6.24.2026.06.21.14.41.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2026 14:41:35 -0700 (PDT) From: Yuanshen Cao Date: Sun, 21 Jun 2026 21:40:58 +0000 Subject: [PATCH v2 5/5] dmaengine: sun6i-dma: Implement support for Allwinner A733 DMA controller Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260621-sun60i-a733-dma-v2-5-340f205891cc@gmail.com> References: <20260621-sun60i-a733-dma-v2-0-340f205891cc@gmail.com> In-Reply-To: <20260621-sun60i-a733-dma-v2-0-340f205891cc@gmail.com> To: Vinod Koul , Frank Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: Yuanshen Cao , dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.15.2 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= This patch implements the actual support for the Allwinner A733 DMA controller. It defines the new register offsets and bitfield mappings required for the A733, which slightly differs from the older `sun6i` series. Changes: - New register macros for A733 interrupt enable `DMA_IRQ_EN_A733` and status `DMA_IRQ_STAT_A733`. - New `SRC_HIGH_ADDR_32G` and `DST_HIGH_ADDR_32G` macro to handle the 32G high-address field in the LLI. - Implemented `sun6i_dma_set_addr_a733` and A733-specific interrupt register accessors. - Added `sun60i_a733_dma_config`, which ties all the refactored functionality together for this specific hardware. Signed-off-by: Yuanshen Cao --- drivers/dma/sun6i-dma.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index 196a0d73b221..4808015934cc 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -52,6 +52,15 @@ #define SUNXI_H3_SECURE_REG 0x20 #define SUNXI_H3_DMA_GATE 0x28 #define SUNXI_H3_DMA_GATE_ENABLE 0x4 + +/* + * sun60i specific registers + */ +#define DMA_IRQ_EN_A733(x) ((x) * 0x40 + 0x134) +#define DMA_IRQ_STAT_A733(x) ((x) * 0x40 + 0x138) + +#define DMA_IRQ_CHAN_NR_A733 1 + /* * Channels specific registers */ @@ -100,6 +109,8 @@ */ #define SRC_HIGH_ADDR(x) (((x) & 0x3U) << 16) #define DST_HIGH_ADDR(x) (((x) & 0x3U) << 18) +#define SRC_HIGH_ADDR_32G(x) (((x) & 0x7U) << 11) +#define DST_HIGH_ADDR_32G(x) (((x) & 0x7U) << 15) /* * Various hardware related defines @@ -257,6 +268,23 @@ static inline void sun6i_dma_dump_com_regs(struct sun6i_dma_dev *sdev) DMA_STAT, readl(sdev->base + DMA_STAT)); } +static inline void sun6i_dma_dump_com_regs_a733(struct sun6i_dma_dev *sdev) +{ + int i; + + for (i = 0; i < sdev->num_pchans / sdev->cfg->num_channels_per_reg; i++) { + dev_dbg(sdev->slave.dev, "Common register:\n" + "chan num %d\n" + "\tmask(%04x): 0x%08x\n" + "\tpend(%04x): 0x%08x\n" + "\tstats(%04x): 0x%08x\n", + i, + DMA_IRQ_EN_A733(i), readl(sdev->base + DMA_IRQ_EN_A733(i)), + DMA_IRQ_STAT_A733(i), readl(sdev->base + DMA_IRQ_STAT_A733(i)), + DMA_STAT, readl(sdev->base + DMA_STAT)); + } +} + static inline void sun6i_dma_dump_chan_regs(struct sun6i_dma_dev *sdev, struct sun6i_pchan *pchan) { @@ -360,21 +388,41 @@ static u32 sun6i_read_irq_en(struct sun6i_dma_dev *sdev, u32 irq_reg) return readl(sdev->base + DMA_IRQ_EN(irq_reg)); } +static u32 sun6i_read_irq_en_a733(struct sun6i_dma_dev *sdev, u32 irq_reg) +{ + return readl(sdev->base + DMA_IRQ_EN_A733(irq_reg)); +} + static void sun6i_write_irq_en(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 irq_val) { writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg)); } +static void sun6i_write_irq_en_a733(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 irq_val) +{ + writel(irq_val, sdev->base + DMA_IRQ_EN_A733(irq_reg)); +} + static u32 sun6i_read_irq_stat(struct sun6i_dma_dev *sdev, u32 irq_reg) { return readl(sdev->base + DMA_IRQ_STAT(irq_reg)); } +static u32 sun6i_read_irq_stat_a733(struct sun6i_dma_dev *sdev, u32 irq_reg) +{ + return readl(sdev->base + DMA_IRQ_STAT_A733(irq_reg)); +} + static void sun6i_write_irq_stat(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 status) { writel(status, sdev->base + DMA_IRQ_STAT(irq_reg)); } +static void sun6i_write_irq_stat_a733(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 status) +{ + writel(status, sdev->base + DMA_IRQ_STAT_A733(irq_reg)); +} + static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan) { struct sun6i_desc *txd = pchan->desc; @@ -695,6 +743,17 @@ static void sun6i_dma_set_addr_a100(struct sun6i_dma_dev *sdev, DST_HIGH_ADDR(upper_32_bits(dst)); } +static void sun6i_dma_set_addr_a733(struct sun6i_dma_dev *sdev, + struct sun6i_dma_lli *v_lli, + dma_addr_t src, dma_addr_t dst) +{ + v_lli->src = lower_32_bits(src); + v_lli->dst = lower_32_bits(dst); + + v_lli->para |= SRC_HIGH_ADDR_32G(upper_32_bits(src)) | + DST_HIGH_ADDR_32G(upper_32_bits(dst)); +} + static inline void sun6i_dma_set_addr(struct sun6i_dma_dev *sdev, struct sun6i_dma_lli *v_lli, dma_addr_t src, dma_addr_t dst) @@ -1339,6 +1398,33 @@ static struct sun6i_dma_config sun50i_h6_dma_cfg = { SUN6I_DMA_IRQ_A31_COMMON_OPS }; +/* + * The A733 binding uses the number of dma channels from the + * device tree node. + */ +static struct sun6i_dma_config sun60i_a733_dma_cfg = { + .clock_autogate_enable = sun6i_enable_clock_autogate_h3, + .set_burst_length = sun6i_set_burst_length_h3, + .set_drq = sun6i_set_drq_h6, + .set_mode = sun6i_set_mode_h6, + .set_addr = sun6i_dma_set_addr_a733, + .dump_com_regs = sun6i_dma_dump_com_regs_a733, + .read_irq_en = sun6i_read_irq_en_a733, + .write_irq_en = sun6i_write_irq_en_a733, + .read_irq_stat = sun6i_read_irq_stat_a733, + .write_irq_stat = sun6i_write_irq_stat_a733, + .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), + .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), + .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + .num_channels_per_reg = DMA_IRQ_CHAN_NR_A733, + .has_mbus_clk = true, +}; + /* * The V3s have only 8 physical channels, a maximum DRQ port id of 23, * and a total of 24 usable source and destination endpoints. @@ -1375,6 +1461,7 @@ static const struct of_device_id sun6i_dma_match[] = { { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg }, { .compatible = "allwinner,sun50i-a100-dma", .data = &sun50i_a100_dma_cfg }, { .compatible = "allwinner,sun50i-h6-dma", .data = &sun50i_h6_dma_cfg }, + { .compatible = "allwinner,sun60i-a733-dma", .data = &sun60i_a733_dma_cfg }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sun6i_dma_match);