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Sun, 21 Jun 2026 18:38:37 -0700 (PDT) From: Yuanshen Cao Date: Mon, 22 Jun 2026 01:36:23 +0000 Subject: [PATCH v3 1/5] dmaengine: sun6i-dma: Refactor to support A733 interrupt and register handling Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260622-sun60i-a733-dma-v3-1-f697ef296cbc@gmail.com> References: <20260622-sun60i-a733-dma-v3-0-f697ef296cbc@gmail.com> In-Reply-To: <20260622-sun60i-a733-dma-v3-0-f697ef296cbc@gmail.com> To: conor+dt@kernel.org, mripard@kernel.org, krzk+dt@kernel.org, robh@kernel.org, samuel@sholland.org, wens@kernel.org, jernej.skrabec@gmail.com, Frank.Li@kernel.org, vkoul@kernel.org Cc: Yuanshen Cao , dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Frank Li X-Mailer: b4 0.15.2 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-1.16 / 15.00]; BAYES_HAM(-5.50)[100.00%]; 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RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: D07811C0113 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Refactor to support the Allwinner A733 DMA controller. Currently, the `sun6i-dma` driver has several functions related to interrupt handling (reading/writing interrupt enable and status registers) and register dumping that are hardcoded. To support the A733, which has different register layouts and interrupt handling logic, these functions are being moved into the `sun6i_dma_config` structure as function pointers. This allows the driver to use a polymorphic approach where the specific implementation is determined by the hardware configuration assigned during device probing. Changes: - Added function pointers to `struct sun6i_dma_config` for: - `dump_com_regs` - `read_irq_en` - `write_irq_en` - `read_irq_stat` - `write_irq_stat` - Implemented generic `sun6i_read/write_irq_*` functions for existing hardware. - Added a macro and updated existing `sun6i_dma_config` instances (A31, A23, H3, A64, A100, H6, V3S) to use these new function pointers. Reviewed-by: Frank Li Signed-off-by: Yuanshen Cao --- drivers/dma/sun6i-dma.c | 50 ++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 45 insertions(+), 5 deletions(-) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index a9a254dbf8cb..ef3052c4ab36 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -138,6 +138,11 @@ struct sun6i_dma_config { void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst); void (*set_drq)(u32 *p_cfg, s8 src_drq, s8 dst_drq); void (*set_mode)(u32 *p_cfg, s8 src_mode, s8 dst_mode); + void (*dump_com_regs)(struct sun6i_dma_dev *sdev); + u32 (*read_irq_en)(struct sun6i_dma_dev *sdev, u32 irq_reg); + void (*write_irq_en)(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 irq_val); + u32 (*read_irq_stat)(struct sun6i_dma_dev *sdev, u32 irq_reg); + void (*write_irq_stat)(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 status); u32 src_burst_lengths; u32 dst_burst_lengths; u32 src_addr_widths; @@ -347,6 +352,26 @@ static void sun6i_set_mode_h6(u32 *p_cfg, s8 src_mode, s8 dst_mode) DMA_CHAN_CFG_DST_MODE_H6(dst_mode); } +static u32 sun6i_read_irq_en(struct sun6i_dma_dev *sdev, u32 irq_reg) +{ + return readl(sdev->base + DMA_IRQ_EN(irq_reg)); +} + +static void sun6i_write_irq_en(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 irq_val) +{ + writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg)); +} + +static u32 sun6i_read_irq_stat(struct sun6i_dma_dev *sdev, u32 irq_reg) +{ + return readl(sdev->base + DMA_IRQ_STAT(irq_reg)); +} + +static void sun6i_write_irq_stat(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 status) +{ + writel(status, sdev->base + DMA_IRQ_STAT(irq_reg)); +} + static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan) { struct sun6i_desc *txd = pchan->desc; @@ -460,16 +485,16 @@ static int sun6i_dma_start_desc(struct sun6i_vchan *vchan) vchan->irq_type = vchan->cyclic ? DMA_IRQ_PKG : DMA_IRQ_QUEUE; - irq_val = readl(sdev->base + DMA_IRQ_EN(irq_reg)); + irq_val = sdev->cfg->read_irq_en(sdev, irq_reg); irq_val &= ~((DMA_IRQ_HALF | DMA_IRQ_PKG | DMA_IRQ_QUEUE) << (irq_offset * DMA_IRQ_CHAN_WIDTH)); irq_val |= vchan->irq_type << (irq_offset * DMA_IRQ_CHAN_WIDTH); - writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg)); + sdev->cfg->write_irq_en(sdev, irq_reg, irq_val); writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR); writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE); - sun6i_dma_dump_com_regs(sdev); + sdev->cfg->dump_com_regs(sdev); sun6i_dma_dump_chan_regs(sdev, pchan); return 0; @@ -549,14 +574,14 @@ static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id) u32 status; for (i = 0; i < sdev->num_pchans / DMA_IRQ_CHAN_NR; i++) { - status = readl(sdev->base + DMA_IRQ_STAT(i)); + status = sdev->cfg->read_irq_stat(sdev, i); if (!status) continue; dev_dbg(sdev->slave.dev, "DMA irq status %s: 0x%x\n", str_high_low(i), status); - writel(status, sdev->base + DMA_IRQ_STAT(i)); + sdev->cfg->write_irq_stat(sdev, i, status); for (j = 0; (j < DMA_IRQ_CHAN_NR) && status; j++) { pchan = sdev->pchans + j; @@ -1101,6 +1126,13 @@ static inline void sun6i_dma_free(struct sun6i_dma_dev *sdev) } } +#define SUN6I_DMA_IRQ_A31_COMMON_OPS \ + .dump_com_regs = sun6i_dma_dump_com_regs, \ + .read_irq_en = sun6i_read_irq_en, \ + .write_irq_en = sun6i_write_irq_en, \ + .read_irq_stat = sun6i_read_irq_stat, \ + .write_irq_stat = sun6i_write_irq_stat, + /* * For A31: * @@ -1132,6 +1164,7 @@ static struct sun6i_dma_config sun6i_a31_dma_cfg = { .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_OPS }; /* @@ -1155,6 +1188,7 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = { .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_OPS }; static struct sun6i_dma_config sun8i_a83t_dma_cfg = { @@ -1173,6 +1207,7 @@ static struct sun6i_dma_config sun8i_a83t_dma_cfg = { .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_OPS }; /* @@ -1200,6 +1235,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_OPS }; /* @@ -1221,6 +1257,7 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_OPS }; /* @@ -1244,6 +1281,7 @@ static struct sun6i_dma_config sun50i_a100_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), .has_high_addr = true, .has_mbus_clk = true, + SUN6I_DMA_IRQ_A31_COMMON_OPS }; /* @@ -1266,6 +1304,7 @@ static struct sun6i_dma_config sun50i_h6_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), .has_mbus_clk = true, + SUN6I_DMA_IRQ_A31_COMMON_OPS }; /* @@ -1289,6 +1328,7 @@ static struct sun6i_dma_config sun8i_v3s_dma_cfg = { .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + SUN6I_DMA_IRQ_A31_COMMON_OPS }; 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Sun, 21 Jun 2026 18:38:39 -0700 (PDT) From: Yuanshen Cao Date: Mon, 22 Jun 2026 01:36:24 +0000 Subject: [PATCH v3 2/5] dmaengine: sun6i-dma: Add set_addr function pointer for variable address widths Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260622-sun60i-a733-dma-v3-2-f697ef296cbc@gmail.com> References: <20260622-sun60i-a733-dma-v3-0-f697ef296cbc@gmail.com> In-Reply-To: <20260622-sun60i-a733-dma-v3-0-f697ef296cbc@gmail.com> To: conor+dt@kernel.org, mripard@kernel.org, krzk+dt@kernel.org, robh@kernel.org, samuel@sholland.org, wens@kernel.org, jernej.skrabec@gmail.com, Frank.Li@kernel.org, vkoul@kernel.org Cc: Yuanshen Cao , dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Frank Li X-Mailer: b4 0.15.2 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The A733 DMA controller supports higher address (up to 32G) compared to previous generations. The existing `sun6i_dma_set_addr` function uses a hardcoded logic for setting the high-address bits in the LLI parameters. By moving `set_addr` into the `sun6i_dma_config` structure, we can provide specialized implementations for different hardware. This allows the A733 to use a version of `set_addr` that correctly handles its specific `SRC_HIGH_ADDR_32G` and `DST_HIGH_ADDR_32G` in the `set_addr` register later in the series. Changes: - Added `set_addr` function pointer to `struct sun6i_dma_config`. - Refactored `sun6i_dma_set_addr` and introduced `sun6i_dma_set_addr_a31/a100` (keeping the logic for previous generations). - Updated all existing configuration structs to include the new `set_addr` pointer. - Removed `has_high_addr` since the logic is replaced by `sun6i_dma_set_addr_a100`. Reviewed-by: Frank Li Signed-off-by: Yuanshen Cao --- drivers/dma/sun6i-dma.c | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index ef3052c4ab36..9984b9033cbb 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -112,6 +112,7 @@ /* forward declaration */ struct sun6i_dma_dev; +struct sun6i_dma_lli; /* * Hardware channels / ports representation @@ -138,6 +139,8 @@ struct sun6i_dma_config { void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst); void (*set_drq)(u32 *p_cfg, s8 src_drq, s8 dst_drq); void (*set_mode)(u32 *p_cfg, s8 src_mode, s8 dst_mode); + void (*set_addr)(struct sun6i_dma_dev *sdev, struct sun6i_dma_lli *v_lli, + dma_addr_t src, dma_addr_t dst); void (*dump_com_regs)(struct sun6i_dma_dev *sdev); u32 (*read_irq_en)(struct sun6i_dma_dev *sdev, u32 irq_reg); void (*write_irq_en)(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 irq_val); @@ -147,7 +150,6 @@ struct sun6i_dma_config { u32 dst_burst_lengths; u32 src_addr_widths; u32 dst_addr_widths; - bool has_high_addr; bool has_mbus_clk; }; @@ -673,16 +675,30 @@ static int set_config(struct sun6i_dma_dev *sdev, return 0; } -static inline void sun6i_dma_set_addr(struct sun6i_dma_dev *sdev, +static void sun6i_dma_set_addr_a31(struct sun6i_dma_dev *sdev, + struct sun6i_dma_lli *v_lli, + dma_addr_t src, dma_addr_t dst) +{ + v_lli->src = lower_32_bits(src); + v_lli->dst = lower_32_bits(dst); +} + +static void sun6i_dma_set_addr_a100(struct sun6i_dma_dev *sdev, struct sun6i_dma_lli *v_lli, dma_addr_t src, dma_addr_t dst) { v_lli->src = lower_32_bits(src); v_lli->dst = lower_32_bits(dst); - if (sdev->cfg->has_high_addr) - v_lli->para |= SRC_HIGH_ADDR(upper_32_bits(src)) | - DST_HIGH_ADDR(upper_32_bits(dst)); + v_lli->para |= SRC_HIGH_ADDR(upper_32_bits(src)) | + DST_HIGH_ADDR(upper_32_bits(dst)); +} + +static inline void sun6i_dma_set_addr(struct sun6i_dma_dev *sdev, + struct sun6i_dma_lli *v_lli, + dma_addr_t src, dma_addr_t dst) +{ + sdev->cfg->set_addr(sdev, v_lli, src, dst); } static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy( @@ -1156,6 +1172,7 @@ static struct sun6i_dma_config sun6i_a31_dma_cfg = { .set_burst_length = sun6i_set_burst_length_a31, .set_drq = sun6i_set_drq_a31, .set_mode = sun6i_set_mode_a31, + .set_addr = sun6i_dma_set_addr_a31, .src_burst_lengths = BIT(1) | BIT(8), .dst_burst_lengths = BIT(1) | BIT(8), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | @@ -1180,6 +1197,7 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = { .set_burst_length = sun6i_set_burst_length_a31, .set_drq = sun6i_set_drq_a31, .set_mode = sun6i_set_mode_a31, + .set_addr = sun6i_dma_set_addr_a31, .src_burst_lengths = BIT(1) | BIT(8), .dst_burst_lengths = BIT(1) | BIT(8), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | @@ -1199,6 +1217,7 @@ static struct sun6i_dma_config sun8i_a83t_dma_cfg = { .set_burst_length = sun6i_set_burst_length_a31, .set_drq = sun6i_set_drq_a31, .set_mode = sun6i_set_mode_a31, + .set_addr = sun6i_dma_set_addr_a31, .src_burst_lengths = BIT(1) | BIT(8), .dst_burst_lengths = BIT(1) | BIT(8), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | @@ -1225,6 +1244,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { .set_burst_length = sun6i_set_burst_length_h3, .set_drq = sun6i_set_drq_a31, .set_mode = sun6i_set_mode_a31, + .set_addr = sun6i_dma_set_addr_a31, .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | @@ -1247,6 +1267,7 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg = { .set_burst_length = sun6i_set_burst_length_h3, .set_drq = sun6i_set_drq_a31, .set_mode = sun6i_set_mode_a31, + .set_addr = sun6i_dma_set_addr_a31, .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | @@ -1269,6 +1290,7 @@ static struct sun6i_dma_config sun50i_a100_dma_cfg = { .set_burst_length = sun6i_set_burst_length_h3, .set_drq = sun6i_set_drq_h6, .set_mode = sun6i_set_mode_h6, + .set_addr = sun6i_dma_set_addr_a100, .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | @@ -1279,7 +1301,6 @@ static struct sun6i_dma_config sun50i_a100_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), - .has_high_addr = true, .has_mbus_clk = true, SUN6I_DMA_IRQ_A31_COMMON_OPS }; @@ -1293,6 +1314,7 @@ static struct sun6i_dma_config sun50i_h6_dma_cfg = { .set_burst_length = sun6i_set_burst_length_h3, .set_drq = sun6i_set_drq_h6, .set_mode = sun6i_set_mode_h6, + .set_addr = sun6i_dma_set_addr_a31, .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | @@ -1320,6 +1342,7 @@ static struct sun6i_dma_config sun8i_v3s_dma_cfg = { .set_burst_length = sun6i_set_burst_length_a31, .set_drq = sun6i_set_drq_a31, .set_mode = sun6i_set_mode_a31, + .set_addr = sun6i_dma_set_addr_a31, .src_burst_lengths = BIT(1) | BIT(8), .dst_burst_lengths = BIT(1) | BIT(8), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | From patchwork Mon Jun 22 01:36:25 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuanshen Cao X-Patchwork-Id: 2456 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sin.lore.kernel.org (sin.lore.kernel.org [104.64.211.4]) by mxe881.netcup.net (Postfix) with ESMTPS id 67E891C0113 for ; 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Sun, 21 Jun 2026 18:38:40 -0700 (PDT) Received: from [172.17.0.2] ([138.28.231.64]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51a098e287csm55778831cf.29.2026.06.21.18.38.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2026 18:38:40 -0700 (PDT) From: Yuanshen Cao Date: Mon, 22 Jun 2026 01:36:25 +0000 Subject: [PATCH v3 3/5] dmaengine: sun6i-dma: Add num_channels_per_reg for flexible interrupt mapping Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260622-sun60i-a733-dma-v3-3-f697ef296cbc@gmail.com> References: <20260622-sun60i-a733-dma-v3-0-f697ef296cbc@gmail.com> In-Reply-To: <20260622-sun60i-a733-dma-v3-0-f697ef296cbc@gmail.com> To: conor+dt@kernel.org, mripard@kernel.org, krzk+dt@kernel.org, robh@kernel.org, samuel@sholland.org, wens@kernel.org, jernej.skrabec@gmail.com, Frank.Li@kernel.org, vkoul@kernel.org Cc: Yuanshen Cao , dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Frank Li X-Mailer: b4 0.15.2 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The previous implementation of `sun6i-dma` had some implicit assumptions about the number of channels per interrupt register. Specifically, functions like `sun6i_kill_tasklet` were hardcoded to only disable interrupts for IRQ 0 and 1. `DMA_MAX_CHANNELS` is also not in used in the past, and the old SoCs never has more than 16 channels. The A733 has a different interrupt structure where the number of channels per register may differ. This patch introduces `num_channels_per_reg` to the `sun6i_dma_config`, similar to BSP, to make the interrupt handling logic hardware-agnostic. It also sets `DMA_MAX_CHANNELS` to 16 to align with the new BSP code and ensure loops over interrupts are correctly bounded. Changes: - Change `DMA_MAX_CHANNELS` definition to 16. - Added `num_channels_per_reg` to `struct sun6i_dma_config`. - Replaced hardcoded IRQ register calculations with values from `sdev->cfg->num_channels_per_reg`. - Updated `sun6i_kill_tasklet` to loop through all possible interrupt registers based on `DMA_MAX_CHANNELS` and the configuration. Reviewed-by: Frank Li Signed-off-by: Yuanshen Cao --- drivers/dma/sun6i-dma.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index 9984b9033cbb..196a0d73b221 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -41,7 +41,7 @@ #define DMA_STAT 0x30 /* Offset between DMA_IRQ_EN and DMA_IRQ_STAT limits number of channels */ -#define DMA_MAX_CHANNELS (DMA_IRQ_CHAN_NR * 0x10 / 4) +#define DMA_MAX_CHANNELS 16 /* * sun8i specific registers @@ -151,6 +151,7 @@ struct sun6i_dma_config { u32 src_addr_widths; u32 dst_addr_widths; bool has_mbus_clk; + u32 num_channels_per_reg; }; /* @@ -482,8 +483,8 @@ static int sun6i_dma_start_desc(struct sun6i_vchan *vchan) sun6i_dma_dump_lli(vchan, pchan->desc->v_lli, pchan->desc->p_lli); - irq_reg = pchan->idx / DMA_IRQ_CHAN_NR; - irq_offset = pchan->idx % DMA_IRQ_CHAN_NR; + irq_reg = pchan->idx / sdev->cfg->num_channels_per_reg; + irq_offset = pchan->idx % sdev->cfg->num_channels_per_reg; vchan->irq_type = vchan->cyclic ? DMA_IRQ_PKG : DMA_IRQ_QUEUE; @@ -575,7 +576,7 @@ static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id) int i, j, ret = IRQ_NONE; u32 status; - for (i = 0; i < sdev->num_pchans / DMA_IRQ_CHAN_NR; i++) { + for (i = 0; i < sdev->num_pchans / sdev->cfg->num_channels_per_reg; i++) { status = sdev->cfg->read_irq_stat(sdev, i); if (!status) continue; @@ -585,7 +586,7 @@ static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id) sdev->cfg->write_irq_stat(sdev, i, status); - for (j = 0; (j < DMA_IRQ_CHAN_NR) && status; j++) { + for (j = 0; (j < sdev->cfg->num_channels_per_reg) && status; j++) { pchan = sdev->pchans + j; vchan = pchan->vchan; if (vchan && (status & vchan->irq_type)) { @@ -1116,9 +1117,11 @@ static struct dma_chan *sun6i_dma_of_xlate(struct of_phandle_args *dma_spec, static inline void sun6i_kill_tasklet(struct sun6i_dma_dev *sdev) { + int i; + /* Disable all interrupts from DMA */ - writel(0, sdev->base + DMA_IRQ_EN(0)); - writel(0, sdev->base + DMA_IRQ_EN(1)); + for (i = 0; i < DMA_MAX_CHANNELS / sdev->cfg->num_channels_per_reg; i++) + sdev->cfg->write_irq_en(sdev, i, 0); /* Prevent spurious interrupts from scheduling the tasklet */ atomic_inc(&sdev->tasklet_shutdown); @@ -1181,6 +1184,7 @@ static struct sun6i_dma_config sun6i_a31_dma_cfg = { .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + .num_channels_per_reg = DMA_IRQ_CHAN_NR, SUN6I_DMA_IRQ_A31_COMMON_OPS }; @@ -1206,6 +1210,7 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = { .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + .num_channels_per_reg = DMA_IRQ_CHAN_NR, SUN6I_DMA_IRQ_A31_COMMON_OPS }; @@ -1226,6 +1231,7 @@ static struct sun6i_dma_config sun8i_a83t_dma_cfg = { .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + .num_channels_per_reg = DMA_IRQ_CHAN_NR, SUN6I_DMA_IRQ_A31_COMMON_OPS }; @@ -1255,6 +1261,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), + .num_channels_per_reg = DMA_IRQ_CHAN_NR, SUN6I_DMA_IRQ_A31_COMMON_OPS }; @@ -1278,6 +1285,7 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), + .num_channels_per_reg = DMA_IRQ_CHAN_NR, SUN6I_DMA_IRQ_A31_COMMON_OPS }; @@ -1301,6 +1309,7 @@ static struct sun6i_dma_config sun50i_a100_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), + .num_channels_per_reg = DMA_IRQ_CHAN_NR, .has_mbus_clk = true, SUN6I_DMA_IRQ_A31_COMMON_OPS }; @@ -1325,6 +1334,7 @@ static struct sun6i_dma_config sun50i_h6_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), + .num_channels_per_reg = DMA_IRQ_CHAN_NR, .has_mbus_clk = true, SUN6I_DMA_IRQ_A31_COMMON_OPS }; @@ -1351,6 +1361,7 @@ static struct sun6i_dma_config sun8i_v3s_dma_cfg = { .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + .num_channels_per_reg = DMA_IRQ_CHAN_NR, SUN6I_DMA_IRQ_A31_COMMON_OPS }; From patchwork Mon Jun 22 01:36:26 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuanshen Cao X-Patchwork-Id: 2460 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id D508B1C0113 for ; Mon, 22 Jun 2026 03:40:26 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=gmail.com; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-23911-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; 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Sun, 21 Jun 2026 18:38:42 -0700 (PDT) Received: from [172.17.0.2] ([138.28.231.64]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51a098e287csm55778831cf.29.2026.06.21.18.38.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2026 18:38:42 -0700 (PDT) From: Yuanshen Cao Date: Mon, 22 Jun 2026 01:36:26 +0000 Subject: [PATCH v3 4/5] dt-bindings: dmaengine: sun50i-a64-dma: Add allwinner,sun60i-a733-dma compatible string Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260622-sun60i-a733-dma-v3-4-f697ef296cbc@gmail.com> References: <20260622-sun60i-a733-dma-v3-0-f697ef296cbc@gmail.com> In-Reply-To: <20260622-sun60i-a733-dma-v3-0-f697ef296cbc@gmail.com> To: conor+dt@kernel.org, mripard@kernel.org, krzk+dt@kernel.org, robh@kernel.org, samuel@sholland.org, wens@kernel.org, jernej.skrabec@gmail.com, Frank.Li@kernel.org, vkoul@kernel.org Cc: Yuanshen Cao , dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Frank Li X-Mailer: b4 0.15.2 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Add `allwinner,sun60i-a733-dma` to the list of compatible strings for the `sun50i-a64-dma` dtbinding documentation. While the A733 DMA controller shares many similarities with the sun50i-a64 DMA controller, it requires a specific configuration due to differences in: - Interrupt register layout and mapping. - Number of channels per interrupt register. - Support for higher (32G) address widths in LLI parameters. Reviewed-by: Frank Li Signed-off-by: Yuanshen Cao Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml index c3e14eb6cfff..1cc3304b7414 100644 --- a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml +++ b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml @@ -25,6 +25,7 @@ properties: - allwinner,sun50i-a64-dma - allwinner,sun50i-a100-dma - allwinner,sun50i-h6-dma + - allwinner,sun60i-a733-dma - items: - const: allwinner,sun8i-r40-dma - const: allwinner,sun50i-a64-dma @@ -70,6 +71,7 @@ if: - allwinner,sun20i-d1-dma - allwinner,sun50i-a100-dma - allwinner,sun50i-h6-dma + - allwinner,sun60i-a733-dma then: properties: From patchwork Mon Jun 22 01:36:27 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuanshen Cao X-Patchwork-Id: 2459 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 80CC91C0113 for ; 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Sun, 21 Jun 2026 18:38:43 -0700 (PDT) Received: from [172.17.0.2] ([138.28.231.64]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-51a098e287csm55778831cf.29.2026.06.21.18.38.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2026 18:38:43 -0700 (PDT) From: Yuanshen Cao Date: Mon, 22 Jun 2026 01:36:27 +0000 Subject: [PATCH v3 5/5] dmaengine: sun6i-dma: Add support for Allwinner A733 DMA controller Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260622-sun60i-a733-dma-v3-5-f697ef296cbc@gmail.com> References: <20260622-sun60i-a733-dma-v3-0-f697ef296cbc@gmail.com> In-Reply-To: <20260622-sun60i-a733-dma-v3-0-f697ef296cbc@gmail.com> To: conor+dt@kernel.org, mripard@kernel.org, krzk+dt@kernel.org, robh@kernel.org, samuel@sholland.org, wens@kernel.org, jernej.skrabec@gmail.com, Frank.Li@kernel.org, vkoul@kernel.org Cc: Yuanshen Cao , dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-1.16 / 15.00]; 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ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 80CC91C0113 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Support Allwinner A733 DMA controller. Define new register offsets, bitfield mappings and dma_config required for the A733, which slightly differs from the older `sun6i` DMA controllers. Changes: - New register macros for A733 interrupt enable `DMA_IRQ_EN_A733`, status `DMA_IRQ_STAT_A733`, and channel count `DMA_IRQ_CHAN_NR_A733`. - New `SRC_HIGH_ADDR_32G` and `DST_HIGH_ADDR_32G` macro to handle the 32G high-address field in the LLI. - Implemented `sun6i_dma_set_addr_a733` and A733-specific interrupt register accessors. - Added `sun60i_a733_dma_cfg`, which ties all the refactored functionality together for this specific hardware. Signed-off-by: Yuanshen Cao Reviewed-by: Frank Li --- drivers/dma/sun6i-dma.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index 196a0d73b221..4808015934cc 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -52,6 +52,15 @@ #define SUNXI_H3_SECURE_REG 0x20 #define SUNXI_H3_DMA_GATE 0x28 #define SUNXI_H3_DMA_GATE_ENABLE 0x4 + +/* + * sun60i specific registers + */ +#define DMA_IRQ_EN_A733(x) ((x) * 0x40 + 0x134) +#define DMA_IRQ_STAT_A733(x) ((x) * 0x40 + 0x138) + +#define DMA_IRQ_CHAN_NR_A733 1 + /* * Channels specific registers */ @@ -100,6 +109,8 @@ */ #define SRC_HIGH_ADDR(x) (((x) & 0x3U) << 16) #define DST_HIGH_ADDR(x) (((x) & 0x3U) << 18) +#define SRC_HIGH_ADDR_32G(x) (((x) & 0x7U) << 11) +#define DST_HIGH_ADDR_32G(x) (((x) & 0x7U) << 15) /* * Various hardware related defines @@ -257,6 +268,23 @@ static inline void sun6i_dma_dump_com_regs(struct sun6i_dma_dev *sdev) DMA_STAT, readl(sdev->base + DMA_STAT)); } +static inline void sun6i_dma_dump_com_regs_a733(struct sun6i_dma_dev *sdev) +{ + int i; + + for (i = 0; i < sdev->num_pchans / sdev->cfg->num_channels_per_reg; i++) { + dev_dbg(sdev->slave.dev, "Common register:\n" + "chan num %d\n" + "\tmask(%04x): 0x%08x\n" + "\tpend(%04x): 0x%08x\n" + "\tstats(%04x): 0x%08x\n", + i, + DMA_IRQ_EN_A733(i), readl(sdev->base + DMA_IRQ_EN_A733(i)), + DMA_IRQ_STAT_A733(i), readl(sdev->base + DMA_IRQ_STAT_A733(i)), + DMA_STAT, readl(sdev->base + DMA_STAT)); + } +} + static inline void sun6i_dma_dump_chan_regs(struct sun6i_dma_dev *sdev, struct sun6i_pchan *pchan) { @@ -360,21 +388,41 @@ static u32 sun6i_read_irq_en(struct sun6i_dma_dev *sdev, u32 irq_reg) return readl(sdev->base + DMA_IRQ_EN(irq_reg)); } +static u32 sun6i_read_irq_en_a733(struct sun6i_dma_dev *sdev, u32 irq_reg) +{ + return readl(sdev->base + DMA_IRQ_EN_A733(irq_reg)); +} + static void sun6i_write_irq_en(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 irq_val) { writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg)); } +static void sun6i_write_irq_en_a733(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 irq_val) +{ + writel(irq_val, sdev->base + DMA_IRQ_EN_A733(irq_reg)); +} + static u32 sun6i_read_irq_stat(struct sun6i_dma_dev *sdev, u32 irq_reg) { return readl(sdev->base + DMA_IRQ_STAT(irq_reg)); } +static u32 sun6i_read_irq_stat_a733(struct sun6i_dma_dev *sdev, u32 irq_reg) +{ + return readl(sdev->base + DMA_IRQ_STAT_A733(irq_reg)); +} + static void sun6i_write_irq_stat(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 status) { writel(status, sdev->base + DMA_IRQ_STAT(irq_reg)); } +static void sun6i_write_irq_stat_a733(struct sun6i_dma_dev *sdev, u32 irq_reg, u32 status) +{ + writel(status, sdev->base + DMA_IRQ_STAT_A733(irq_reg)); +} + static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan) { struct sun6i_desc *txd = pchan->desc; @@ -695,6 +743,17 @@ static void sun6i_dma_set_addr_a100(struct sun6i_dma_dev *sdev, DST_HIGH_ADDR(upper_32_bits(dst)); } +static void sun6i_dma_set_addr_a733(struct sun6i_dma_dev *sdev, + struct sun6i_dma_lli *v_lli, + dma_addr_t src, dma_addr_t dst) +{ + v_lli->src = lower_32_bits(src); + v_lli->dst = lower_32_bits(dst); + + v_lli->para |= SRC_HIGH_ADDR_32G(upper_32_bits(src)) | + DST_HIGH_ADDR_32G(upper_32_bits(dst)); +} + static inline void sun6i_dma_set_addr(struct sun6i_dma_dev *sdev, struct sun6i_dma_lli *v_lli, dma_addr_t src, dma_addr_t dst) @@ -1339,6 +1398,33 @@ static struct sun6i_dma_config sun50i_h6_dma_cfg = { SUN6I_DMA_IRQ_A31_COMMON_OPS }; +/* + * The A733 binding uses the number of dma channels from the + * device tree node. + */ +static struct sun6i_dma_config sun60i_a733_dma_cfg = { + .clock_autogate_enable = sun6i_enable_clock_autogate_h3, + .set_burst_length = sun6i_set_burst_length_h3, + .set_drq = sun6i_set_drq_h6, + .set_mode = sun6i_set_mode_h6, + .set_addr = sun6i_dma_set_addr_a733, + .dump_com_regs = sun6i_dma_dump_com_regs_a733, + .read_irq_en = sun6i_read_irq_en_a733, + .write_irq_en = sun6i_write_irq_en_a733, + .read_irq_stat = sun6i_read_irq_stat_a733, + .write_irq_stat = sun6i_write_irq_stat_a733, + .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), + .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), + .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), + .num_channels_per_reg = DMA_IRQ_CHAN_NR_A733, + .has_mbus_clk = true, +}; + /* * The V3s have only 8 physical channels, a maximum DRQ port id of 23, * and a total of 24 usable source and destination endpoints. @@ -1375,6 +1461,7 @@ static const struct of_device_id sun6i_dma_match[] = { { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg }, { .compatible = "allwinner,sun50i-a100-dma", .data = &sun50i_a100_dma_cfg }, { .compatible = "allwinner,sun50i-h6-dma", .data = &sun50i_h6_dma_cfg }, + { .compatible = "allwinner,sun60i-a733-dma", .data = &sun60i_a733_dma_cfg }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sun6i_dma_match);