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b=Fy4QgNpwpJYAjbCaQMQQLlYhgSiNB5utT8w+awwJFJt9wtfdbMQUOljiJ/2ztsXkn fdie5Cr0Zmg+tJr54o4le96ekNTKGDvatDl0QcEYQJsgcqDjv3oDNQzRYCkzz8/ex6 FwmzLiXlXL4F9OXwTvUcX9IDS2DmFEY4kyinAQFU= X-QQ-mid: esmtpgz13t1783330553tb007279a X-QQ-Originating-IP: pFwwsK+bFgjr+sBuJ3tvvVI0IHeKzOu5y//TagiDwvs= Received: from PEN202512010004 ( [113.57.152.160]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 06 Jul 2026 17:35:51 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 1 X-BIZMAIL-ID: 17558151343560022495 EX-QQ-RecipientCnt: 12 From: raoxu To: vkoul@kernel.org Cc: wens@kernel.org, jernej.skrabec@gmail.com, samuel@sholland.org, neil.armstrong@linaro.org, andre.przywara@arm.com, raoxu@uniontech.com, marco.crivellari@suse.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH] phy: allwinner: sun4i-usb: disable the PHY2 PMU clock after SIDDQ setup Date: Mon, 6 Jul 2026 17:35:49 +0800 Message-ID: <1368E4E3485E881C+20260706093549.867442-1-raoxu@uniontech.com> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:uniontech.com:qybglogicsvrgz:qybglogicsvrgz6b-0 X-QQ-XMAILINFO: Nb41GHfx0X4XTL3TPXxkavFYJKt5wzl/hNPTEllmLgYKBmlRcdqjiCnQ upfmTN9JiW9gplgKuq13SbpzVTX9Xf0lgo7QsUGdS1efsEqzT1cEaE5/W9o+8sGyqBcfluM ESaZ3hOwcD5UW2zCC9HoKc8ZmPRiDJBtYhOv2rJkh28G4qi8DZT27F8blfrkhtjC/dDfdWV a8mH5jD3Z2+KtrLzVpBSGLml6dDytyapcZ2v7gsqXoqHOc8B3JT4TwmBiTGuulFZdTtikt7 5n0GExWOObYUiMli5h3zUi2Ym/YhxZI4ElSSeYBXts2fxlspOEqGwLnjVR0eyrEgxKRO5+d T56GlpHLmVJZwGvyV3vx8cD3Gig9jr5KBQ7rI8tWB/j/gqx1M8zaZUZqOPW4qZwQIRJmD3y YiP2P7hLLLhtU9qFPZPTLi4DuXl2X6H0Ol2ZuZJHmCUoOVB/0sn0jZV08zBFlGBmIm8zOzO 8cwgJV4ZFLCg0Si06PYMlsLjo6BInvMTTbr9ZWxHMdgfwd2Vbw0dexvew8q67RHQoPXR9+1 JOEAeTyOH6+NJsnrfX3iMcO/HaQC/3+ml1SP88ZQPynsJ6UioS3jPsSTmYXpwErm1e/KU0t 7dBw/WYhSZMZkHIOx5Ue/ggdU6kFO1ehtijpsweDkDH7i55sgV072NhNBaSEUzEXaN/eg81 sIClMCX6DT9vpRBKz5RU9nP8fjcIopL2qYAmPmd8vWK2QR0C1kf2P7TteI8f+5Jyw3ZOryo kpeL7Giz5vlHWDvNncrWmCsRpzaUwEluFq7pR70UFAcf5MjAS0+PCxwiyDSIIBQq2pBiOYU 7eFmp5FYySfHx2CXsgmWhvetzjqhJPRwzhYDhuAfTgh6yPEi8kZaD7vXCEE5cau6jGRzpbk OugVx/vaMxleBMzqs6iaOnazWG9YxRZrYzpcBqB+eehhJwOsbdPtWdyNBh0Yn3wWGq5ddYQ fDXDa8PiUThG+luanYwJq9eBJ1drP3HtHx8ZDdisP+pOWgUBzWN/PtgzhqRdvm7tMMRb/Md Qk19aK5Y094ztLIrmL9cGPUFjkmrEhM3doxbmN6zrgShNBgfOnGfLD1rifijcHk2pQSdTuT YSz7fXvJA0N X-QQ-XMRINFO: OWPUhxQsoeAVwkVaQIEGSKwwgKCxK/fD5g== X-QQ-RECHKSPAM: 0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-0.66 / 15.00]; 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RCVD_TLS_LAST(0.00)[]; TAGGED_FROM(0.00)[bounces-24215-noreply=patchwork.local]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; R_SPF_ALLOW(0.00)[+ip4:172.234.253.10:c] X-Rspamd-Queue-Id: 7D98A1C0790 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= From: Xu Rao sun4i_usb_phy_init() temporarily enables PHY2's clk2 when a SoC needs PHY2 SIDDQ setup while initializing another PHY. However, after updating PHY2's PMU register it disables the clk2 pointer from the PHY currently being initialized. This leaves PHY2's clk2 enabled and also drops an extra reference from the current PHY's clk2, causing the prepare/enable accounting to become unbalanced. Disable the same PHY2 clk2 that was enabled for the auxiliary PMU access. Signed-off-by: Xu Rao --- drivers/phy/allwinner/phy-sun4i-usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.50.1 diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index e2fbf8ccf99e..839856c09e30 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -318,7 +318,7 @@ static int sun4i_usb_phy_init(struct phy *_phy) writel(val, phy2->pmu + REG_HCI_PHY_CTL); } - clk_disable_unprepare(phy->clk2); + clk_disable_unprepare(phy2->clk2); } if (phy->pmu && data->cfg->hci_phy_ctl_clear) {