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Wed, 22 Jul 2026 13:33:58 -0700 (PDT) Received: from coolemuke.fritz.box ([2a00:6020:b320:1a00:c256:1463:a40b:d8c6]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4956ab2f0a2sm63134945e9.1.2026.07.22.13.33.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2026 13:33:58 -0700 (PDT) From: " =?utf-8?q?S=C3=B6ren_Hantel?= " X-Google-Original-From: =?utf-8?q?S=C3=B6ren_Hantel?= To: linux-pm@vger.kernel.org Cc: Vasily Khoruzhick , Yangtao Li , "Rafael J . Wysocki" , Daniel Lezcano , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Rossak , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, =?utf-8?q?S=C3=B6ren_Hantel?= , Claude Fable 5 Subject: [PATCH 1/3] dt-bindings: thermal: sun8i: Add binding for the A80 THS controller Date: Wed, 22 Jul 2026 22:33:39 +0200 Message-ID: <20260722203341.2917852-2-fugininsane@googlemail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260722203341.2917852-1-fugininsane@googlemail.com> References: <20260722203341.2917852-1-fugininsane@googlemail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-1.16 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.234.253.10:from]; SUSPICIOUS_RECIPS(1.50)[]; DMARC_POLICY_SOFTFAIL(1.00)[gmail.com : SPF not aligned (relaxed), No valid DKIM,none]; MAILLIST(-0.15)[generic]; MIME_GOOD(-0.10)[text/plain]; BAD_REP_POLICIES(0.10)[]; HAS_LIST_UNSUB(-0.01)[]; RCPT_COUNT_TWELVE(0.00)[18]; TAGGED_RCPT(0.00)[dt]; DBL_BLOCKED_OPENRESOLVER(0.00)[anthropic.com:email,sea.lore.kernel.org:rdns,sea.lore.kernel.org:helo]; TO_DN_SOME(0.00)[]; FUZZY_BLOCKED(0.00)[rspamd.com]; FORGED_SENDER_MAILLIST(0.00)[]; FREEMAIL_CC(0.00)[gmail.com,kernel.org,sholland.org,vger.kernel.org,lists.infradead.org,lists.linux.dev,googlemail.com,anthropic.com]; R_SPF_ALLOW(0.00)[+ip4:172.234.253.10]; PRECEDENCE_BULK(0.00)[]; FREEMAIL_FROM(0.00)[gmail.com]; RCVD_TLS_LAST(0.00)[]; MIME_TRACE(0.00)[0:+]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; FROM_HAS_DN(0.00)[]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; TAGGED_FROM(0.00)[bounces-24619-noreply=patchwork.local]; RCVD_COUNT_FIVE(0.00)[6]; FROM_NEQ_ENVFROM(0.00)[fugininsane@gmail.com,linux-sunxi@lists.linux.dev]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 037091C2C6B X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The Allwinner A80 has a thermal sensor with four channels which shares its MMIO block, bus gate, module clock and reset line with the GPADC. Register-wise it is an early version of the THS found in the A83T and later SoCs, with the THS registers starting at offset 0x40 of the shared block. Add the compatible to the sun8i THS binding. The A80 takes a bus and a module clock plus a reset line, so the existing conditionals already describe it correctly. Co-authored-by: Claude Fable 5 Signed-off-by: Sören Hantel --- .../devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml index 3e61689..718c44d 100644 --- a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml +++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml @@ -18,6 +18,7 @@ properties: - allwinner,sun8i-a83t-ths - allwinner,sun8i-h3-ths - allwinner,sun8i-r40-ths + - allwinner,sun9i-a80-ths - allwinner,sun20i-d1-ths - allwinner,sun50i-a64-ths - allwinner,sun50i-a100-ths From patchwork Wed Jul 22 20:33:40 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?S=C3=B6ren_Hantel?= X-Patchwork-Id: 2721 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 5FDC51C0BC9 for ; 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Wed, 22 Jul 2026 13:34:00 -0700 (PDT) Received: from coolemuke.fritz.box ([2a00:6020:b320:1a00:c256:1463:a40b:d8c6]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4956ab2f0a2sm63134945e9.1.2026.07.22.13.33.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2026 13:33:59 -0700 (PDT) From: " =?utf-8?q?S=C3=B6ren_Hantel?= " X-Google-Original-From: =?utf-8?q?S=C3=B6ren_Hantel?= To: linux-pm@vger.kernel.org Cc: Vasily Khoruzhick , Yangtao Li , "Rafael J . Wysocki" , Daniel Lezcano , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Rossak , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, =?utf-8?q?S=C3=B6ren_Hantel?= , Claude Fable 5 Subject: [PATCH 2/3] thermal/drivers/sun8i: Add support for the A80 THS Date: Wed, 22 Jul 2026 22:33:40 +0200 Message-ID: <20260722203341.2917852-3-fugininsane@googlemail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260722203341.2917852-1-fugininsane@googlemail.com> References: <20260722203341.2917852-1-fugininsane@googlemail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The Allwinner A80 thermal sensor is an early relative of the THS found in the A83T and later SoCs. It shares its register block, bus gate, 4 MHz module clock and reset line with the GPADC; the THS registers live at offset 0x40 of the shared block, with four data registers for the four sensors (0: big cluster, 1: DRAM, 2: GPU, 3: little cluster). Register layout, initialization values and the temperature formula (T = 190 - raw * 1000 / 14543, i.e. offset 190000 / scale 688 in this driver's convention) are taken from the vendor BSP kernel. The init sequence also programs the hardware alarm (~90 degC) and emergency shutdown (~105 degC) thresholds the BSP uses, since their reset defaults are undefined. Unlike on later SoCs the data-ready interrupt fires at the conversion rate (tens of kHz), so it is left disabled and the thermal core polls the sensors; the interrupt line only serves the alarm and shutdown events, matching the vendor BSP behaviour. The A80 SID is not yet supported by the sunxi nvmem driver, so calibration data is currently unavailable and the driver falls back to the defaults, which yield plausible results (idle temperatures around 40 degC, full-load peaks in the mid 50s on a Cubieboard4). Tested on a Cubietech Cubieboard4: all four zones report load-reactive temperatures via polling. Co-authored-by: Claude Fable 5 Signed-off-by: Sören Hantel --- drivers/thermal/sun8i_thermal.c | 93 ++++++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c index 2267479..3e7bfda 100644 --- a/drivers/thermal/sun8i_thermal.c +++ b/drivers/thermal/sun8i_thermal.c @@ -65,8 +65,27 @@ struct tsensor { int id; }; +/* + * The A80 thermal sensor shares its register block with the GPADC. + * The THS registers start at offset 0x40 within that block. + */ +#define SUN9I_THS_CTRL 0x40 +#define SUN9I_THS_IC 0x44 +#define SUN9I_THS_IS 0x48 +#define SUN9I_THS_ALARM_TH(x) (0x50 + (x) * 0x4) +#define SUN9I_THS_SHUT_TH(x) (0x60 + (x) * 0x4) +#define SUN9I_THS_MFC 0x70 +#define SUN9I_THS_TEMP_DATA 0x80 +#define SUN9I_THS_CTRL_ACQ(x) ((x) << 16) +#define SUN9I_THS_CTRL_SENSOR_EN GENMASK(3, 0) +#define SUN9I_THS_ALARM_IRQ_EN GENMASK(3, 0) +#define SUN9I_THS_SHUT_IRQ_EN GENMASK(7, 4) +#define SUN9I_THS_ALARM_IRQ_STS(x) BIT(x) +#define SUN9I_THS_SHUT_IRQ_STS(x) BIT(4 + (x)) + struct ths_thermal_chip { bool has_mod_clk; + unsigned long mod_clk_rate; bool has_bus_clk_reset; bool needs_sram; int sensor_num; @@ -413,7 +432,8 @@ static int sun8i_ths_resource_init(struct ths_device *tmdev) return PTR_ERR(tmdev->mod_clk); } - ret = clk_set_rate(tmdev->mod_clk, 24000000); + ret = clk_set_rate(tmdev->mod_clk, tmdev->chip->mod_clk_rate ?: + 24000000); if (ret) return ret; @@ -596,6 +616,76 @@ static int sun8i_ths_probe(struct platform_device *pdev) return 0; } +static int sun9i_a80_thermal_init(struct ths_device *tmdev) +{ + int i; + + /* clear any pending interrupt status */ + regmap_write(tmdev->regmap, SUN9I_THS_IS, 0xfff); + /* set up the median filter, average over 8 samples */ + regmap_write(tmdev->regmap, SUN9I_THS_MFC, 0x5); + + /* + * Program the protection thresholds with the values the vendor + * BSP uses (thresholds are in raw sensor units, which decrease + * with rising temperature): an alarm interrupt at ~90 degC and + * an emergency hardware shutdown at ~105 degC. + */ + for (i = 0; i < tmdev->chip->sensor_num; i++) { + regmap_write(tmdev->regmap, SUN9I_THS_ALARM_TH(i), + (1454 << 16) | 0xfff); + regmap_write(tmdev->regmap, SUN9I_THS_SHUT_TH(i), + (1231 << 16) | 0xfff); + } + + /* + * Unlike on later SoCs, the data-ready interrupt fires at the + * conversion rate (tens of kHz), so leave it disabled and let the + * thermal core poll the data registers; the interrupt line only + * serves the alarm and shutdown events, like in the vendor BSP. + */ + regmap_write(tmdev->regmap, SUN9I_THS_IC, + SUN9I_THS_ALARM_IRQ_EN | SUN9I_THS_SHUT_IRQ_EN); + /* acquire time 0x2f, enable all four sensors */ + regmap_write(tmdev->regmap, SUN9I_THS_CTRL, + SUN9I_THS_CTRL_ACQ(0x2f) | SUN9I_THS_CTRL_SENSOR_EN); + + return 0; +} + +static unsigned long sun9i_a80_irq_ack(struct ths_device *tmdev) +{ + unsigned long irq_bitmap = 0; + int i, state; + + regmap_read(tmdev->regmap, SUN9I_THS_IS, &state); + + for (i = 0; i < MAX_SENSOR_NUM; i++) { + if (state & (SUN9I_THS_ALARM_IRQ_STS(i) | + SUN9I_THS_SHUT_IRQ_STS(i))) { + regmap_write(tmdev->regmap, SUN9I_THS_IS, + state & (SUN9I_THS_ALARM_IRQ_STS(i) | + SUN9I_THS_SHUT_IRQ_STS(i))); + set_bit(i, &irq_bitmap); + } + } + + return irq_bitmap; +} + +static const struct ths_thermal_chip sun9i_a80_ths = { + .sensor_num = 4, + .has_mod_clk = true, + .mod_clk_rate = 4000000, + .has_bus_clk_reset = true, + .scale = 688, + .offset = 190000, + .temp_data_base = SUN9I_THS_TEMP_DATA, + .init = sun9i_a80_thermal_init, + .irq_ack = sun9i_a80_irq_ack, + .calc_temp = sun8i_ths_calc_temp, +}; + static const struct ths_thermal_chip sun8i_a83t_ths = { .sensor_num = 3, .scale = 705, @@ -711,6 +801,7 @@ static const struct ths_thermal_chip sun50i_h616_ths = { static const struct of_device_id of_ths_match[] = { { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths }, + { .compatible = "allwinner,sun9i-a80-ths", .data = &sun9i_a80_ths }, { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths }, { .compatible = "allwinner,sun8i-r40-ths", .data = &sun8i_r40_ths }, { .compatible = "allwinner,sun50i-a64-ths", .data = &sun50i_a64_ths }, From patchwork Wed Jul 22 20:33:41 2026 Content-Type: text/plain; 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Wed, 22 Jul 2026 13:34:02 -0700 (PDT) Received: from coolemuke.fritz.box ([2a00:6020:b320:1a00:c256:1463:a40b:d8c6]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4956ab2f0a2sm63134945e9.1.2026.07.22.13.34.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2026 13:34:00 -0700 (PDT) From: " =?utf-8?q?S=C3=B6ren_Hantel?= " X-Google-Original-From: =?utf-8?q?S=C3=B6ren_Hantel?= To: linux-pm@vger.kernel.org Cc: Vasily Khoruzhick , Yangtao Li , "Rafael J . Wysocki" , Daniel Lezcano , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Rossak , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Claude Fable 5 , =?utf-8?q?S=C3=B6ren_Hantel?= Subject: [PATCH 3/3] ARM: dts: sun9i-a80: Add thermal sensor and thermal zones Date: Wed, 22 Jul 2026 22:33:41 +0200 Message-ID: <20260722203341.2917852-4-fugininsane@googlemail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260722203341.2917852-1-fugininsane@googlemail.com> References: <20260722203341.2917852-1-fugininsane@googlemail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= From: Philipp Rossak Now that the A80 thermal sensor is supported, add its device node and the thermal zones to the device tree. The clocks and the resets are shared between the GPADC and the THS sensor. Sensor 0 is located beside the big CPU cluster, sensor 1 beside the DRAM controller, sensor 2 beside the GPU and sensor 3 beside the little CPU cluster. Signed-off-by: Philipp Rossak [soeren: rebased from the 2018 series, fixed the interrupt number (SPI 115 as in the vendor BSP; verified on hardware - SPI 31 stays silent), added critical trip points matching the driver's emergency shutdown threshold] Co-authored-by: Claude Fable 5 Signed-off-by: Sören Hantel --- arch/arm/boot/dts/allwinner/sun9i-a80.dtsi | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi index a1ae092..8e7f8cd 100644 --- a/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi @@ -941,6 +941,16 @@ #reset-cells = <1>; }; + ths: thermal-sensor@6004c00 { + compatible = "allwinner,sun9i-a80-ths"; + reg = <0x06004c00 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_GPADC>, <&ccu CLK_GPADC>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_GPADC>; + #thermal-sensor-cells = <1>; + }; + timer@6000c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x06000c00 0xa0>; @@ -1250,4 +1260,62 @@ #size-cells = <0>; }; }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&ths 0>; + + trips { + cpu0_crit: cpu0-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + dram_thermal: dram-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&ths 1>; + + trips { + dram_crit: dram-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&ths 2>; + + trips { + gpu_crit: gpu-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu2_thermal: cpu2-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&ths 3>; + + trips { + cpu2_crit: cpu2-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; };