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b=Icyn6c8yhdHQAlx4W0szQLanIZtkiDmin71gdpSPyrvseqstoBx/3lutSSjhE90S8 GZbfZ2S1RauSutzc7fuyy5YGfq5Aj2ebY5wBgKQKKdyHSc//gthF2A4QW62oNaZoYe VkdeR+IUVzzcuvVy3vbpHo70JmH2RByS/iRVgOVg= X-QQ-mid: esmtpgz12t1786626355t9ca26cba X-QQ-Originating-IP: dHhI7VBaezRAp4X4gI1x1FX2IMsrpI09Qjr/PigbalE= Received: from PEN202512010004 ( [113.57.152.160]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 13 Aug 2026 21:05:53 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 1 X-BIZMAIL-ID: 588101152483150386 EX-QQ-RecipientCnt: 12 From: raoxu To: vkoul@kernel.org Cc: wens@kernel.org, jernej.skrabec@gmail.com, samuel@sholland.org, neil.armstrong@linaro.org, andre.przywara@arm.com, marco.crivellari@suse.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, raoxu@uniontech.com Subject: [PATCH v2] phy: allwinner: sun4i-usb: disable the PHY2 PMU clock after SIDDQ setup Date: Thu, 13 Aug 2026 21:05:42 +0800 Message-ID: X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:uniontech.com:qybglogicsvrgz:qybglogicsvrgz6b-0 X-QQ-XMAILINFO: MvyKdZyVtFx3ogxxWRGDkb3wjkVowJkMY7zgE3kzwgOz3wTrVGElr46w 3Stlq7ADwX6crnNIfcueySAkOPttnBR3+N0tWSpJ+Hf8bILjwodltDfDMAys3dpWJ5A2Sr/ kzkC6/fws1aw9SZgCdts4gEKQNjSQ/VxciLKeYWzg+FkQbef38BKrY/8HtMgagSH+DyDaUC A3Az1uhdWcVii3UHm8GHeDCcFLwNUyz/B4aQkA78dbQl4j/8x49oy4H08kvKj6Nd7xIS8tS qhHF9mujbFd8JKTe1XDICdF27ULL1pE/p1xIgDtH5qoNkzHU2V2TES9Z6dV9f+skkLfuN9x E/c5PvOI3Y8rByc1gcS6U98anIjR8ToinuSCtecagKaM3CR7ra+CAR7ALMctB57Qe08oKB1 Cj6uh7xNk+RUl9cxw9xqwEp1Oq6nB7864/6o/fZ5g7Etfj68ZmNLjSM+LtaegcmJ/V2a+Wh Aos1SVlPZ3t3JubC8C5c06YAN59cXkmyfRM6ZajPi94c5xnqkVx5N0XWN9TGZ99AMvaD7be B0IBl4Wnev9FLc6rWF9IvEVYq+jIslNiR1WENa0ClGt1/hHImu/ZCv706b5Iko4znp6AMdK rJagUlF24IeEriPsfY+Nm9MmFjax2O3oWZiRCOCK/sQsrMJpdI9phgMbTEPY9xnv1fItS06 69hyGvKKHqeK9RIspeXqEOTiWQs2UDZjlqmme1KWokWX2TZhgKeGcYhryy78+Q5k5PfTYDg GzIZ7J9SU0/vNnZxzD6W625AV0NmYmsKlWBoGnTv/sPZk0No5biElFnueUOT4UCnuF26Weu 8ZB8oXUqEOkdQZU6hy6ZwAjgrDR/uccHiJSjrbYbpHuotLsCbhiFDlUJ+eFBLi8UfkZnL+g 2zL+8mTfbRoNvcc2PTbYQXLNIVEuj8Go9gAVuhA5amJLYWNLnJhLQDurUBtG2vuBa0m7AA6 F+jBCXCms9N2koilwDDuDkL4a3rHLRUXNQg2Qjw2y3EKz5PizeTUUzS/4FnOygjZalRCwll ErQo+qK/vGO565+9eNg1UZ3aWlVkQL9HVdGs50bMUHehIe1YdTDrq0TmOjySWE9Hdu8xA4z w== X-QQ-XMRINFO: NS+P29fieYNwqS3WCnRCOn9D1NpZuCnCRA== X-QQ-RECHKSPAM: 0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-0.66 / 15.00]; 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RCVD_COUNT_FIVE(0.00)[5] X-Rspamd-Queue-Id: DBF341C3BC6 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= From: Xu Rao sun4i_usb_phy_init() temporarily enables PHY2's clk2 when a SoC needs PHY2 SIDDQ setup while initializing another PHY. However, after updating PHY2's PMU register it disables the clk2 pointer from the PHY currently being initialized instead. Only PHY2 on H616 has a clk2 clock. No other PHY on H616 has a clk2 clock, so phy->clk2 is NULL in this path and disabling it is a no-op. This is why disabling the wrong clock did not cause an additional functional failure. The temporary phy2->clk2 enable therefore remains unmatched, leaking a clock enable reference each time this path is executed. Disable the same PHY2 clk2 that was enabled for the auxiliary PMU access. Fixes: b45c6d80325b ("phy: sun4i-usb: Introduce port2 SIDDQ quirk") Reviewed-by: Andre Przywara Signed-off-by: Xu Rao --- Changes in v2: - Explain why disabling phy->clk2 did not cause additional harm: no other PHY on H616 has clk2, so phy->clk2 is NULL and the operation is a no-op. - Clarify that the concrete issue is the unmatched PHY2 clk2 enable. - Add the Fixes tag and Andre's Reviewed-by. drivers/phy/allwinner/phy-sun4i-usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.50.1 diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index e2fbf8ccf99e..839856c09e30 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -318,7 +318,7 @@ static int sun4i_usb_phy_init(struct phy *_phy) writel(val, phy2->pmu + REG_HCI_PHY_CTL); } - clk_disable_unprepare(phy->clk2); + clk_disable_unprepare(phy2->clk2); } if (phy->pmu && data->cfg->hci_phy_ctl_clear) {