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Fri, 04 Sep 2026 14:33:34 -0700 (PDT) Received: from X570.phub.net.cable.rogers.com ([2607:fea8:744f:d200:9441:f2ae:56aa:8a81]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-53054227a0esm29646561cf.29.2026.09.04.14.33.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 14:33:34 -0700 (PDT) From: Barzin Lotfabadi To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Airlie , Simona Vetter Cc: Ryan Walklin , dri-devel@lists.freedesktop.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] arm64: dts: allwinner: h616: add display engine and HDMI nodes Date: Fri, 4 Sep 2026 17:33:28 -0400 Message-ID: <20260904213329.3910099-2-barzin221@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904213329.3910099-1-barzin221@gmail.com> References: <20260904213329.3910099-1-barzin221@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The H616 and its variants (H618, H700, T507) carry a Display Engine 3.3 (DE33) block feeding a TCON TOP, a TV TCON and a DesignWare HDMI 2.0 transmitter with an Allwinner-specific PHY. None of this is described in the SoC .dtsi, so nothing probes and the HDMI port stays dark even though the DE33 mixer support is present in the sun4i DRM driver. Add the display pipeline: display-engine - the DRM pipeline root bus@1000000 - DE33 bus, holding the display clock controller and the mixer clock@8000 - display clock controller mixer@100000 - DE33 mixer 0 tcon-top@6510000 - TCON TOP, muxing the mixer onto the TCONs lcd-controller@6515000 - TCON TV 0 hdmi@6000000 - DesignWare HDMI TX controller v2.12a hdmi-phy@6010000 - Allwinner H616 HDMI PHY All register addresses, clock indices and reset lines were read from the vendor device tree shipped with the board and translated to the mainline dt-bindings macros; the clock and reset numbering was verified identical between the vendor and mainline CCU headers. The mixer's three register regions are named "layers", "top" and "display". On DE33 the global control registers moved out of the mixer block into separate windows, and the driver looks up the latter two by name, so these names are load-bearing rather than decorative. Everything is left disabled; boards opt in. Signed-off-by: Barzin Lotfabadi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index 1598e8625..21aa94482 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -7,7 +7,10 @@ #include #include #include +#include +#include #include +#include #include #include @@ -94,6 +97,12 @@ l2_cache: l2-cache { }; }; + de: display-engine { + compatible = "allwinner,sun50i-h6-display-engine"; + allwinner,pipelines = <&mixer0>; + status = "disabled"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -965,6 +974,188 @@ ohci3: usb@5311400 { status = "disabled"; }; + bus: bus@1000000 { + compatible = "allwinner,sun50i-h616-de33", + "allwinner,sun50i-a64-de2"; + reg = <0x1000000 0x400000>; + allwinner,sram = <&sram_c 1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1000000 0x400000>; + + display_clocks: clock@8000 { + compatible = "allwinner,sun50i-h616-de33-clk"; + reg = <0x8000 0x100>; + clocks = <&ccu CLK_DE>, + <&ccu CLK_BUS_DE>; + clock-names = "mod", "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mixer0: mixer@100000 { + compatible = "allwinner,sun50i-h616-de33-mixer-0"; + reg = <0x100000 0x100000>, + <0x8100 0x40>, + <0x280000 0x20000>; + reg-names = "layers", "top", "display"; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", "mod"; + resets = <&display_clocks RST_MIXER0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + reg = <1>; + + mixer0_out_tcon_top_mixer0: endpoint { + remote-endpoint = <&tcon_top_mixer0_in_mixer0>; + }; + }; + }; + }; + }; + + tcon_top: tcon-top@6510000 { + compatible = "allwinner,sun50i-h6-tcon-top"; + reg = <0x6510000 0x1000>; + clocks = <&ccu CLK_BUS_TCON_TOP>, + <&ccu CLK_TCON_TV0>; + clock-names = "bus", "tcon-tv0"; + clock-output-names = "tcon-top-tv0"; + resets = <&ccu RST_BUS_TCON_TOP>; + #clock-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon_top_mixer0_in_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon_top_mixer0>; + }; + }; + + tcon_top_mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon_top_mixer0_out_tcon_tv: endpoint@2 { + reg = <2>; + remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; + }; + }; + + tcon_top_hdmi_in: port@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + tcon_top_hdmi_in_tcon_tv: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_tv_out_tcon_top_hdmi>; + }; + }; + + tcon_top_hdmi_out: port@5 { + reg = <5>; + + tcon_top_hdmi_out_hdmi: endpoint { + remote-endpoint = <&hdmi_in_tcon_top>; + }; + }; + }; + }; + + tcon_tv: lcd-controller@6515000 { + compatible = "allwinner,sun50i-h6-tcon-tv", + "allwinner,sun8i-r40-tcon-tv"; + reg = <0x6515000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON_TV0>, + <&tcon_top CLK_TCON_TOP_TV0>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON_TV0>; + reset-names = "lcd"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_tv_in: port@0 { + reg = <0>; + + tcon_tv_in_tcon_top_mixer0: endpoint { + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; + }; + }; + + tcon_tv_out: port@1 { + reg = <1>; + + tcon_tv_out_tcon_top_hdmi: endpoint { + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; + }; + }; + }; + }; + + hdmi: hdmi@6000000 { + compatible = "allwinner,sun50i-h616-dw-hdmi", + "allwinner,sun50i-h6-dw-hdmi"; + reg = <0x6000000 0x10000>; + reg-io-width = <1>; + interrupts = ; + clocks = <&ccu CLK_BUS_HDMI>, + <&ccu CLK_HDMI_SLOW>, + <&ccu CLK_HDMI>, + <&ccu CLK_HDMI_CEC>; + clock-names = "iahb", "isfr", "tmds", "cec"; + resets = <&ccu RST_BUS_HDMI_SUB>; + reset-names = "ctrl"; + phys = <&hdmi_phy>; + phy-names = "phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_tcon_top: endpoint { + remote-endpoint = <&tcon_top_hdmi_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + hdmi_phy: hdmi-phy@6010000 { + compatible = "allwinner,sun50i-h616-hdmi-phy"; + reg = <0x6010000 0x10000>; + clocks = <&ccu CLK_BUS_HDMI>, + <&ccu CLK_HDMI_SLOW>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_HDMI>; + reset-names = "phy"; + #phy-cells = <0>; + }; + rtc: rtc@7000000 { compatible = "allwinner,sun50i-h616-rtc"; reg = <0x07000000 0x400>; From patchwork Fri Sep 4 21:33:29 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Barzin Lotfabadi X-Patchwork-Id: 3188 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114]) by mxe881.netcup.net (Postfix) with ESMTPS id 042E41C2CC9 for ; Fri, 4 Sep 2026 23:34:06 +0200 (CEST) Authentication-Results: mxe881; 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Fri, 04 Sep 2026 14:33:36 -0700 (PDT) Received: from X570.phub.net.cable.rogers.com ([2607:fea8:744f:d200:9441:f2ae:56aa:8a81]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-53054227a0esm29646561cf.29.2026.09.04.14.33.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 14:33:36 -0700 (PDT) From: Barzin Lotfabadi To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Airlie , Simona Vetter Cc: Ryan Walklin , dri-devel@lists.freedesktop.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] arm64: dts: allwinner: orangepi-zero3: enable HDMI output Date: Fri, 4 Sep 2026 17:33:29 -0400 Message-ID: <20260904213329.3910099-3-barzin221@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904213329.3910099-1-barzin221@gmail.com> References: <20260904213329.3910099-1-barzin221@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The Orange Pi Zero 3 exposes the H618 HDMI transmitter on a micro-HDMI connector. Add the connector node, wire it to the HDMI transmitter's output port, and enable the display pipeline. Tested on an Orange Pi Zero 3 (H618, 4GB): the sink's EDID is read correctly and the board drives a 1920x1080@60Hz desktop. Signed-off-by: Barzin Lotfabadi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts index c51d4d912..444773e4a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts @@ -11,6 +11,17 @@ / { model = "OrangePi Zero3"; compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618"; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; }; &cpu0 { @@ -103,3 +114,17 @@ &pio { vcc-ph-supply = <®_dldo1>; vcc-pi-supply = <®_dldo1>; }; + +&de { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +};