From patchwork Thu Sep 10 13:35:12 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 3275 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sto.lore.kernel.org (sto.lore.kernel.org [172.232.135.74]) by mxe881.netcup.net (Postfix) with ESMTPS id 14C181C2261 for ; Thu, 10 Sep 2026 15:55:04 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=arm.com; spf=pass (sender IP is 172.232.135.74) smtp.mailfrom=linux-sunxi+bounces-25800-noreply=patchwork.local@lists.linux.dev smtp.helo=sto.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.232.135.74 as permitted sender) client-ip=172.232.135.74; envelope-from=linux-sunxi+bounces-25800-noreply=patchwork.local@lists.linux.dev; helo=sto.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sto.lore.kernel.org (Postfix) with ESMTP id B634C623375 for ; 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Thu, 10 Sep 2026 06:35:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789047328; bh=jnmA0n6S6YqDU0KnRi20V6Gu7FJaQfv/zxIH7uoXepU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=olMpN7jKGT9mE9//0kZtkNc3/Rm1xJBV6zMfCK2msJrzo9sEz/E36TObXsrZKdjjd PG3RZaacXmdyR/U7bEcj5sUXNYVA32+7gn3jCo/shhSjZjSFe154Hp4u440B7AKNvz J65lJpquFmXyUTjMnTTmPwrtVcOsCP2bAuo32ZRw= From: Andre Przywara To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Jerome Brunet , Yixun Lan , Enzo Adriano , Vinicius Pedrosa , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [PATCH 1/7] pinctrl: sunxi: rename SUNXI_PINCTRL_NEW_REG_LAYOUT Date: Thu, 10 Sep 2026 15:35:12 +0200 Message-ID: <20260910133519.459011-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260910133519.459011-1-andre.przywara@arm.com> References: <20260910133519.459011-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-0.66 / 15.00]; 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FREEMAIL_TO(0.00)[kernel.org,gmail.com,sholland.org]; MIME_TRACE(0.00)[0:+]; TAGGED_FROM(0.00)[bounces-25800-noreply=patchwork.local]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; ASN(0.00)[asn:63949, ipnet:172.232.128.0/19, country:SG]; RCVD_TLS_LAST(0.00)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.232.135.74:from] X-Rspamd-Queue-Id: 14C181C2261 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= After keeping the pinctrl IP mostly register compatible for almost a decade, in 2021 Allwinner introduced some changes to the register layout, which made us use a flag called SUNXI_PINCTRL_NEW_REG_LAYOUT. Now with their latest SoC (A733), Allwinner changed the pinctrl IP again, so "NEW" isn't really a fitting name anymore. Rename the symbol to SUNXI_PINCTRL_NCAT2_REG_LAYOUT, with "NCAT2" being a name often used in vendor source code to signify this "new" generation of SoCs. Just a rename of the symbol, no actual code changes. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c | 2 +- drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c | 2 +- drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c | 2 +- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 4 ++-- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c b/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c index 8efe35b77af4d..37a60e5d1163b 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c @@ -821,7 +821,7 @@ static const struct sunxi_pinctrl_desc d1_pinctrl_data = { static int d1_pinctrl_probe(struct platform_device *pdev) { return sunxi_pinctrl_init_with_flags(pdev, &d1_pinctrl_data, - SUNXI_PINCTRL_NEW_REG_LAYOUT); + SUNXI_PINCTRL_NCAT2_REG_LAYOUT); } static const struct of_device_id d1_pinctrl_match[] = { diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c index 462aa1c4a5fa6..9e07fbb5be7cb 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c @@ -35,7 +35,7 @@ static int a523_r_pinctrl_probe(struct platform_device *pdev) return sunxi_pinctrl_dt_table_init(pdev, a523_r_nr_bank_pins, a523_r_irq_bank_muxes, &a523_r_pinctrl_data, - SUNXI_PINCTRL_NEW_REG_LAYOUT); + SUNXI_PINCTRL_NCAT2_REG_LAYOUT); } static const struct of_device_id a523_r_pinctrl_match[] = { diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c index b6f78f1f30ac4..801f62abc93df 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c @@ -34,7 +34,7 @@ static int a523_pinctrl_probe(struct platform_device *pdev) return sunxi_pinctrl_dt_table_init(pdev, a523_nr_bank_pins, a523_irq_bank_muxes, &a523_pinctrl_data, - SUNXI_PINCTRL_NEW_REG_LAYOUT | + SUNXI_PINCTRL_NCAT2_REG_LAYOUT | SUNXI_PINCTRL_ELEVEN_BANKS); } diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 25489beeb3125..bc6948e3fb495 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -1107,7 +1107,7 @@ static int sunxi_pinctrl_irq_request_resources(struct irq_data *d) muxval = (readl(pctl->membase + reg) & mask) >> shift; /* Change muxing to GPIO INPUT mode if at reset value */ - if (pctl->flags & SUNXI_PINCTRL_NEW_REG_LAYOUT) + if (pctl->flags & SUNXI_PINCTRL_NCAT2_REG_LAYOUT) disabled_mux = SUN4I_FUNC_DISABLED_NEW; else disabled_mux = SUN4I_FUNC_DISABLED_OLD; @@ -1589,7 +1589,7 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev, pctl->dev = &pdev->dev; pctl->desc = desc; pctl->flags = flags; - if (flags & SUNXI_PINCTRL_NEW_REG_LAYOUT) { + if (flags & SUNXI_PINCTRL_NCAT2_REG_LAYOUT) { pctl->bank_mem_size = D1_BANK_MEM_SIZE; pctl->pull_regs_offset = D1_PULL_REGS_OFFSET; pctl->dlevel_field_width = D1_DLEVEL_FIELD_WIDTH; diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 0daf7600e2fb0..c519055e31b73 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -90,7 +90,7 @@ #define SUN4I_FUNC_DISABLED_NEW 15 #define SUNXI_PINCTRL_VARIANT_MASK GENMASK(7, 0) -#define SUNXI_PINCTRL_NEW_REG_LAYOUT BIT(8) +#define SUNXI_PINCTRL_NCAT2_REG_LAYOUT BIT(8) #define SUNXI_PINCTRL_PORTF_SWITCH BIT(9) #define SUNXI_PINCTRL_ELEVEN_BANKS BIT(10) From patchwork Thu Sep 10 13:35:13 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 3274 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 1C3191C0774 for ; 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arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B2A0C2103; Thu, 10 Sep 2026 06:35:27 -0700 (PDT) Received: from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C8AE93F528; Thu, 10 Sep 2026 06:35:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789047331; bh=FxDtznMDF3G6v0CC70O4PDTkkMNel6NjQbC+dSOUz88=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P2rUvKCc6VWahL75AGslFxx/iJECXrzPx0JPzJM6WnYBtpajHI33FgH8EJo2UJEsv 8PKF6u3/TDuCfgyMvC/K1OnSfw8CJ5cZtGERkvscnIH5PdRuwJ9e5mGsyRnv3Z4n5O W0jBsHSre5QW+IjH3+zxOCX8ovtNwI5NlkbR4L7U= From: Andre Przywara To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Jerome Brunet , Yixun Lan , Enzo Adriano , Vinicius Pedrosa , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [PATCH 2/7] pinctrl: sunxi: only use PortK special handling on A523 Date: Thu, 10 Sep 2026 15:35:13 +0200 Message-ID: <20260910133519.459011-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260910133519.459011-1-andre.przywara@arm.com> References: <20260910133519.459011-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The Allwinner A523 pinctrl IP requires an exception for addressing PortK, since the registers for this GPIO bank did not fit anymore in the existing MMIO frame. Since the A523 was also the first SoC to actually implement PortK, we just enabled this quirk unconditionally. Now the new Allwinner A733 changed the MMIO frame layout, so PortK can and must be handled without any special code. Mark the special casing for PortK with the ELEVEN_BANKS quirk flag we introduced, so that it will only be used on SoCs using the A523 pinctrl IP. Signed-off-by: Andre Przywara Reviewed-by: Chen-Yu Tsai --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index bc6948e3fb495..2524e0b3a2a5a 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -67,7 +67,7 @@ static u32 sunxi_bank_offset(const struct sunxi_pinctrl *pctl, u32 pin) { u32 offset = 0; - if (pin >= PK_BASE) { + if (pin >= PK_BASE && (pctl->flags & SUNXI_PINCTRL_ELEVEN_BANKS)) { pin -= PK_BASE; offset = PIO_BANK_K_OFFSET; } From patchwork Thu Sep 10 13:35:14 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 3277 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 744361C2261 for ; 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arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9EBA02247; Thu, 10 Sep 2026 06:35:30 -0700 (PDT) Received: from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B60F03F528; Thu, 10 Sep 2026 06:35:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789047334; bh=ATp6SchB/R4FKlGvlE5UAbJ6RFYgLziKcTWGE1Qio3I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=R7z7TwaM5BOlKCEIiciFGHxiVxVINpKS+S1vv6X3oXGSJ0b397KsGqssGARvXfomI GaxnHGNv/1DagZYbwPgQy3+LO+Lb/XMBs3aMhEW8biBkpUYLoA/hVMkCB6vvGCXjzn 4JuQOmDDpY9aUkuOnMAh/xwcEHzC3b+zOOHXWgnI= From: Andre Przywara To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Jerome Brunet , Yixun Lan , Enzo Adriano , Vinicius Pedrosa , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [PATCH 3/7] pinctrl: sunxi: refactor IRQ register accessors Date: Thu, 10 Sep 2026 15:35:14 +0200 Message-ID: <20260910133519.459011-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260910133519.459011-1-andre.przywara@arm.com> References: <20260910133519.459011-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= So far on Allwinner SoCs the registers for controlling the IRQ capabilities of each bank are grouped separately, behind all the pinmux related register for all banks: 0x000 0x024 0x144 0x200 0x220 0x320 PortA PortB ... PortJ IRQ-A IRQ-B ... IRQ-J The newest SoCs now group the IRQ registers together with the other per-bank registers, so we need to change the accessor functions to account for that: 0x080 0x0c0 0x100 0x140 0x580 0x5c0 PortA IRQ-A PortB IRQ-B ... PortK IRQ-K In preparation for supporting those newer SoCs, pass in the pointer to "struct sunxi_pinctrl" instead of just its member "desc", so that we gain access to the flags, to later determine which of the layout variants we need to use. To simplify that, add a new sunxi_irq_base_reg() function that returns the respective IRQ register base address. Also split off the IRQ control register base offset (0x200) from each IRQ register's offset, so that the individual offsets can be added later separately, to that base address. No functional change at this point, just refactoring. Signed-off-by: Andre Przywara --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 21 +++++----- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 55 ++++++++++++++++----------- 2 files changed, 44 insertions(+), 32 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 2524e0b3a2a5a..5f08c75549b4d 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -762,9 +762,10 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, else val = 0xD; /* 3.3V */ - reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); + reg = readl(pctl->membase + sunxi_grp_config_reg(pctl, pin)); reg &= ~IO_BIAS_MASK; - writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); + writel(reg | val, pctl->membase + + sunxi_grp_config_reg(pctl, pin)); return 0; case BIAS_VOLTAGE_PIO_POW_MODE_CTL: val = uV > 1800000 && uV <= 2500000 ? BIT(bank) : 0; @@ -1140,7 +1141,7 @@ static void sunxi_pinctrl_irq_release_resources(struct irq_data *d) static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) { struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); - u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq); + u32 reg = sunxi_irq_cfg_reg(pctl, d->hwirq); u8 index = sunxi_irq_cfg_offset(d->hwirq); unsigned long flags; u32 regval; @@ -1187,7 +1188,7 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) static void sunxi_pinctrl_irq_ack(struct irq_data *d) { struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); - u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq); + u32 status_reg = sunxi_irq_status_reg(pctl, d->hwirq); u8 status_idx = sunxi_irq_status_offset(d->hwirq); /* Clear the IRQ */ @@ -1197,7 +1198,7 @@ static void sunxi_pinctrl_irq_ack(struct irq_data *d) static void sunxi_pinctrl_irq_mask(struct irq_data *d) { struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); - u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); + u32 reg = sunxi_irq_ctrl_reg(pctl, d->hwirq); u8 idx = sunxi_irq_ctrl_offset(d->hwirq); unsigned long flags; u32 val; @@ -1214,7 +1215,7 @@ static void sunxi_pinctrl_irq_mask(struct irq_data *d) static void sunxi_pinctrl_irq_unmask(struct irq_data *d) { struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); - u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); + u32 reg = sunxi_irq_ctrl_reg(pctl, d->hwirq); u8 idx = sunxi_irq_ctrl_offset(d->hwirq); unsigned long flags; u32 val; @@ -1318,7 +1319,7 @@ static void sunxi_pinctrl_irq_handler(struct irq_desc *desc) chained_irq_enter(chip, desc); - reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank); + reg = sunxi_irq_status_reg_from_bank(pctl, bank); val = readl(pctl->membase + reg); if (val) { @@ -1557,7 +1558,7 @@ static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl, writel(src | div << 4, pctl->membase + - sunxi_irq_debounce_reg_from_bank(pctl->desc, i)); + sunxi_irq_debounce_reg_from_bank(pctl, i)); } return 0; @@ -1745,10 +1746,10 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev, for (i = 0; i < pctl->desc->irq_banks; i++) { /* Mask and clear all IRQs before registering a handler */ writel(0, pctl->membase + - sunxi_irq_ctrl_reg_from_bank(pctl->desc, i)); + sunxi_irq_ctrl_reg_from_bank(pctl, i)); writel(0xffffffff, pctl->membase + - sunxi_irq_status_reg_from_bank(pctl->desc, i)); + sunxi_irq_status_reg_from_bank(pctl, i)); irq_set_chained_handler_and_data(pctl->irq[i], sunxi_pinctrl_irq_handler, diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index c519055e31b73..15aa6fe62dbbc 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -57,20 +57,21 @@ #define IRQ_PER_BANK 32 -#define IRQ_CFG_REG 0x200 +#define IRQ_REGS_OFFSET 0x200 +#define IRQ_CFG_REG_OFFSET 0x00 #define IRQ_CFG_IRQ_PER_REG 8 #define IRQ_CFG_IRQ_BITS 4 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1) -#define IRQ_CTRL_REG 0x210 +#define IRQ_CTRL_REG_OFFSET 0x10 #define IRQ_CTRL_IRQ_PER_REG 32 #define IRQ_CTRL_IRQ_BITS 1 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1) -#define IRQ_STATUS_REG 0x214 +#define IRQ_STATUS_REG_OFFSET 0x14 #define IRQ_STATUS_IRQ_PER_REG 32 #define IRQ_STATUS_IRQ_BITS 1 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1) -#define IRQ_DEBOUNCE_REG 0x218 +#define IRQ_DEBOUNCE_REG_OFFSET 0x18 #define IRQ_MEM_SIZE 0x20 @@ -226,7 +227,8 @@ struct sunxi_pinctrl { .irqnum = _irq, \ } -static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank) +static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, + u8 bank) { if (!desc->irq_bank_map) return bank; @@ -234,68 +236,77 @@ static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u return desc->irq_bank_map[bank]; } -static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc, +static inline u32 sunxi_irq_base_reg(const struct sunxi_pinctrl *pctl, u16 bank) +{ + return IRQ_REGS_OFFSET + + sunxi_irq_hw_bank_num(pctl->desc, bank) * IRQ_MEM_SIZE; +} + +static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl *pctl, u16 irq) { u8 bank = irq / IRQ_PER_BANK; u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04; - return IRQ_CFG_REG + - sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg; + return sunxi_irq_base_reg(pctl, bank) + IRQ_CFG_REG_OFFSET + reg; } static inline u32 sunxi_irq_cfg_offset(u16 irq) { u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG; + return irq_num * IRQ_CFG_IRQ_BITS; } -static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) +static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl *pctl, + u8 bank) { - return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; + return sunxi_irq_base_reg(pctl, bank) + IRQ_CTRL_REG_OFFSET; } -static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc, - u16 irq) +static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl *pctl, u16 irq) { u8 bank = irq / IRQ_PER_BANK; - return sunxi_irq_ctrl_reg_from_bank(desc, bank); + return sunxi_irq_ctrl_reg_from_bank(pctl, bank); } static inline u32 sunxi_irq_ctrl_offset(u16 irq) { u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG; + return irq_num * IRQ_CTRL_IRQ_BITS; } -static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) +static inline +u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl *pctl, u8 bank) { - return IRQ_DEBOUNCE_REG + - sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; + return sunxi_irq_base_reg(pctl, bank) + IRQ_DEBOUNCE_REG_OFFSET; } -static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) +static inline +u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl *pctl, u8 bank) { - return IRQ_STATUS_REG + - sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; + return sunxi_irq_base_reg(pctl, bank) + IRQ_STATUS_REG_OFFSET; } -static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc, +static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl *pctl, u16 irq) { u8 bank = irq / IRQ_PER_BANK; - return sunxi_irq_status_reg_from_bank(desc, bank); + return sunxi_irq_status_reg_from_bank(pctl, bank); } static inline u32 sunxi_irq_status_offset(u16 irq) { u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG; + return irq_num * IRQ_STATUS_IRQ_BITS; } -static inline u32 sunxi_grp_config_reg(u16 pin) +static inline u32 sunxi_grp_config_reg(const struct sunxi_pinctrl *pctl, + u16 pin) { u8 bank = pin / PINS_PER_BANK; From patchwork Thu Sep 10 13:35:15 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 3272 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id EE69A1C2261 for ; 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FREEMAIL_TO(0.00)[kernel.org,gmail.com,sholland.org]; MIME_TRACE(0.00)[0:+]; TAGGED_FROM(0.00)[bounces-25803-noreply=patchwork.local]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; RCVD_TLS_LAST(0.00)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.234.253.10:from] X-Rspamd-Queue-Id: EE69A1C2261 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= After Allwinner changed the layout of the pinctrl/GPIO IP MMIO register frame only a few years back, the new SoC generation (starting with the A733) changes the layout again: each port now uses 128 instead of 36 or 48 bytes, and the drive level registers move to make space for the new set/clear data registers. Also the PortA registers start at offset 0x80 instead of 0x0 as before, to make room for non-bank specific registers, like the pow_mod_sel registers, at the beginning of the MMIO frame. Finally the IRQ registers move into each bank's region. Add yet another quirk bit to mark this case, and set the existing register offset values to match the new layout. This also requires to add new members to struct sunxi_pinctrl, to accommodate the extra changes. The actual runtime code changes are fortunately minor. Signed-off-by: Andre Przywara --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 14 ++++++++++++-- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 14 ++++++++++++++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 5f08c75549b4d..35aa3a8ea1814 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -65,7 +65,7 @@ static struct irq_chip sunxi_pinctrl_level_irq_chip; */ static u32 sunxi_bank_offset(const struct sunxi_pinctrl *pctl, u32 pin) { - u32 offset = 0; + u32 offset = pctl->bank_offset; if (pin >= PK_BASE && (pctl->flags & SUNXI_PINCTRL_ELEVEN_BANKS)) { pin -= PK_BASE; @@ -102,7 +102,7 @@ static void sunxi_dlevel_reg(const struct sunxi_pinctrl *pctl, { u32 offset = pin % PINS_PER_BANK * pctl->dlevel_field_width; - *reg = sunxi_bank_offset(pctl, pin) + DLEVEL_REGS_OFFSET + + *reg = sunxi_bank_offset(pctl, pin) + pctl->drv_regs_offset + offset / BITS_PER_TYPE(u32) * sizeof(u32); *shift = offset % BITS_PER_TYPE(u32); *mask = (BIT(pctl->dlevel_field_width) - 1) << *shift; @@ -1592,15 +1592,25 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev, pctl->flags = flags; if (flags & SUNXI_PINCTRL_NCAT2_REG_LAYOUT) { pctl->bank_mem_size = D1_BANK_MEM_SIZE; + pctl->drv_regs_offset = DLEVEL_REGS_OFFSET; pctl->pull_regs_offset = D1_PULL_REGS_OFFSET; pctl->dlevel_field_width = D1_DLEVEL_FIELD_WIDTH; + } else if (flags & SUNXI_PINCTRL_NCAT3_REG_LAYOUT) { + pctl->bank_mem_size = A733_BANK_MEM_SIZE; + pctl->bank_offset = A733_BANK_OFFSET; + pctl->drv_regs_offset = A733_DLEVEL_REGS_OFFSET; + pctl->pull_regs_offset = A733_PULL_REGS_OFFSET; + pctl->dlevel_field_width = D1_DLEVEL_FIELD_WIDTH; } else { pctl->bank_mem_size = BANK_MEM_SIZE; + pctl->drv_regs_offset = DLEVEL_REGS_OFFSET; pctl->pull_regs_offset = PULL_REGS_OFFSET; pctl->dlevel_field_width = DLEVEL_FIELD_WIDTH; } if (flags & SUNXI_PINCTRL_ELEVEN_BANKS) pctl->pow_mod_sel_offset = PIO_11B_POW_MOD_SEL_REG; + else if (flags & SUNXI_PINCTRL_NCAT3_REG_LAYOUT) + pctl->pow_mod_sel_offset = PIO_NCAT3_POW_MOD_SEL_REG; else pctl->pow_mod_sel_offset = PIO_POW_MOD_SEL_REG; diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 15aa6fe62dbbc..d09467ed437a3 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -53,6 +53,12 @@ #define D1_DLEVEL_FIELD_WIDTH 4 #define D1_PULL_REGS_OFFSET 0x24 +#define A733_BANK_MEM_SIZE 0x80 +#define A733_BANK_OFFSET 0x80 +#define A733_DLEVEL_REGS_OFFSET 0x20 +#define A733_PULL_REGS_OFFSET 0x30 +#define A733_IRQ_REGS_OFFSET 0x40 + #define PINS_PER_BANK 32 #define IRQ_PER_BANK 32 @@ -94,7 +100,9 @@ #define SUNXI_PINCTRL_NCAT2_REG_LAYOUT BIT(8) #define SUNXI_PINCTRL_PORTF_SWITCH BIT(9) #define SUNXI_PINCTRL_ELEVEN_BANKS BIT(10) +#define SUNXI_PINCTRL_NCAT3_REG_LAYOUT BIT(11) +#define PIO_NCAT3_POW_MOD_SEL_REG 0x040 #define PIO_POW_MOD_SEL_REG 0x340 #define PIO_11B_POW_MOD_SEL_REG 0x380 #define PIO_POW_MOD_CTL_OFS 0x004 @@ -179,6 +187,8 @@ struct sunxi_pinctrl { struct pinctrl_dev *pctl_dev; unsigned long flags; u32 bank_mem_size; + u32 bank_offset; + u32 drv_regs_offset; u32 pull_regs_offset; u32 dlevel_field_width; u32 pow_mod_sel_offset; @@ -238,6 +248,10 @@ static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, static inline u32 sunxi_irq_base_reg(const struct sunxi_pinctrl *pctl, u16 bank) { + if (pctl->flags & SUNXI_PINCTRL_NCAT3_REG_LAYOUT) + return pctl->bank_offset + bank * pctl->bank_mem_size + + A733_IRQ_REGS_OFFSET; + return IRQ_REGS_OFFSET + sunxi_irq_hw_bank_num(pctl->desc, bank) * IRQ_MEM_SIZE; } From patchwork Thu Sep 10 13:35:16 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 3278 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 43A751C0774 for ; Thu, 10 Sep 2026 15:59:06 +0200 (CEST) Authentication-Results: mxe881; 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arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7DA1622C7; Thu, 10 Sep 2026 06:35:36 -0700 (PDT) Received: from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9220C3F528; Thu, 10 Sep 2026 06:35:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789047340; bh=hSa/tH8M8jk5gYes5gwVXQnH3e8X4j6HtduRWqIb3Ig=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ufl9Fesw8ci7X2Kc4PTAqdtuKbfDNk+st4bNXYBhxmDMYOlz9TjgyfWh6sRuv1v9o 4juU4bwHRWNchv+K9SsLkDg/Cjrt2THjC5Kz22Fx7iL3pImZJnbqHUC5HqcWb9bEJQ ZVD7Sy5FAi2WzcsvanRC8rC1EoFFOsxLHqa/1QnM= From: Andre Przywara To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Jerome Brunet , Yixun Lan , Enzo Adriano , Vinicius Pedrosa , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [PATCH 5/7] dt-bindings: pinctrl: add compatible for Allwinner A733 Date: Thu, 10 Sep 2026 15:35:16 +0200 Message-ID: <20260910133519.459011-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260910133519.459011-1-andre.przywara@arm.com> References: <20260910133519.459011-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The A733 contains a pin controller similar to previous SoCs, although with a change in the MMIO register frame layout. This SoC uses the new style of DT binding, where the pinmux values for each pin group are stored in the new "allwinner,pinmux" property in the DT node. Add the new compatible to the existing A523 binding, since they share a lot of features, including the number of banks and clocks. Signed-off-by: Andre Przywara Acked-by: Conor Dooley --- .../bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml index f87b8274cc372..d7d0ba32ced4d 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/allwinner,sun55i-a523-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A523 Pin Controller +title: Allwinner A523 & A733 Pin Controller maintainers: - Andre Przywara @@ -28,6 +28,8 @@ properties: enum: - allwinner,sun55i-a523-pinctrl - allwinner,sun55i-a523-r-pinctrl + - allwinner,sun60i-a733-pinctrl + - allwinner,sun60i-a733-r-pinctrl reg: maxItems: 1 @@ -126,6 +128,7 @@ allOf: compatible: enum: - allwinner,sun55i-a523-pinctrl + - allwinner,sun60i-a733-pinctrl then: properties: @@ -138,6 +141,7 @@ allOf: compatible: enum: - allwinner,sun55i-a523-r-pinctrl + - allwinner,sun60i-a733-r-pinctrl then: properties: From patchwork Thu Sep 10 13:35:17 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 3273 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id B23721C0774 for ; Thu, 10 Sep 2026 15:54:10 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=arm.com; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-25805-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; envelope-from=linux-sunxi+bounces-25805-noreply=patchwork.local@lists.linux.dev; helo=sea.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sea.lore.kernel.org (Postfix) with ESMTP id CC84964939 for ; Thu, 10 Sep 2026 13:41:47 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6810F4A2634; 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smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=TMigpWmV; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6BD5322C8; Thu, 10 Sep 2026 06:35:39 -0700 (PDT) Received: from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 801593F528; Thu, 10 Sep 2026 06:35:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789047343; bh=vFiGko9W5vY2zPx9uystmT+pgsJatJ921+bOqjDFnsw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TMigpWmVs+gqlwFfSICdSaAmeo6lDUIvUP6cV9HfrbQt55FN6fTzomymOP19U3v9J f6VS/cUdGXCOgakdg9hL8rw6vkvhAOCtOPHpv2tmQbRYrLHCKE3+EGZOdPbMKr6CaC Njqm5G9HmtqPDwAg+e3/s/nDqc31iNGz9UqrHa3A= From: Andre Przywara To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Jerome Brunet , Yixun Lan , Enzo Adriano , Vinicius Pedrosa , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [PATCH 6/7] pinctrl: sunxi: a523-r: add a733-r compatible string Date: Thu, 10 Sep 2026 15:35:17 +0200 Message-ID: <20260910133519.459011-7-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260910133519.459011-1-andre.przywara@arm.com> References: <20260910133519.459011-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-0.66 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.234.253.10:from]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; MAILLIST(-0.15)[generic]; BAD_REP_POLICIES(0.10)[]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; TAGGED_RCPT(0.00)[dt]; FROM_HAS_DN(0.00)[]; PRECEDENCE_BULK(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; RCPT_COUNT_TWELVE(0.00)[15]; FREEMAIL_CC(0.00)[baylibre.com,gentoo.org,gmail.com,vger.kernel.org,lists.infradead.org,lists.linux.dev]; DBL_BLOCKED_OPENRESOLVER(0.00)[arm.com:email,arm.com:dkim,sea.lore.kernel.org:rdns,sea.lore.kernel.org:helo]; FORGED_SENDER_MAILLIST(0.00)[]; R_DKIM_ALLOW(0.00)[arm.com:s=foss]; RCVD_COUNT_FIVE(0.00)[6]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; DKIM_TRACE(0.00)[arm.com:+]; DMARC_POLICY_ALLOW(0.00)[arm.com,none]; R_SPF_ALLOW(0.00)[+ip4:172.234.253.10]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[217.140.110.172:received,100.90.174.1:received]; TO_DN_SOME(0.00)[]; FROM_NEQ_ENVFROM(0.00)[andre.przywara@arm.com,linux-sunxi@lists.linux.dev]; FREEMAIL_TO(0.00)[kernel.org,gmail.com,sholland.org]; MIME_TRACE(0.00)[0:+]; TAGGED_FROM(0.00)[bounces-25805-noreply=patchwork.local]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; RCVD_TLS_LAST(0.00)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.234.253.10:from] X-Rspamd-Queue-Id: B23721C0774 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The secondary Allwinner A733 pincontroller ("-r") is interestingly not using the same new MMIO frame layout as the main controller, but is in fact very similar to the A523-r one: it has two banks, with 14 and 6 pins each. From the driver's perspective, this is all we care about, so we can re-use the a523-r pinctrl driver for the a733-r, too. The individual pinmux settings are different, so we must not use the a523-r compatible string as a fallback, but we can surely let the same driver care for both the a523-r and a733-r IP, as the pinmux values will be provided by the DT. Add the a733-r compatible string to the match list, without further distinguishing between the two. Should differences be discovered later, we can easily split this up then. Signed-off-by: Andre Przywara --- drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c index 9e07fbb5be7cb..dfdcfa740ecc9 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c @@ -40,6 +40,7 @@ static int a523_r_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id a523_r_pinctrl_match[] = { { .compatible = "allwinner,sun55i-a523-r-pinctrl", }, + { .compatible = "allwinner,sun60i-a733-r-pinctrl", }, {} }; From patchwork Thu Sep 10 13:35:18 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 3276 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id AB0571C591C for ; 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arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5978922D7; Thu, 10 Sep 2026 06:35:42 -0700 (PDT) Received: from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6DE663F528; Thu, 10 Sep 2026 06:35:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789047346; bh=afNw4mfmWPusnYCWAuWnIcZqwy8vQndi0BEvd7sUpx8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UfTRtROJp3o3h+kxey19i79i5p4qm5F7glE6bRJQrgIYbYioCZeEY5yrFrRBP1oFX Wge3Vj4qNIzetJJqDKqGYvcETFwerYkqYBLrSrmevjQS6lhgc77Hxa3AwQ+DgaBSbA K9PGVLIAGmHvsbT/PtW7vjT5XljEHaKEEa6SqU6U= From: Andre Przywara To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Jerome Brunet , Yixun Lan , Enzo Adriano , Vinicius Pedrosa , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [PATCH 7/7] pinctrl: sunxi: add support for the Allwinner A733 Date: Thu, 10 Sep 2026 15:35:18 +0200 Message-ID: <20260910133519.459011-8-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260910133519.459011-1-andre.przywara@arm.com> References: <20260910133519.459011-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The Allwinner A733 changes the layout of the pinctrl MMIO register frame, but stays otherwise rather close to the previous IP. The main PIO looks similar to the one in the A523, with ports B-K being implemented, each also with the same number of pins per port as on the A523. Use the DT based pinctrl driver to describe just the generic pinctrl properties, so advertise the number of pins per bank, interrupt capabilities and the new quirks. The actual function/mux assignment will be taken from the devicetree. Signed-off-by: Andre Przywara --- drivers/pinctrl/sunxi/Kconfig | 5 +++ drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c | 50 +++++++++++++++++++++ 3 files changed, 56 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index dc62eba96348e..831bb1dc93738 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -141,4 +141,9 @@ config PINCTRL_SUN55I_A523_R default ARM64 && ARCH_SUNXI select PINCTRL_SUNXI +config PINCTRL_SUN60I_A733 + bool "Support for the Allwinner A733 PIO" + default ARM64 && ARCH_SUNXI + select PINCTRL_SUNXI + endif diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 951b3f1e4b4f1..3658c9d06b498 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -29,5 +29,6 @@ obj-$(CONFIG_PINCTRL_SUN50I_H616) += pinctrl-sun50i-h616.o obj-$(CONFIG_PINCTRL_SUN50I_H616_R) += pinctrl-sun50i-h616-r.o obj-$(CONFIG_PINCTRL_SUN55I_A523) += pinctrl-sun55i-a523.o obj-$(CONFIG_PINCTRL_SUN55I_A523_R) += pinctrl-sun55i-a523-r.o +obj-$(CONFIG_PINCTRL_SUN60I_A733) += pinctrl-sun60i-a733.o obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c b/drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c new file mode 100644 index 0000000000000..ca82f08a3a65b --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Allwinner A733 SoC pinctrl driver. + * + * Copyright (C) 2025 Arm Ltd. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" + +static const u8 a733_nr_bank_pins[SUNXI_PINCTRL_MAX_BANKS] = +/* PA PB PC PD PE PF PG PH PI PJ PK */ + { 0, 11, 17, 24, 16, 7, 15, 20, 17, 28, 26 }; + +static const u8 a733_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] = +/* PA PB PC PD PE PF PG PH PI PJ PK */ + { 0, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}; + +static struct sunxi_pinctrl_desc a733_pinctrl_data = { + .irq_banks = 10, + .irq_read_needs_mux = true, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, +}; + +static int a733_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_dt_table_init(pdev, a733_nr_bank_pins, + a733_irq_bank_muxes, + &a733_pinctrl_data, + SUNXI_PINCTRL_NCAT3_REG_LAYOUT); +} + +static const struct of_device_id a733_pinctrl_match[] = { + { .compatible = "allwinner,sun60i-a733-pinctrl", }, + {} +}; + +static struct platform_driver a733_pinctrl_driver = { + .probe = a733_pinctrl_probe, + .driver = { + .name = "sun60i-a733-pinctrl", + .of_match_table = a733_pinctrl_match, + }, +}; +builtin_platform_driver(a733_pinctrl_driver);