From patchwork Wed Sep 16 04:41:16 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alastair D'Silva X-Patchwork-Id: 3371 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id A3BB71C1FF4 for ; Wed, 16 Sep 2026 06:43:30 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=d-silva.org; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-25974-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; envelope-from=linux-sunxi+bounces-25974-noreply=patchwork.local@lists.linux.dev; helo=sea.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sea.lore.kernel.org (Postfix) with ESMTP id CA4032E421 for ; Wed, 16 Sep 2026 04:41:39 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AC5371BD9D0; Wed, 16 Sep 2026 04:41:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=d-silva.org header.i=@d-silva.org header.b="TVevDxfh" X-Original-To: linux-sunxi@lists.linux.dev Received: from www.nmnhosting.com (watt.d-silva.org [119.15.109.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B4CC36B910 for ; Wed, 16 Sep 2026 04:41:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=119.15.109.137 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789533698; cv=none; b=m8LZ42AQBVlLRzb+wvALpI4MFfNR4drsAZRkwhKK9KVoVwojX4llvizzNbnmb+ZD979Uluu8dplglTLHDypcBpBZ0IdNgJ7nDV7dvkS8qPyT+diUtG7sP7ioEfNZ13AU6nthHhgq/F1/cDki/JSWvKkpaLxpzf1qtgeyxeEWICo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789533698; c=relaxed/simple; bh=7NPwQy2auI7LmLQm3SpYdb8l1i8zjUHB0l13I1dVu+s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TJErwAUV8DItRYz5DwWKEsUFNkikz+H8PO0PvrnHXWYKPfYbFplyKFIFX7rTcEcsUhSlBhsQnnMO2ZD4UehG/lFblEEz9JoiRqqjp/3RlJ3JJ4x5SW85oTmIcKBnvx0WjmyhRsoBHT6DEsYGMPHc9KkQsAWGigtZxbxEYfErvrg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=d-silva.org; spf=pass smtp.mailfrom=d-silva.org; dkim=pass (2048-bit key) header.d=d-silva.org header.i=@d-silva.org header.b=TVevDxfh; arc=none smtp.client-ip=119.15.109.137 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=d-silva.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=d-silva.org Received: from Hawking.lan (hawking.lan [10.0.1.4]) by www.nmnhosting.com (Postfix) with ESMTP id 5165D424F1; Wed, 16 Sep 2026 14:41:27 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=d-silva.org; s=2025a; t=1789533687; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=G/UK2qpKtNV1mnmu2lxIpo6gk6uPMJBOxxrjbjHOjE8=; b=TVevDxfhqAX54sA9vZQWaBqtG2zSD+Fe4J8ZB3UfbBQbzBqtslXdfrAEeqtC1fQ96qI76z 5AfPBj+mSDZoIrTHZDbnK0/kAvULYaMDkDb5IXM5+1UWsD21tn0VtitEEzOM1XSpsp4t0X TjhGRUUlZTgYMNWnBcstLBe6HvvG5M0v1LKn6Zu+AHLNs8qx468UcZaLwtaqLRfP93v4UK mbzORxn1jAJMkLN+Jp7l1AquUN2gxO6FsamKTCbbNAKiDquqOKCVgZNXoCiYKlN44CLkTU pDs6OkpBpQ2zyVIsaGpX5laoY6fOgDs5L6NPF/Q+H2vUuR4GqgvAojeeGH1nHA== X-GPT-Reason: legitimate; this is a technical Linux kernel patch submission for device tree bindings. The mailbox (alastair@d-silva.org) aligns perfectly with the sender (Alastair D'Silva ), and the content is a standard git-style patch for the net-next mailing list. The URL domain (devicetree.org) is relevant to the technical topic of hardware bindings, and there are no indicators of phishing, marketing, or urgency. From: Alastair D'Silva To: Andrew Lunn , Heiner Kallweit , Russell King , Alexandre Torgue , Maxime Chevallier , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Alastair D'Silva Subject: [PATCH net-next 1/4] dt-bindings: net: phy: Add Allwinner AC300 EPHY binding Date: Wed, 16 Sep 2026 14:41:16 +1000 Message-ID: <20260916044119.475666-2-alastair@d-silva.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260916044119.475666-1-alastair@d-silva.org> References: <20260916044119.475666-1-alastair@d-silva.org> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-0.66 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.234.253.10:from]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; MAILLIST(-0.15)[generic]; BAD_REP_POLICIES(0.10)[]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; PRECEDENCE_BULK(0.00)[]; TAGGED_RCPT(0.00)[netdev,dt]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[119.15.109.137:received,100.90.174.1:received]; RCPT_COUNT_TWELVE(0.00)[21]; FREEMAIL_CC(0.00)[vger.kernel.org,lists.linux.dev,lists.infradead.org,kernel.org,gmail.com,sholland.org,d-silva.org]; DBL_BLOCKED_OPENRESOLVER(0.00)[d-silva.org:email,d-silva.org:dkim,sea.lore.kernel.org:rdns,sea.lore.kernel.org:helo,0.0.0.0:email,devicetree.org:url]; FORGED_SENDER_MAILLIST(0.00)[]; FROM_HAS_DN(0.00)[]; R_DKIM_ALLOW(0.00)[d-silva.org:s=2025a]; FROM_NEQ_ENVFROM(0.00)[alastair@d-silva.org,linux-sunxi@lists.linux.dev]; DMARC_POLICY_ALLOW(0.00)[d-silva.org,reject]; FREEMAIL_TO(0.00)[lunn.ch,gmail.com,armlinux.org.uk,foss.st.com,bootlin.com,davemloft.net,google.com,kernel.org,redhat.com]; DKIM_TRACE(0.00)[d-silva.org:+]; TO_DN_SOME(0.00)[]; R_SPF_ALLOW(0.00)[+ip4:172.234.253.10]; RCVD_COUNT_FIVE(0.00)[5]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; RCVD_TLS_LAST(0.00)[]; TAGGED_FROM(0.00)[bounces-25974-noreply=patchwork.local]; MIME_TRACE(0.00)[0:+]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.234.253.10:from] X-Rspamd-Queue-Id: A3BB71C1FF4 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Add device tree binding documentation for the Allwinner AC300 Fast Ethernet Physical Layer (EPHY) co-packaged on Allwinner H616 and H618 SoCs. Assisted-by: LLM Signed-off-by: Alastair D'Silva --- Notes: Tested on Mellow Fly-C5 (Allwinner H618) under Armbian with Linux 6.18 and 7.x kernels, verifying schema validation with dt_binding_check. .../net/allwinner,sun50i-h618-ac300-ephy.yaml | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun50i-h618-ac300-ephy.yaml diff --git a/Documentation/devicetree/bindings/net/allwinner,sun50i-h618-ac300-ephy.yaml b/Documentation/devicetree/bindings/net/allwinner,sun50i-h618-ac300-ephy.yaml new file mode 100644 index 000000000000..a04416e78138 --- /dev/null +++ b/Documentation/devicetree/bindings/net/allwinner,sun50i-h618-ac300-ephy.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/allwinner,sun50i-h618-ac300-ephy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner AC300 Ethernet PHY + +maintainers: + - Alastair D'Silva + +description: + The AC300 is an integrated Fast Ethernet Physical Layer (EPHY) co-packaged + with Allwinner H616 and H618 SoCs, communicated with over MDIO. + +allOf: + - $ref: ethernet-phy.yaml# + +select: + properties: + compatible: + contains: + const: allwinner,sun50i-h618-ac300-ephy + required: + - compatible + +properties: + compatible: + items: + - const: ethernet-phy-id0044.1400 + - const: allwinner,sun50i-h618-ac300-ephy + - const: ethernet-phy-ieee802.3-c22 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: 25MHz reference clock from CCU + - description: 2MHz reference clock from PWM + + clock-names: + minItems: 1 + items: + - const: ephy + - const: pwm + + nvmem-cells: + items: + - description: Calibration data from SID + + nvmem-cell-names: + items: + - const: calibration + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + compatible = "ethernet-phy-id0044.1400", + "allwinner,sun50i-h618-ac300-ephy", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + clocks = <&ccu 81>, <&ac300_pwm_clk>; + clock-names = "ephy", "pwm"; + nvmem-cells = <&ephy_calibration>; + nvmem-cell-names = "calibration"; + }; + }; From patchwork Wed Sep 16 04:41:17 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alastair D'Silva X-Patchwork-Id: 3372 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id BD01F1C1FF4 for ; Wed, 16 Sep 2026 06:44:24 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=d-silva.org; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-25975-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; envelope-from=linux-sunxi+bounces-25975-noreply=patchwork.local@lists.linux.dev; helo=sea.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sea.lore.kernel.org (Postfix) with ESMTP id 0A65A3CD06 for ; Wed, 16 Sep 2026 04:41:54 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4CEB93B2FC6; Wed, 16 Sep 2026 04:41:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=d-silva.org header.i=@d-silva.org header.b="0fM+Bbd+" X-Original-To: linux-sunxi@lists.linux.dev Received: from www.nmnhosting.com (watt.d-silva.org [119.15.109.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DE863AC0E9 for ; Wed, 16 Sep 2026 04:41:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=119.15.109.137 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789533713; cv=none; b=ATbkoceLkZJ7ACbU989h8iNNpj3fhY/fwKsu/GwHkcxDG++H3sazW8DkzD3X2Znbd7FVw6ZimkClVoNK7TtqRogCjv4D1hiz8b6jz2b9N0YpQijvoAmdKM9nd1Jo6UYciSAJsrsIB3kVzp4lZwakS13k4/crvIEgfkM7BMRQDbU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789533713; c=relaxed/simple; bh=aMWczIEqeYggtk8qBPl7Xvpeyy0secKTqQ+GfWpMaZY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=r5SzjWt0FdQ0HRE8whplpONkY0P08OTkZt202vd22bT9fyXmBNjGsuIrnLBUqDLlGCDznM1PRht0/58nfb1JUYD73VOXt1xGMqzsob40Qufon/tdjCERiRiq1vyOoQvK6eDvEQCqaPv09Zn88zITllI4SCj3IGF6xgkTKXBYZeM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=d-silva.org; spf=pass smtp.mailfrom=d-silva.org; dkim=pass (2048-bit key) header.d=d-silva.org header.i=@d-silva.org header.b=0fM+Bbd+; arc=none smtp.client-ip=119.15.109.137 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=d-silva.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=d-silva.org Received: from Hawking.lan (hawking.lan [10.0.1.4]) by www.nmnhosting.com (Postfix) with ESMTP id 7575843BC4; Wed, 16 Sep 2026 14:41:35 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=d-silva.org; s=2025a; t=1789533695; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Ia5UEC091vWYGaLXg2IJatFIQRrBZcpebd6XutvbknM=; b=0fM+Bbd+dF0CUTY5gmmWczH+Q1EPowE/U8hYc4suiDhqeo2DLCywqWk6Mxj2pQFW6zLnKS bNm5udLTPsPyToa4n5wp4RDk588TWRLxMsknufkCUtTLLodEewXDHuJ+nz1vwEI350VjPz FxRW4JaV/6F0oTYW7EbrFO0cL0QZbidIn/wtFZ/9D47WRUu/jTjiHAAEUMQfj8IwO8E8FD LUqFgAAnuaONhuL88NgiA4B3MJERBQdrog480nbQCpJYrThmaoieCutHARocnyimuVKzf1 83uy8wysHoNineYtLMxhfjq4AAtHi2dxQp44D8yN8hHjPI0BV3GZwKOKlvb1NA== X-GPT-Reason: legitimate; the message is a technical software patch for a Linux kernel driver (net-next), which perfectly aligns with the technical nature of the sender's domain (d-silva.org) and the provided URL (linux-sunxi.org); there are no phishing indicators, as the content consists of standard C source code (diffs) and includes a "Signed-off-by" tag; the mailbox is expected to receive such developer communications, and no urgency or suspicious links are present. From: Alastair D'Silva To: Andrew Lunn , Heiner Kallweit , Russell King , Alexandre Torgue , Maxime Chevallier , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Alastair D'Silva Subject: [PATCH net-next 2/4] net: phy: Add Allwinner AC300 EPHY driver Date: Wed, 16 Sep 2026 14:41:17 +1000 Message-ID: <20260916044119.475666-3-alastair@d-silva.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260916044119.475666-1-alastair@d-silva.org> References: <20260916044119.475666-1-alastair@d-silva.org> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-0.66 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.234.253.10:from]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; MAILLIST(-0.15)[generic]; BAD_REP_POLICIES(0.10)[]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; PRECEDENCE_BULK(0.00)[]; TAGGED_RCPT(0.00)[netdev,dt]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[119.15.109.137:received,100.90.174.1:received]; RCPT_COUNT_TWELVE(0.00)[21]; FREEMAIL_CC(0.00)[vger.kernel.org,lists.linux.dev,lists.infradead.org,kernel.org,gmail.com,sholland.org,d-silva.org]; DBL_BLOCKED_OPENRESOLVER(0.00)[sea.lore.kernel.org:rdns,sea.lore.kernel.org:helo,d-silva.org:email,d-silva.org:dkim]; FORGED_SENDER_MAILLIST(0.00)[]; FROM_HAS_DN(0.00)[]; R_DKIM_ALLOW(0.00)[d-silva.org:s=2025a]; FROM_NEQ_ENVFROM(0.00)[alastair@d-silva.org,linux-sunxi@lists.linux.dev]; DMARC_POLICY_ALLOW(0.00)[d-silva.org,reject]; FREEMAIL_TO(0.00)[lunn.ch,gmail.com,armlinux.org.uk,foss.st.com,bootlin.com,davemloft.net,google.com,kernel.org,redhat.com]; DKIM_TRACE(0.00)[d-silva.org:+]; TO_DN_SOME(0.00)[]; R_SPF_ALLOW(0.00)[+ip4:172.234.253.10]; RCVD_COUNT_FIVE(0.00)[5]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; RCVD_TLS_LAST(0.00)[]; TAGGED_FROM(0.00)[bounces-25975-noreply=patchwork.local]; MIME_TRACE(0.00)[0:+]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.234.253.10:from] X-Rspamd-Queue-Id: BD01F1C1FF4 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Add support for the Allwinner AC300 integrated Fast Ethernet Physical Layer (EPHY) co-packaged on Allwinner H616 and H618 SoCs. The driver communicates with the AC300 configuration space over MDIO at address 16 + phy_addr, handles internal power domains, clock gating, bandgap calibration retrieval from SID nvmem, and optimizes transceiver signal path registers. Assisted-by: LLM Signed-off-by: Alastair D'Silva --- Notes: Tested on Mellow Fly-C5 (Allwinner H618) under Armbian with sustained 100Mbps traffic (DHCP, iperf3, NFS rootfs), verifying indirect MDIO register programming and bandgap calibration readout from SID nvmem. drivers/net/phy/Kconfig | 9 + drivers/net/phy/Makefile | 1 + drivers/net/phy/ac300-phy.c | 331 ++++++++++++++++++++++++++++++++++++ 3 files changed, 341 insertions(+) create mode 100644 drivers/net/phy/ac300-phy.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index b4ef927fd4a6..c473f0a814b7 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -120,6 +120,15 @@ config MESON_GXL_PHY help Currently has a driver for the Amlogic Meson GXL Internal PHY +config AC300_PHY + tristate "Allwinner AC300 EPHY support" + depends on OF && NVMEM + help + Support for the Allwinner AC300 integrated Fast Ethernet Physical + Layer (EPHY) co-packaged on Allwinner H616 and H618 SoCs. The AC300 + EPHY communicates over MDIO and provides 10/100 Mbps connectivity. + If compiled as a module, it will be called ac300-phy. + config ADIN_PHY tristate "Analog Devices Industrial Ethernet PHYs" help diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 25c4a3c2429f..98453e68fd9f 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_SFP) += sfp.o sfp-obj-$(CONFIG_SFP) += sfp-bus.o obj-y += $(sfp-obj-y) $(sfp-obj-m) +obj-$(CONFIG_AC300_PHY) += ac300-phy.o obj-$(CONFIG_ADIN_PHY) += adin.o obj-$(CONFIG_ADIN1100_PHY) += adin1100.o obj-$(CONFIG_ADIN1140_PHY) += adin1140-phy.o diff --git a/drivers/net/phy/ac300-phy.c b/drivers/net/phy/ac300-phy.c new file mode 100644 index 000000000000..c70f567c3179 --- /dev/null +++ b/drivers/net/phy/ac300-phy.c @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: GPL-2.0+ +/** + * Driver for X-Powers AC300 Ethernet PHY + * + * Datasheet: https://linux-sunxi.org/images/b/b2/AC300_User_Manual_V1.0_cleaned.pdf + * + * Copyright (c) 2026 Alastair D'Silva + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AC300_EPHY_ID 0x00441400 +#define AC300_EPHY_ID_MASK 0x0ffffff0 + +/* AC300 Configuration Registers (on MDIO Address 16) */ +#define AC300_REG00_CHIP_VERSION_MASK GENMASK(15, 12) +#define AC300_REG00_PKG_STATUS_MASK GENMASK(11, 8) +#define AC300_REG00_EPHY_CLK_SEL_MASK GENMASK(7, 6) +#define AC300_REG00_EPHY_CLK_SEL_25M 0 +#define AC300_REG00_EPHY_CLK_SEL_27M 1 +#define AC300_REG00_EPHY_CLK_SEL_24M 2 +#define AC300_REG00_EFUSE_REG_CLK_GATING BIT(5) +#define AC300_REG00_EPHY_REG_CLK_GATING BIT(4) +#define AC300_REG00_MDIO_ERROR BIT(3) +#define AC300_REG00_CLKIN_GATING BIT(2) +#define AC300_REG00_EPHY_RESET_INVALID BIT(1) +#define AC300_REG00_CHIP_RESET BIT(0) + +#define AC300_REG01_DEFAULT 0x1084 +#define AC300_REG01_BGTC_MASK GENMASK(12, 8) +#define AC300_REG01_BG_EN BIT(7) +#define AC300_REG01_BGV_MASK GENMASK(5, 0) + +#define AC300_REG02_DEFAULT 0xC000 +#define AC300_REG02_DLDOEN BIT(15) +#define AC300_REG02_DLDOVOL_MASK GENMASK(14, 12) + +#define AC300_REG05_DEFAULT 0xA800 +#define AC300_REG05_MDIO_DRV_MASK GENMASK(15, 14) +#define AC300_REG05_LED_DRV_MASK GENMASK(13, 12) +#define AC300_REG05_MII_DRV_MASK GENMASK(11, 10) +#define AC300_REG05_EPHY_IRQ_STATUS BIT(9) +#define AC300_REG05_EPHY_IRQ_ENABLE BIT(8) +#define AC300_REG05_CLKIN_PAD_EN BIT(4) +#define AC300_REG05_E_DPX_LED_IO_EN BIT(3) +#define AC300_REG05_E_SPD_LED_IO_EN BIT(2) +#define AC300_REG05_E_LNK_LED_IO_EN BIT(1) +#define AC300_REG05_EPHY_MII_IO_EN BIT(0) + +#define AC300_REG06_DEFAULT 0x0001 +#define AC300_REG06_BGS_EFUSE_MASK GENMASK(15, 12) +#define AC300_REG06_XMII_SEL BIT(11) +#define AC300_REG06_EPHY_MODE_MASK GENMASK(10, 9) +#define AC300_REG06_BIST_CLK_EN BIT(3) +#define AC300_REG06_LED_POL BIT(1) +#define AC300_REG06_SHUTDOWN BIT(0) + +struct ac300_phy_priv { + struct clk *ephy_clk; + struct clk *pwm_clk; + u16 caldata; +}; + +static int ac300_phy_disable(struct phy_device *phydev) +{ + struct mii_bus *bus = phydev->mdio.bus; + int cfg_addr = 16 + phydev->mdio.addr; + u16 val; + int ret; + + val = 0x1f00 | FIELD_PREP(AC300_REG00_EPHY_CLK_SEL_MASK, AC300_REG00_EPHY_CLK_SEL_24M); + ret = mdiobus_write(bus, cfg_addr, 0x00, val); + if (ret) + return ret; + + ret = mdiobus_write(bus, cfg_addr, 0x05, AC300_REG05_DEFAULT); + if (ret) + return ret; + + return mdiobus_write(bus, cfg_addr, 0x06, AC300_REG06_SHUTDOWN); +} + +static int ac300_phy_enable(struct phy_device *phydev) +{ + struct ac300_phy_priv *priv = phydev->priv; + struct mii_bus *bus = phydev->mdio.bus; + int cfg_addr = 16 + phydev->mdio.addr; + u16 val; + int ret; + + /* Step 1: release reset */ + val = 0x1f00 | FIELD_PREP(AC300_REG00_EPHY_CLK_SEL_MASK, AC300_REG00_EPHY_CLK_SEL_24M) | + AC300_REG00_EPHY_RESET_INVALID | AC300_REG00_CHIP_RESET; + ret = mdiobus_write(bus, cfg_addr, 0x00, val); + if (ret) + return ret; + usleep_range(10000, 11000); + + /* Step 2: clk gating */ + val |= AC300_REG00_EPHY_REG_CLK_GATING | AC300_REG00_CLKIN_GATING | + AC300_REG00_EFUSE_REG_CLK_GATING; + ret = mdiobus_write(bus, cfg_addr, 0x00, val); + if (ret) + return ret; + usleep_range(10000, 11000); + + /* Step 2.5: Apply System BIAS Calibration */ + val = AC300_REG01_DEFAULT; + if (priv->caldata) + val = (priv->caldata & (AC300_REG01_BGTC_MASK | AC300_REG01_BGV_MASK)); + val |= AC300_REG01_BG_EN; /* Ensure Bandgap is enabled */ + ret = mdiobus_write(bus, cfg_addr, 0x01, val); + if (ret) + return ret; + usleep_range(10000, 11000); + + /* Step 3: SYS_IO setup */ + val = AC300_REG05_DEFAULT | AC300_REG05_CLKIN_PAD_EN | + AC300_REG05_EPHY_MII_IO_EN | AC300_REG05_E_DPX_LED_IO_EN; + ret = mdiobus_write(bus, cfg_addr, 0x05, val); + if (ret) + return ret; + usleep_range(10000, 11000); + + /* Step 4: RMII Mode, SHUTDOWN=0, calibration & LED polarity */ + val = 0; + if (phydev->interface == PHY_INTERFACE_MODE_RMII) + val |= AC300_REG06_XMII_SEL; + val |= AC300_REG06_LED_POL; /* LED_POL 1:Low active */ + val &= ~(0x0F << 12); + val |= (0x0F & (0x03 + priv->caldata)) << 12; + ret = mdiobus_write(bus, cfg_addr, 0x06, val); + if (ret) + return ret; + msleep(100); + + return 0; +} + +static int ac300_phy_config_init(struct phy_device *phydev) +{ + struct ac300_phy_priv *priv = phydev->priv; + int ret; + + /* Write page-based EPHY transceiver and signal path optimizations */ + ret = phy_write(phydev, 0x1f, 0x0100); /* Switch to Page 1 */ + if (ret) + return ret; + ret = phy_write(phydev, 0x12, 0x4824); /* Disable APS */ + if (ret) + return ret; + + ret = phy_write(phydev, 0x1f, 0x0200); /* Switch to Page 2 */ + if (ret) + return ret; + ret = phy_write(phydev, 0x18, 0x0000); /* PHYAFE TRX optimization */ + if (ret) + return ret; + + ret = phy_write(phydev, 0x1f, 0x0600); /* Switch to Page 6 */ + if (ret) + return ret; + if (priv->caldata & BIT(9)) { + ret = phy_write(phydev, 0x14, 0x7809); /* Fixed TX optimization */ + if (ret) + return ret; + ret = phy_write(phydev, 0x13, 0xf000); /* Fixed RX optimization */ + if (ret) + return ret; + ret = phy_write(phydev, 0x10, 0x5523); + if (ret) + return ret; + ret = phy_write(phydev, 0x15, 0x3533); + if (ret) + return ret; + } else { + ret = phy_write(phydev, 0x14, 0x708b); /* Default TX optimization */ + if (ret) + return ret; + ret = phy_write(phydev, 0x13, 0xF000); /* Default RX optimization */ + if (ret) + return ret; + ret = phy_write(phydev, 0x15, 0x1530); + if (ret) + return ret; + } + + ret = phy_write(phydev, 0x1f, 0x0800); /* Switch to Page 8 */ + if (ret) + return ret; + if (priv->caldata & BIT(9)) { + ret = phy_write(phydev, 0x1d, 0x0844); /* disable auto offset */ + if (ret) + return ret; + } + ret = phy_write(phydev, 0x18, 0x00bc); /* PHYAFE TRX optimization */ + if (ret) + return ret; + + ret = phy_write(phydev, 0x1f, 0x0100); /* Switch to page 1 */ + if (ret) + return ret; + ret = phy_clear_bits(phydev, 0x17, BIT(3)); /* Disable Intelligent EEE */ + if (ret) + return ret; + + /* Disable 802.3az EEE */ + ret = phy_write(phydev, 0x1f, 0x0200); /* Switch to page 2 */ + if (ret) + return ret; + ret = phy_write(phydev, 0x18, 0x0000); + if (ret) + return ret; + ret = phy_write(phydev, 0x1f, 0x0000); /* Switch to page 0 */ + if (ret) + return ret; + + return phy_clear_bits_mmd(phydev, 0x7, 0x3c, BIT(1)); +} + +static int ac300_phy_probe(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct ac300_phy_priv *priv; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + phydev->priv = priv; + + priv->ephy_clk = devm_clk_get_optional_enabled(dev, "ephy"); + if (IS_ERR(priv->ephy_clk)) + return dev_err_probe(dev, PTR_ERR(priv->ephy_clk), + "Failed to request ephy clock\n"); + + priv->pwm_clk = devm_clk_get_optional_enabled(dev, "pwm"); + if (IS_ERR(priv->pwm_clk)) + return dev_err_probe(dev, PTR_ERR(priv->pwm_clk), + "Failed to request pwm clock\n"); + + /* Read calibration data from NVMEM/SID */ + ret = nvmem_cell_read_u16(dev, "calibration", &priv->caldata); + if (ret) { + if (ret == -EPROBE_DEFER) + return -EPROBE_DEFER; + dev_warn(dev, "Failed to read EPHY calibration (%pe)\n", ERR_PTR(ret)); + } else { + dev_info(dev, "Read AC300 EPHY calibration: 0x%04x\n", priv->caldata); + } + + return ac300_phy_enable(phydev); +} + +static void ac300_phy_remove(struct phy_device *phydev) +{ + ac300_phy_disable(phydev); +} + +static int ac300_phy_suspend(struct phy_device *phydev) +{ + int ret; + + ret = ac300_phy_disable(phydev); + if (ret) + return ret; + return genphy_suspend(phydev); +} + +static int ac300_phy_resume(struct phy_device *phydev) +{ + int ret; + + ret = ac300_phy_enable(phydev); + if (ret) + return ret; + return genphy_resume(phydev); +} + +static int ac300_phy_soft_reset(struct phy_device *phydev) +{ + int ret; + + ret = ac300_phy_enable(phydev); + if (ret) + return ret; + return genphy_soft_reset(phydev); +} + +static int ac300_phy_match_phy_device(struct phy_device *phydev, + const struct phy_driver *phydrv) +{ + return of_device_is_compatible(phydev->mdio.dev.of_node, + "allwinner,sun50i-h618-ac300-ephy"); +} + +static struct phy_driver ac300_phy_driver[] = { + { + .phy_id = AC300_EPHY_ID, + .phy_id_mask = AC300_EPHY_ID_MASK, + .name = "Allwinner AC300 EPHY", + .features = PHY_BASIC_FEATURES, + .match_phy_device = ac300_phy_match_phy_device, + .soft_reset = ac300_phy_soft_reset, + .config_init = ac300_phy_config_init, + .probe = ac300_phy_probe, + .remove = ac300_phy_remove, + .suspend = ac300_phy_suspend, + .resume = ac300_phy_resume, + } +}; +module_phy_driver(ac300_phy_driver); + +MODULE_AUTHOR("Alastair D'Silva "); +MODULE_DESCRIPTION("X-Powers AC300 Ethernet PHY driver"); +MODULE_LICENSE("GPL"); + +static const struct mdio_device_id __maybe_unused ac300_phy_tbl[] = { + { AC300_EPHY_ID, AC300_EPHY_ID_MASK }, + { } +}; +MODULE_DEVICE_TABLE(mdio, ac300_phy_tbl); From patchwork Wed Sep 16 04:41:18 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alastair D'Silva X-Patchwork-Id: 3373 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 3AD2A1C2BF8 for ; Wed, 16 Sep 2026 06:45:03 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=d-silva.org; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-25976-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; envelope-from=linux-sunxi+bounces-25976-noreply=patchwork.local@lists.linux.dev; helo=sea.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sea.lore.kernel.org (Postfix) with ESMTP id 733E541AB5 for ; Wed, 16 Sep 2026 04:41:59 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3360136B910; Wed, 16 Sep 2026 04:41:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=d-silva.org header.i=@d-silva.org header.b="pc4HvCwe" X-Original-To: linux-sunxi@lists.linux.dev Received: from www.nmnhosting.com (watt.d-silva.org [119.15.109.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F7FF1BD9D0 for ; Wed, 16 Sep 2026 04:41:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=119.15.109.137 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789533719; cv=none; b=mYxrz8rFj0SnXqfJed54ioj8CMqWuEtnIrn/6MOFIjkQ5hAPE4cPrJLtLqKP7xIVX2lwjKi8k0c155zUwVcds9GA8+Fhcp7xD7ZXGn9J6LXVtW3l53dgF7Ssi3wd0PX5UdJK1vdTC/o0m8sRfzqaNG+w/ITKEtNgegSxn27/WV8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789533719; c=relaxed/simple; bh=QQ4Rx0RKXeD+Mgg6OnjaTMpWCTRfWxOZGJ9jQAQSPlc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=esGPJdjeaEdtEwKmZaQIzQpRosU1iH7rMm1oZ2fO1MDs2AZ1p+5zqdJrYaJaXSsQgKMAzbAyiWYeeH6SzEjjQLl/2wblmEjvM3E4qOviEC7TTNq51jspEo9LiSm2no7EI9BN9mxm6RsXDsWXbIf9Hmqade+iaMK2dr3OGUa1Cxc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=d-silva.org; spf=pass smtp.mailfrom=d-silva.org; dkim=pass (2048-bit key) header.d=d-silva.org header.i=@d-silva.org header.b=pc4HvCwe; arc=none smtp.client-ip=119.15.109.137 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=d-silva.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=d-silva.org Received: from Hawking.lan (hawking.lan [10.0.1.4]) by www.nmnhosting.com (Postfix) with ESMTP id A3BE543BC8; Wed, 16 Sep 2026 14:41:47 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=d-silva.org; s=2025a; t=1789533707; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=z+VOksxVxl1n9pVJKF/iIgS3rOWKCiVngYTFNCP+Fq4=; b=pc4HvCweIVrkeCspTViACRKJL/iO6fNRNRnrpQRkg4Vxx5pOP3Ve1IeAnVK0T7s7OHnBmn y654KnCD7ZcygtHjQ1/pYyMJ4wydZFBMW5GqOVNXy5gDXVl1V2ATjiJK5FBilrcrLVpJ+1 jipxHgsr5G09FqzaCwV5rMgsWfOH5ADrUehiSjLPNPs9nLKhZsa4Uw+G7Rcd24XoctrwOB Xu79Dqi1fn+nNwhY0eWIjAELI8k/Kzd6JCfw8dLrBcJvkmPhLDDgKJD4VJ614eEPn25h/a tol3mAi0lbeHUdL+olwOpKj+ALyjkyM6MJ9kGxzYYGt0spwzIR+IB1LE2gDzLA== X-GPT-Reason: legitimate; the email is a technical "patch" notification regarding Linux kernel devicetree bindings, which aligns with the personal/professional context of the recipient and sender (alastair@d-silva.org); the From domain matches the sender's identity; the content is highly specific technical documentation (YAML schema updates) with no marketing, urgency, or phishing indicators; and there are no suspicious links or requests for sensitive information. From: Alastair D'Silva To: Andrew Lunn , Heiner Kallweit , Russell King , Alexandre Torgue , Maxime Chevallier , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Alastair D'Silva Subject: [PATCH net-next 3/4] dt-bindings: net: allwinner,sun8i-a83t-emac: Add Allwinner H616 EMAC1 and syscon index Date: Wed, 16 Sep 2026 14:41:18 +1000 Message-ID: <20260916044119.475666-4-alastair@d-silva.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260916044119.475666-1-alastair@d-silva.org> References: <20260916044119.475666-1-alastair@d-silva.org> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Document the Allwinner H616 EMAC1 and internal EMAC compatible strings ("allwinner,sun50i-h616-emac1" and "allwinner,sun50i-h616-internal-emac"). Update the syscon property schema to support an optional register index offset argument, allowing boards to reference the secondary EMAC clock register on H616/H618 SoCs. Assisted-by: LLM Signed-off-by: Alastair D'Silva --- Notes: Tested against Allwinner H616/H618 device trees in Armbian, verifying schema validation with dt_binding_check. .../bindings/net/allwinner,sun8i-a83t-emac.yaml | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml index 323a669fa982..cd1075dab581 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -39,6 +39,8 @@ properties: - allwinner,sun50i-a100-emac - allwinner,sun50i-h6-emac - allwinner,sun50i-h616-emac0 + - allwinner,sun50i-h616-emac1 + - allwinner,sun50i-h616-internal-emac - allwinner,sun55i-a523-gmac0 - const: allwinner,sun50i-a64-emac - items: @@ -71,10 +73,16 @@ properties: maxItems: 1 syscon: - $ref: /schemas/types.yaml#/definitions/phandle + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - minItems: 1 + maxItems: 2 + items: + - description: Phandle to the device containing the EMAC or GMAC clock register + - description: Register index offset (0 for EMAC0, 1 for EMAC1) description: - Phandle to the device containing the EMAC or GMAC clock - register + Phandle to the device containing the EMAC or GMAC clock register, + with an optional register index (0 for EMAC0, 1 for EMAC1). required: - compatible From patchwork Wed Sep 16 04:41:19 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alastair D'Silva X-Patchwork-Id: 3370 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sto.lore.kernel.org (sto.lore.kernel.org [172.232.135.74]) by mxe881.netcup.net (Postfix) with ESMTPS id CF1E41C1FF4 for ; Wed, 16 Sep 2026 06:42:10 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=d-silva.org; spf=pass (sender IP is 172.232.135.74) smtp.mailfrom=linux-sunxi+bounces-25977-noreply=patchwork.local@lists.linux.dev smtp.helo=sto.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.232.135.74 as permitted sender) client-ip=172.232.135.74; envelope-from=linux-sunxi+bounces-25977-noreply=patchwork.local@lists.linux.dev; helo=sto.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sto.lore.kernel.org (Postfix) with ESMTP id EFA4560AAED for ; Wed, 16 Sep 2026 04:42:08 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4AAA53A2E2E; Wed, 16 Sep 2026 04:42:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=d-silva.org header.i=@d-silva.org header.b="k8nOuG05" X-Original-To: linux-sunxi@lists.linux.dev Received: from www.nmnhosting.com (watt.d-silva.org [119.15.109.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 741521BD9D0 for ; Wed, 16 Sep 2026 04:42:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=119.15.109.137 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789533728; cv=none; b=h8SfVq/6p9lFTU/wDxFOG/jXctPaY03B2cQFN0RfP66YGU4LOBqADIV70ZpS0fvhOfBQMNUWIJ+oOI8vLjY4HiTlDp0CpraKbUaLORdX8BKMSeCCOdNe2MIKvuOpcEW2wZ+72NXcj1JFus32MlfC5cylSIVfGMqDWm8XCjy235Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789533728; c=relaxed/simple; bh=XB2VFwMX8lLgGoB9hByOvLGI1Lo6AfMSPcEBL9X0adY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RdxbhHiR/ZGv+s9X2+1UCnnlVIjzvjIZWIJEwSED/14Aja589pxYBdDlpybLk0akmjQTErm0RBgqmAXHTlIjn0J1nQ8eshHEeQUFblvp8Ox993WFp8Hr02QDDarzZW/r1eR1TCtS4mbOv8UkPL1R+wcMjCtXgibQFAGz3aJJNXI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=d-silva.org; spf=pass smtp.mailfrom=d-silva.org; dkim=pass (2048-bit key) header.d=d-silva.org header.i=@d-silva.org header.b=k8nOuG05; arc=none smtp.client-ip=119.15.109.137 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=d-silva.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=d-silva.org Received: from Hawking.lan (hawking.lan [10.0.1.4]) by www.nmnhosting.com (Postfix) with ESMTP id 6A10443BD0; Wed, 16 Sep 2026 14:41:55 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=d-silva.org; s=2025a; t=1789533715; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YF/1pjayfOlwmv8drW2kZBXUotBXt7gAJUwr6YSztco=; b=k8nOuG05Z+CeUrqH2ZSIqdlJmph3gWW3orj/DZdoNJlTJMAYQjT5UEPAK/1+Ij7LxVqni/ SkfcGj58RTHYg4SMGaaRf5Xl1nd6OFiWu3qr9Ttnf0w06sZ1ZZLLpDA87RFfvYHAw4TzPX ehIpEtU1cYyZ6LzqEBxn+JmEXKNQs+5B+16TSyGTN4sgHRxDXdc4/X2XGzhIaQAUNJBMI4 qSip0kFU7tXOPPPBZoa+N5dOAyK9bXGZmhKoEH9jUwTvWj9gl4IGuA77duHIo88tslJEdV oDXjmNmW6TDuNZzOg+QpwQWDOMrlK4smcMpxmjbejxZHs/txuQgWqCQC/2bcZQ== X-GPT-Reason: legitimate_transactional_technical_patch_submission_The email is a technical kernel patch submission for the Linux kernel (net-next), which perfectly aligns with the personal/professional context of the alastair@d-silva.org mailbox. The From domain matches the signature and content, and the body consists of a standard git diff and technical notes regarding the Allwinner H616 EMAC clock index. There are no phishing indicators, no external links, and no urgency/scare tactics. From: Alastair D'Silva To: Andrew Lunn , Heiner Kallweit , Russell King , Alexandre Torgue , Maxime Chevallier , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Alastair D'Silva Subject: [PATCH net-next 4/4] net: stmmac: dwmac-sun8i: Add Allwinner H616 EMAC clock index and internal PHY support Date: Wed, 16 Sep 2026 14:41:19 +1000 Message-ID: <20260916044119.475666-5-alastair@d-silva.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260916044119.475666-1-alastair@d-silva.org> References: <20260916044119.475666-1-alastair@d-silva.org> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Support EMAC1 and the internal Fast Ethernet PHY (AC300) on Allwinner H616 and H618 SoCs: - Allow reading a register index from the syscon property to offset the regmap field for EMAC1's dedicated clock control register. - Add emac_variant_h616_internal with support for internal PHY, MII, RMII, and RGMII modes. - Delay the MAC software reset until sun8i_dwmac_init() when using the internal PHY, ensuring the PHY has powered on and begun generating the receive clock before the MAC attempts to reset. - Skip setting H3_EPHY_SELECT for H616 internal EMAC, which does not use the H3-style EPHY select bit. - Handle -EPROBE_DEFER cleanly during clock and reset control acquisition in get_ephy_nodes(). Assisted-by: LLM Signed-off-by: Alastair D'Silva --- Notes: Tested on Mellow Fly-C5 (Allwinner H618) under Armbian, verifying stable EMAC1 probe, deferred soft reset with the internal AC300 EPHY, and 100M full duplex operation under load. .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 65 ++++++++++++++++--- 1 file changed, 55 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index 48c52eb96233..1728893589a6 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -130,6 +130,16 @@ static const struct emac_variant emac_variant_a64 = { .tx_delay_max = 7, }; +static const struct emac_variant emac_variant_h616_internal = { + .syscon_field = &sun8i_syscon_reg_field, + .soc_has_internal_phy = true, + .support_mii = true, + .support_rmii = true, + .support_rgmii = true, + .rx_delay_max = 31, + .tx_delay_max = 7, +}; + static const struct emac_variant emac_variant_h6 = { .syscon_field = &sun8i_syscon_reg_field, /* The "Internal PHY" of H6 is not on the die. It's on the @@ -570,6 +580,7 @@ static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = { }; static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv); +static int sun8i_dwmac_reset(struct stmmac_priv *priv); static int sun8i_dwmac_init(struct device *dev, void *priv) { @@ -589,6 +600,10 @@ static int sun8i_dwmac_init(struct device *dev, void *priv) ret = sun8i_dwmac_power_internal_phy(netdev_priv(ndev)); if (ret) goto err_disable_regulator; + + ret = sun8i_dwmac_reset(netdev_priv(ndev)); + if (ret) + goto err_disable_regulator; } return 0; @@ -784,16 +799,23 @@ static int get_ephy_nodes(struct stmmac_priv *priv) /* Seek for internal PHY */ for_each_child_of_node_scoped(mdio_internal, iphynode) { gmac->ephy_clk = of_clk_get(iphynode, 0); - if (IS_ERR(gmac->ephy_clk)) - continue; + if (IS_ERR(gmac->ephy_clk)) { + ret = PTR_ERR(gmac->ephy_clk); + if (ret == -EPROBE_DEFER) { + of_node_put(mdio_internal); + return ret; + } + gmac->ephy_clk = NULL; + } gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL); if (IS_ERR(gmac->rst_ephy)) { ret = PTR_ERR(gmac->rst_ephy); if (ret == -EPROBE_DEFER) { + clk_put(gmac->ephy_clk); of_node_put(mdio_internal); return ret; } - continue; + gmac->rst_ephy = NULL; } dev_info(priv->device, "Found internal PHY node\n"); of_node_put(mdio_internal); @@ -871,7 +893,9 @@ static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, switch (desired_child) { case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID: dev_info(priv->device, "Switch mux to internal PHY"); - val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; + val = (reg & ~H3_EPHY_MUX_MASK); + if (gmac->variant != &emac_variant_h616_internal) + val |= H3_EPHY_SELECT; gmac->use_internal_phy = true; break; case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID: @@ -892,10 +916,13 @@ static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, } else { sun8i_dwmac_unpower_internal_phy(gmac); } - /* After changing syscon value, the MAC need reset or it will + /* After changing syscon value, the MAC needs reset or it will * use the last value (and so the last PHY set). + * For internal PHY, the MAC reset will timeout because the PHY + * is not yet enabled/clocked. Delay the reset to dwmac_init. */ - ret = sun8i_dwmac_reset(priv); + if (!gmac->use_internal_phy) + ret = sun8i_dwmac_reset(priv); } return ret; } @@ -1000,9 +1027,13 @@ static int sun8i_dwmac_set_syscon(struct device *dev, static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) { - if (gmac->variant->soc_has_internal_phy) - regmap_field_write(gmac->regmap_field, - (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT)); + if (gmac->variant->soc_has_internal_phy) { + u32 val = H3_EPHY_SHUTDOWN; + + if (gmac->variant != &emac_variant_h616_internal) + val |= H3_EPHY_SELECT; + regmap_field_write(gmac->regmap_field, val); + } } static void sun8i_dwmac_exit(struct device *dev, void *priv) @@ -1111,6 +1142,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) struct stmmac_priv *priv; struct net_device *ndev; struct regmap *regmap; + u32 syscon_idx = 0; int ret; ret = stmmac_get_platform_resources(pdev, &stmmac_res); @@ -1163,8 +1195,15 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) return ret; } + ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, + &syscon_idx); gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, - *gmac->variant->syscon_field); + (const struct reg_field) { + .reg = gmac->variant->syscon_field->reg + + syscon_idx * sizeof(u32), + .lsb = gmac->variant->syscon_field->lsb, + .msb = gmac->variant->syscon_field->msb, + }); if (IS_ERR(gmac->regmap_field)) { ret = PTR_ERR(gmac->regmap_field); dev_err(dev, "Unable to map syscon register: %d\n", ret); @@ -1278,6 +1317,12 @@ static const struct of_device_id sun8i_dwmac_match[] = { .data = &emac_variant_a64 }, { .compatible = "allwinner,sun50i-h6-emac", .data = &emac_variant_h6 }, + { .compatible = "allwinner,sun50i-h616-emac", + .data = &emac_variant_h6 }, + { .compatible = "allwinner,sun50i-h616-emac1", + .data = &emac_variant_h6 }, + { .compatible = "allwinner,sun50i-h616-internal-emac", + .data = &emac_variant_h616_internal }, { } }; MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);