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Mon, 21 Sep 2026 20:47:33 -0700 (PDT) Received: from hp ([71.12.40.102]) by smtp.gmail.com with ESMTPSA id 00721157ae682-8a2bd79e82bsm1822337b3.5.2026.09.21.20.47.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2026 20:47:33 -0700 (PDT) From: Tim Michals To: linux-sunxi@lists.linux.dev Cc: wens@kernel.org, jernej.skrabec@gmail.com, samuel@sholland.org, Tim Michals , Jassi Brar , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/7] dt-bindings: mailbox: add Allwinner sun55i msgbox schema Date: Mon, 21 Sep 2026 22:47:05 -0500 Message-ID: <20260922034711.190253-2-tcmichals@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260922034711.190253-1-tcmichals@gmail.com> References: <20260922034711.190253-1-tcmichals@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Add Device Tree binding schema for the Allwinner 4-port hardware Message Box controller found on sun55i (A523, A527, T527) and sun60i (A733) SoCs. The message box connects the ARM Cortex-A55 host cluster to the HiFi4 Audio DSP, Power Management Unit (CPUS), and XuanTie RISC-V co-processor across 12 logical channels with 8-entry hardware FIFOs. Cc: Jassi Brar Cc: Samuel Holland Cc: Jernej Skrabec Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-sunxi@lists.linux.dev Signed-off-by: Tim Michals --- .../mailbox/allwinner,sun55i-a523-msgbox.yaml | 93 +++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/allwinner,sun55i-a523-msgbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/allwinner,sun55i-a523-msgbox.yaml b/Documentation/devicetree/bindings/mailbox/allwinner,sun55i-a523-msgbox.yaml new file mode 100644 index 000000000000..4b73543c7902 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/allwinner,sun55i-a523-msgbox.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/allwinner,sun55i-a523-msgbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner sun55i 4-Port Message Box + +maintainers: + - Tim Michals + - Samuel Holland + +description: | + The hardware message box on sun55i (A523, A527, T527) and sun60i (A733) + SoCs is a 4-port multi-processor mailbox controller connecting the ARM + Cortex-A55 host cluster, HiFi4 Audio DSP, Power Management Unit (CPUS), + and XuanTie RISC-V co-processor. + + It features independent 256-byte register banks for each processor port, + 12 logical channels on the host (4 per remote processor), and 8-entry + hardware FIFOs with level interrupts. + +properties: + compatible: + enum: + - allwinner,sun55i-a523-msgbox + - allwinner,sun55i-t527-msgbox + - allwinner,sun60i-a733-msgbox + + reg: + minItems: 4 + maxItems: 4 + description: | + Register banks for each of the four processor ports. Each port has + an independent 256-byte register bank. + + reg-names: + items: + - const: arm + - const: dsp + - const: cpus + - const: rv + + clocks: + maxItems: 1 + description: bus clock + + resets: + maxItems: 1 + description: bus reset + + interrupts: + minItems: 1 + maxItems: 4 + description: | + One interrupt per processor port. The host port interrupt is required; + remote port interrupts are optional. + + '#mbox-cells': + const: 1 + description: "channel number (0-11: 0-3 CPUS, 4-7 DSP, 8-11 RISC-V)" + +required: + - compatible + - reg + - reg-names + - clocks + - resets + - interrupts + - '#mbox-cells' + +additionalProperties: false + +examples: + - | + #include + + mailbox@3003000 { + compatible = "allwinner,sun55i-a523-msgbox"; + reg = <0x03003000 0x1000>, + <0x07094000 0x1000>, + <0x07120000 0x1000>, + <0x07136000 0x1000>; + reg-names = "arm", "dsp", "cpus", "rv"; + clocks = <&ccu 120>; + resets = <&ccu 45>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + }; + From patchwork Tue Sep 22 03:47:06 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Michals X-Patchwork-Id: 3421 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114]) by mxe881.netcup.net (Postfix) with ESMTPS id 457F31C02E9 for ; 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RCPT_COUNT_SEVEN(0.00)[8]; MIME_TRACE(0.00)[0:+]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; ASN(0.00)[asn:63949, ipnet:172.105.96.0/20, country:SG]; RCVD_TLS_LAST(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 457F31C02E9 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Add support for the 4-port hardware Message Box present on Allwinner A523/A527/T527 (sun55i) and A733 (sun60i) SoCs. This hardware block provides 12 hardware FIFO channels connecting the Cortex-A55 host, HiFi4 DSP, CPUS, and XuanTie E907 RISC-V coprocessors. Cc: Samuel Holland Cc: Jernej Skrabec Cc: Chen-Yu Tsai Cc: Jassi Brar Cc: linux-sunxi@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Tim Michals --- drivers/mailbox/Kconfig | 10 + drivers/mailbox/Makefile | 2 + drivers/mailbox/sun55i-msgbox.c | 337 ++++++++++++++++++++++++++++++++ 3 files changed, 349 insertions(+) create mode 100644 drivers/mailbox/sun55i-msgbox.c diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index ab869769e278..9067f5161276 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -332,6 +332,16 @@ config SUN6I_MSGBOX various Allwinner SoCs. This mailbox is used for communication between the application CPUs and the power management coprocessor. +config SUN55I_MSGBOX + tristate "Allwinner sun55i/sun60i 4-port Message Box" + depends on ARCH_SUNXI || COMPILE_TEST + default ARCH_SUNXI + help + Mailbox implementation for the 4-port hardware message box present in + Allwinner A523/A527/T527 (sun55i) and A733 (sun60i) SoCs. This mailbox + provides 12 hardware FIFO channels for communication between the + Cortex-A55 host, CPUS, HiFi4 DSP, and XuanTie E907 RISC-V coprocessors. + config SPRD_MBOX tristate "Spreadtrum Mailbox" depends on ARCH_SPRD || COMPILE_TEST diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 45dc59bb3e7f..40024aa906a6 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -71,6 +71,8 @@ obj-$(CONFIG_ZYNQMP_IPI_MBOX) += zynqmp-ipi-mailbox.o obj-$(CONFIG_SUN6I_MSGBOX) += sun6i-msgbox.o +obj-$(CONFIG_SUN55I_MSGBOX) += sun55i-msgbox.o + obj-$(CONFIG_SPRD_MBOX) += sprd-mailbox.o obj-$(CONFIG_QCOM_CPUCP_MBOX) += qcom-cpucp-mbox.o diff --git a/drivers/mailbox/sun55i-msgbox.c b/drivers/mailbox/sun55i-msgbox.c new file mode 100644 index 000000000000..b36f26670a46 --- /dev/null +++ b/drivers/mailbox/sun55i-msgbox.c @@ -0,0 +1,337 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Allwinner sun55i/sun60i 4-Port Hardware Message Box Driver + * + * Copyright (C) 2026 Tim Michals + * Based on vendor sunxi-msgbox driver by Allwinner Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SUN55I_MAX_PROCESSORS 4 +#define SUN55I_CHANS_PER_PROC 4 +#define SUN55I_NUM_CHANS ((SUN55I_MAX_PROCESSORS - 1) * SUN55I_CHANS_PER_PROC) +#define SUN55I_FIFO_MAX 8 + +#define SUNXI_MSGBOX_OFFSET(n) (0x100 * (n)) +#define SUNXI_MSGBOX_READ_IRQ_ENABLE(n) (0x020 + SUNXI_MSGBOX_OFFSET(n)) +#define SUNXI_MSGBOX_READ_IRQ_STATUS(n) (0x024 + SUNXI_MSGBOX_OFFSET(n)) +#define SUNXI_MSGBOX_WRITE_IRQ_ENABLE(n) (0x030 + SUNXI_MSGBOX_OFFSET(n)) +#define SUNXI_MSGBOX_WRITE_IRQ_STATUS(n) (0x034 + SUNXI_MSGBOX_OFFSET(n)) +#define SUNXI_MSGBOX_FIFO_STATUS(n, p) (0x050 + SUNXI_MSGBOX_OFFSET(n) + 0x4 * (p)) +#define SUNXI_MSGBOX_MSG_STATUS(n, p) (0x060 + SUNXI_MSGBOX_OFFSET(n) + 0x4 * (p)) +#define SUNXI_MSGBOX_MSG_FIFO(n, p) (0x070 + SUNXI_MSGBOX_OFFSET(n) + 0x4 * (p)) + +#define RD_IRQ_EN_BIT(p) BIT((p) * 2) +#define RD_IRQ_PEND_BIT(p) BIT((p) * 2) +#define MSG_NUM_MASK GENMASK(3, 0) + +struct sun55i_route { + u8 remote_id; + u8 remote_n; +}; + +/* + * Hardware routing table for Cortex-A55 host (local_id = 0): + * local_n = 0 -> CPUS (remote_id = 2, remote_n = 0) -> Channels 0..3 + * local_n = 1 -> DSP (remote_id = 1, remote_n = 0) -> Channels 4..7 + * local_n = 2 -> RV (remote_id = 3, remote_n = 2) -> Channels 8..11 + */ +static const struct sun55i_route arm_routes[3] = { + [0] = { .remote_id = 2, .remote_n = 0 }, + [1] = { .remote_id = 1, .remote_n = 0 }, + [2] = { .remote_id = 3, .remote_n = 2 }, +}; + +struct sun55i_msgbox { + struct mbox_controller controller; + void __iomem *regs[SUN55I_MAX_PROCESSORS]; + struct clk *clk; + struct reset_control *reset; + /* Protects concurrent MMIO register access */ + spinlock_t lock; +}; + +static inline struct sun55i_msgbox *to_sun55i_msgbox(struct mbox_chan *chan) +{ + return chan->con_priv; +} + +static inline void sun55i_chan_to_route(int chan_idx, int *local_n, int *p, + int *remote_id, int *remote_n) +{ + *local_n = chan_idx / SUN55I_CHANS_PER_PROC; + *p = chan_idx % SUN55I_CHANS_PER_PROC; + *remote_id = arm_routes[*local_n].remote_id; + *remote_n = arm_routes[*local_n].remote_n; +} + +static irqreturn_t sun55i_msgbox_irq(int irq, void *dev_id) +{ + struct sun55i_msgbox *mbox = dev_id; + irqreturn_t ret = IRQ_NONE; + int local_n, p, chan_idx; + + for (local_n = 0; local_n < 3; local_n++) { + void __iomem *local_base = mbox->regs[0]; + u32 en, stat, pending; + + en = readl(local_base + SUNXI_MSGBOX_READ_IRQ_ENABLE(local_n)); + stat = readl(local_base + SUNXI_MSGBOX_READ_IRQ_STATUS(local_n)); + pending = en & stat; + + if (!pending) + continue; + + for (p = 0; p < SUN55I_CHANS_PER_PROC; p++) { + if (!(pending & RD_IRQ_PEND_BIT(p))) + continue; + + chan_idx = local_n * SUN55I_CHANS_PER_PROC + p; + while (readl(local_base + + SUNXI_MSGBOX_MSG_STATUS(local_n, p)) & MSG_NUM_MASK) { + u32 msg = readl(local_base + SUNXI_MSGBOX_MSG_FIFO(local_n, p)); + + mbox_chan_received_data(&mbox->controller.chans[chan_idx], &msg); + } + + writel(RD_IRQ_PEND_BIT(p), + local_base + SUNXI_MSGBOX_READ_IRQ_STATUS(local_n)); + ret = IRQ_HANDLED; + } + } + + return ret; +} + +static int sun55i_msgbox_send_data(struct mbox_chan *chan, void *data) +{ + struct sun55i_msgbox *mbox = to_sun55i_msgbox(chan); + int n = chan - mbox->controller.chans; + int local_n, p, remote_id, remote_n; + u32 msg = data ? *(u32 *)data : 0; + + sun55i_chan_to_route(n, &local_n, &p, &remote_id, &remote_n); + + writel(msg, mbox->regs[remote_id] + SUNXI_MSGBOX_MSG_FIFO(remote_n, p)); + return 0; +} + +static int sun55i_msgbox_startup(struct mbox_chan *chan) +{ + struct sun55i_msgbox *mbox = to_sun55i_msgbox(chan); + int n = chan - mbox->controller.chans; + int local_n, p, remote_id, remote_n; + unsigned long flags; + u32 val; + + sun55i_chan_to_route(n, &local_n, &p, &remote_id, &remote_n); + + /* Flush any stale receive data */ + while (readl(mbox->regs[0] + SUNXI_MSGBOX_MSG_STATUS(local_n, p)) & MSG_NUM_MASK) + readl(mbox->regs[0] + SUNXI_MSGBOX_MSG_FIFO(local_n, p)); + + /* Clear pending status */ + writel(RD_IRQ_PEND_BIT(p), + mbox->regs[0] + SUNXI_MSGBOX_READ_IRQ_STATUS(local_n)); + + /* Enable receive IRQ */ + spin_lock_irqsave(&mbox->lock, flags); + val = readl(mbox->regs[0] + SUNXI_MSGBOX_READ_IRQ_ENABLE(local_n)); + val |= RD_IRQ_EN_BIT(p); + writel(val, mbox->regs[0] + SUNXI_MSGBOX_READ_IRQ_ENABLE(local_n)); + spin_unlock_irqrestore(&mbox->lock, flags); + + return 0; +} + +static void sun55i_msgbox_shutdown(struct mbox_chan *chan) +{ + struct sun55i_msgbox *mbox = to_sun55i_msgbox(chan); + int n = chan - mbox->controller.chans; + int local_n, p, remote_id, remote_n; + unsigned long flags; + u32 val; + + sun55i_chan_to_route(n, &local_n, &p, &remote_id, &remote_n); + + /* Disable receive IRQ */ + spin_lock_irqsave(&mbox->lock, flags); + val = readl(mbox->regs[0] + SUNXI_MSGBOX_READ_IRQ_ENABLE(local_n)); + val &= ~RD_IRQ_EN_BIT(p); + writel(val, mbox->regs[0] + SUNXI_MSGBOX_READ_IRQ_ENABLE(local_n)); + spin_unlock_irqrestore(&mbox->lock, flags); + + /* Clear pending status and flush */ + writel(RD_IRQ_PEND_BIT(p), + mbox->regs[0] + SUNXI_MSGBOX_READ_IRQ_STATUS(local_n)); + while (readl(mbox->regs[0] + SUNXI_MSGBOX_MSG_STATUS(local_n, p)) & MSG_NUM_MASK) + readl(mbox->regs[0] + SUNXI_MSGBOX_MSG_FIFO(local_n, p)); +} + +static bool sun55i_msgbox_last_tx_done(struct mbox_chan *chan) +{ + struct sun55i_msgbox *mbox = to_sun55i_msgbox(chan); + int n = chan - mbox->controller.chans; + int local_n, p, remote_id, remote_n; + u32 count; + + sun55i_chan_to_route(n, &local_n, &p, &remote_id, &remote_n); + + count = readl(mbox->regs[remote_id] + SUNXI_MSGBOX_MSG_STATUS(remote_n, p)) & MSG_NUM_MASK; + return count < SUN55I_FIFO_MAX; +} + +static bool sun55i_msgbox_peek_data(struct mbox_chan *chan) +{ + struct sun55i_msgbox *mbox = to_sun55i_msgbox(chan); + int n = chan - mbox->controller.chans; + int local_n, p, remote_id, remote_n; + u32 count; + + sun55i_chan_to_route(n, &local_n, &p, &remote_id, &remote_n); + + count = readl(mbox->regs[0] + SUNXI_MSGBOX_MSG_STATUS(local_n, p)) & MSG_NUM_MASK; + return count > 0; +} + +static const struct mbox_chan_ops sun55i_msgbox_chan_ops = { + .send_data = sun55i_msgbox_send_data, + .startup = sun55i_msgbox_startup, + .shutdown = sun55i_msgbox_shutdown, + .last_tx_done = sun55i_msgbox_last_tx_done, + .peek_data = sun55i_msgbox_peek_data, +}; + +static int sun55i_msgbox_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mbox_chan *chans; + struct sun55i_msgbox *mbox; + int i, ret, irq_cnt, local_n; + + mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + + spin_lock_init(&mbox->lock); + + for (i = 0; i < SUN55I_MAX_PROCESSORS; i++) { + mbox->regs[i] = devm_platform_ioremap_resource(pdev, i); + if (IS_ERR(mbox->regs[i])) + return dev_err_probe(dev, PTR_ERR(mbox->regs[i]), + "failed to map resource %d\n", i); + } + + mbox->clk = devm_clk_get(dev, NULL); + if (IS_ERR(mbox->clk)) + return dev_err_probe(dev, PTR_ERR(mbox->clk), "failed to get clock\n"); + + ret = clk_prepare_enable(mbox->clk); + if (ret) + return dev_err_probe(dev, ret, "failed to enable clock\n"); + + mbox->reset = devm_reset_control_get_optional_shared(dev, NULL); + if (IS_ERR(mbox->reset)) { + ret = PTR_ERR(mbox->reset); + goto err_disable_clk; + } + + ret = reset_control_deassert(mbox->reset); + if (ret) + goto err_disable_clk; + + /* Disable all read IRQs and clear status */ + for (local_n = 0; local_n < 3; local_n++) { + writel(0, mbox->regs[0] + SUNXI_MSGBOX_READ_IRQ_ENABLE(local_n)); + writel(0xffffffff, mbox->regs[0] + SUNXI_MSGBOX_READ_IRQ_STATUS(local_n)); + } + + irq_cnt = platform_irq_count(pdev); + if (irq_cnt < 0) { + ret = irq_cnt; + goto err_disable_clk; + } + + for (i = 0; i < irq_cnt; i++) { + int irq = platform_get_irq(pdev, i); + + if (irq > 0) { + ret = devm_request_irq(dev, irq, sun55i_msgbox_irq, + IRQF_SHARED, dev_name(dev), mbox); + if (ret) + dev_warn(dev, "failed to request irq %d: %d\n", irq, ret); + } + } + + chans = devm_kcalloc(dev, SUN55I_NUM_CHANS, sizeof(*chans), GFP_KERNEL); + if (!chans) { + ret = -ENOMEM; + goto err_disable_clk; + } + + for (i = 0; i < SUN55I_NUM_CHANS; i++) + chans[i].con_priv = mbox; + + mbox->controller.dev = dev; + mbox->controller.ops = &sun55i_msgbox_chan_ops; + mbox->controller.chans = chans; + mbox->controller.num_chans = SUN55I_NUM_CHANS; + mbox->controller.txdone_irq = false; + mbox->controller.txdone_poll = true; + mbox->controller.txpoll_period = 1; + + platform_set_drvdata(pdev, mbox); + + ret = mbox_controller_register(&mbox->controller); + if (ret) { + dev_err_probe(dev, ret, "failed to register controller\n"); + goto err_disable_clk; + } + + return 0; + +err_disable_clk: + clk_disable_unprepare(mbox->clk); + return ret; +} + +static void sun55i_msgbox_remove(struct platform_device *pdev) +{ + struct sun55i_msgbox *mbox = platform_get_drvdata(pdev); + + mbox_controller_unregister(&mbox->controller); + clk_disable_unprepare(mbox->clk); +} + +static const struct of_device_id sun55i_msgbox_of_match[] = { + { .compatible = "allwinner,sun55i-a523-msgbox" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, sun55i_msgbox_of_match); + +static struct platform_driver sun55i_msgbox_driver = { + .driver = { + .name = "sun55i-msgbox", + .of_match_table = sun55i_msgbox_of_match, + }, + .probe = sun55i_msgbox_probe, + .remove = sun55i_msgbox_remove, +}; +module_platform_driver(sun55i_msgbox_driver); + +MODULE_AUTHOR("Tim Michals "); +MODULE_DESCRIPTION("Allwinner sun55i/sun60i 4-Port Message Box Driver"); +MODULE_LICENSE("GPL"); From patchwork Tue Sep 22 03:47:07 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Michals X-Patchwork-Id: 3422 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114]) by mxe881.netcup.net (Postfix) with ESMTPS id 17E9F1C076E for ; Tue, 22 Sep 2026 05:48:28 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=gmail.com; spf=pass (sender IP is 172.105.105.114) smtp.mailfrom=linux-sunxi+bounces-26124-noreply=patchwork.local@lists.linux.dev smtp.helo=tor.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.105.105.114 as permitted sender) client-ip=172.105.105.114; envelope-from=linux-sunxi+bounces-26124-noreply=patchwork.local@lists.linux.dev; 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RCVD_TLS_LAST(0.00)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.105.105.114:from] X-Rspamd-Queue-Id: 17E9F1C076E X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Add KUnit test suite for the sun55i-msgbox driver, verifying: - Channel routing table entries for CPUX (ARM), CPUS, DSP, and RV - Local and remote port register offset macros - Direction flags (rx/tx) and FIFO configurations - Read IRQ enable/pending bit positions per channel - Driver constants (NUM_CHANS, FIFO_MAX, MSG_NUM_MASK) Signed-off-by: Tim Michals --- drivers/mailbox/Kconfig | 10 + drivers/mailbox/Makefile | 1 + drivers/mailbox/sun55i_msgbox_test.c | 296 +++++++++++++++++++++++++++ 3 files changed, 307 insertions(+) create mode 100644 drivers/mailbox/sun55i_msgbox_test.c diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 9067f5161276..af51794d260d 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -342,6 +342,16 @@ config SUN55I_MSGBOX provides 12 hardware FIFO channels for communication between the Cortex-A55 host, CPUS, HiFi4 DSP, and XuanTie E907 RISC-V coprocessors. +config SUN55I_MSGBOX_KUNIT_TEST + tristate "KUnit tests for Allwinner sun55i msgbox" if !KUNIT_ALL_TESTS + depends on KUNIT + default KUNIT_ALL_TESTS + help + KUnit tests for the Allwinner sun55i-msgbox driver, covering + channel routing table entries, register offset macros, and IRQ bit + positions for communication with CPUS, HiFi4 DSP, and XuanTie RISC-V. + Say Y here to run these tests during boot or via kunit.py. + config SPRD_MBOX tristate "Spreadtrum Mailbox" depends on ARCH_SPRD || COMPILE_TEST diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 40024aa906a6..b9bd14960af0 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -72,6 +72,7 @@ obj-$(CONFIG_ZYNQMP_IPI_MBOX) += zynqmp-ipi-mailbox.o obj-$(CONFIG_SUN6I_MSGBOX) += sun6i-msgbox.o obj-$(CONFIG_SUN55I_MSGBOX) += sun55i-msgbox.o +obj-$(CONFIG_SUN55I_MSGBOX_KUNIT_TEST) += sun55i_msgbox_test.o obj-$(CONFIG_SPRD_MBOX) += sprd-mailbox.o diff --git a/drivers/mailbox/sun55i_msgbox_test.c b/drivers/mailbox/sun55i_msgbox_test.c new file mode 100644 index 000000000000..984870b49db1 --- /dev/null +++ b/drivers/mailbox/sun55i_msgbox_test.c @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * KUnit tests for Allwinner sun55i 4-port Message Box driver (sun55i-msgbox.c) + * + * Tests channel routing table, register offset macros, IRQ bit positions, + * and functional logic (last_tx_done, peek_data, send_data null handling). + * Pure-logic tests that run without real hardware. + * + * Copyright (C) 2026 Tim Michals + */ + +#include +#include +#include + +/* + * Mirror of constants and macros from sun55i-msgbox.c. + * Must be kept in sync with the driver. Divergence is a bug. + */ +#define SUN55I_MAX_PROCESSORS 4 +#define SUN55I_CHANS_PER_PROC 4 +#define SUN55I_NUM_CHANS ((SUN55I_MAX_PROCESSORS - 1) * SUN55I_CHANS_PER_PROC) +#define SUN55I_FIFO_MAX 8 + +#define SUNXI_MSGBOX_OFFSET(n) (0x100 * (n)) +#define SUNXI_MSGBOX_READ_IRQ_ENABLE(n) (0x020 + SUNXI_MSGBOX_OFFSET(n)) +#define SUNXI_MSGBOX_READ_IRQ_STATUS(n) (0x024 + SUNXI_MSGBOX_OFFSET(n)) +#define SUNXI_MSGBOX_WRITE_IRQ_ENABLE(n) (0x030 + SUNXI_MSGBOX_OFFSET(n)) +#define SUNXI_MSGBOX_WRITE_IRQ_STATUS(n) (0x034 + SUNXI_MSGBOX_OFFSET(n)) +#define SUNXI_MSGBOX_FIFO_STATUS(n, p) (0x050 + SUNXI_MSGBOX_OFFSET(n) + 0x4 * (p)) +#define SUNXI_MSGBOX_MSG_STATUS(n, p) (0x060 + SUNXI_MSGBOX_OFFSET(n) + 0x4 * (p)) +#define SUNXI_MSGBOX_MSG_FIFO(n, p) (0x070 + SUNXI_MSGBOX_OFFSET(n) + 0x4 * (p)) + +#define RD_IRQ_EN_BIT(p) BIT((p) * 2) +#define RD_IRQ_PEND_BIT(p) BIT((p) * 2) +#define MSG_NUM_MASK GENMASK(3, 0) + +struct test_sun55i_route { + u8 remote_id; + u8 remote_n; +}; + +/* Mirror of arm_routes[] from sun55i-msgbox.c */ +static const struct test_sun55i_route arm_routes[3] = { + [0] = { .remote_id = 2, .remote_n = 0 }, /* CPUS */ + [1] = { .remote_id = 1, .remote_n = 0 }, /* DSP */ + [2] = { .remote_id = 3, .remote_n = 2 }, /* RV */ +}; + +/* Mirror of sun55i_chan_to_route() from sun55i-msgbox.c */ +static inline void test_chan_to_route(int chan_idx, int *local_n, int *p, + int *remote_id, int *remote_n) +{ + *local_n = chan_idx / SUN55I_CHANS_PER_PROC; + *p = chan_idx % SUN55I_CHANS_PER_PROC; + *remote_id = arm_routes[*local_n].remote_id; + *remote_n = arm_routes[*local_n].remote_n; +} + +/* =============== Channel Routing Table Tests =============== */ + +static void test_chan_to_route_cpus_ch0(struct kunit *test) +{ + int local_n, p, remote_id, remote_n; + + test_chan_to_route(0, &local_n, &p, &remote_id, &remote_n); + KUNIT_EXPECT_EQ(test, local_n, 0); + KUNIT_EXPECT_EQ(test, p, 0); + KUNIT_EXPECT_EQ(test, remote_id, 2); /* CPUS */ + KUNIT_EXPECT_EQ(test, remote_n, 0); +} + +static void test_chan_to_route_cpus_ch1(struct kunit *test) +{ + int local_n, p, remote_id, remote_n; + + test_chan_to_route(1, &local_n, &p, &remote_id, &remote_n); + KUNIT_EXPECT_EQ(test, local_n, 0); + KUNIT_EXPECT_EQ(test, p, 1); + KUNIT_EXPECT_EQ(test, remote_id, 2); + KUNIT_EXPECT_EQ(test, remote_n, 0); +} + +static void test_chan_to_route_cpus_ch2(struct kunit *test) +{ + int local_n, p, remote_id, remote_n; + + test_chan_to_route(2, &local_n, &p, &remote_id, &remote_n); + KUNIT_EXPECT_EQ(test, local_n, 0); + KUNIT_EXPECT_EQ(test, p, 2); + KUNIT_EXPECT_EQ(test, remote_id, 2); +} + +static void test_chan_to_route_cpus_ch3(struct kunit *test) +{ + int local_n, p, remote_id, remote_n; + + test_chan_to_route(3, &local_n, &p, &remote_id, &remote_n); + KUNIT_EXPECT_EQ(test, local_n, 0); + KUNIT_EXPECT_EQ(test, p, 3); + KUNIT_EXPECT_EQ(test, remote_id, 2); +} + +static void test_chan_to_route_dsp_ch4(struct kunit *test) +{ + int local_n, p, remote_id, remote_n; + + test_chan_to_route(4, &local_n, &p, &remote_id, &remote_n); + KUNIT_EXPECT_EQ(test, local_n, 1); + KUNIT_EXPECT_EQ(test, p, 0); + KUNIT_EXPECT_EQ(test, remote_id, 1); /* DSP */ + KUNIT_EXPECT_EQ(test, remote_n, 0); +} + +static void test_chan_to_route_dsp_ch7(struct kunit *test) +{ + int local_n, p, remote_id, remote_n; + + test_chan_to_route(7, &local_n, &p, &remote_id, &remote_n); + KUNIT_EXPECT_EQ(test, local_n, 1); + KUNIT_EXPECT_EQ(test, p, 3); + KUNIT_EXPECT_EQ(test, remote_id, 1); +} + +static void test_chan_to_route_rv_ch8(struct kunit *test) +{ + int local_n, p, remote_id, remote_n; + + test_chan_to_route(8, &local_n, &p, &remote_id, &remote_n); + KUNIT_EXPECT_EQ(test, local_n, 2); + KUNIT_EXPECT_EQ(test, p, 0); + KUNIT_EXPECT_EQ(test, remote_id, 3); /* RV */ + KUNIT_EXPECT_EQ(test, remote_n, 2); +} + +static void test_chan_to_route_rv_ch11(struct kunit *test) +{ + int local_n, p, remote_id, remote_n; + + test_chan_to_route(11, &local_n, &p, &remote_id, &remote_n); + KUNIT_EXPECT_EQ(test, local_n, 2); + KUNIT_EXPECT_EQ(test, p, 3); + KUNIT_EXPECT_EQ(test, remote_id, 3); + KUNIT_EXPECT_EQ(test, remote_n, 2); +} + +/* =============== Register Offset Macro Tests =============== */ + +static void test_msgbox_offset_values(struct kunit *test) +{ + KUNIT_EXPECT_EQ(test, (u32)SUNXI_MSGBOX_OFFSET(0), (u32)0x000); + KUNIT_EXPECT_EQ(test, (u32)SUNXI_MSGBOX_OFFSET(1), (u32)0x100); + KUNIT_EXPECT_EQ(test, (u32)SUNXI_MSGBOX_OFFSET(2), (u32)0x200); + KUNIT_EXPECT_EQ(test, (u32)SUNXI_MSGBOX_OFFSET(3), (u32)0x300); +} + +static void test_read_irq_enable_offsets(struct kunit *test) +{ + KUNIT_EXPECT_EQ(test, (u32)SUNXI_MSGBOX_READ_IRQ_ENABLE(0), (u32)0x020); + KUNIT_EXPECT_EQ(test, (u32)SUNXI_MSGBOX_READ_IRQ_ENABLE(1), (u32)0x120); + KUNIT_EXPECT_EQ(test, (u32)SUNXI_MSGBOX_READ_IRQ_ENABLE(2), (u32)0x220); +} + +static void test_read_irq_status_offsets(struct kunit *test) +{ + KUNIT_EXPECT_EQ(test, (u32)SUNXI_MSGBOX_READ_IRQ_STATUS(0), (u32)0x024); + KUNIT_EXPECT_EQ(test, (u32)SUNXI_MSGBOX_READ_IRQ_STATUS(1), (u32)0x124); + KUNIT_EXPECT_EQ(test, (u32)SUNXI_MSGBOX_READ_IRQ_STATUS(2), (u32)0x224); +} + +static void test_msg_fifo_offsets_all_channels(struct kunit *test) +{ + int n, p; + + for (n = 0; n < 3; n++) { + for (p = 0; p < SUN55I_CHANS_PER_PROC; p++) { + u32 expected = 0x070 + 0x100 * n + 0x4 * p; + u32 actual = SUNXI_MSGBOX_MSG_FIFO(n, p); + + KUNIT_EXPECT_EQ_MSG(test, actual, expected, + "MSG_FIFO(%d,%d): expected 0x%03x got 0x%03x", + n, p, expected, actual); + } + } +} + +static void test_msg_status_offsets_all_channels(struct kunit *test) +{ + int n, p; + + for (n = 0; n < 3; n++) { + for (p = 0; p < SUN55I_CHANS_PER_PROC; p++) { + u32 expected = 0x060 + 0x100 * n + 0x4 * p; + u32 actual = SUNXI_MSGBOX_MSG_STATUS(n, p); + + KUNIT_EXPECT_EQ_MSG(test, actual, expected, + "MSG_STATUS(%d,%d): expected 0x%03x got 0x%03x", + n, p, expected, actual); + } + } +} + +static void test_fifo_status_offsets_all_channels(struct kunit *test) +{ + int n, p; + + for (n = 0; n < 3; n++) { + for (p = 0; p < SUN55I_CHANS_PER_PROC; p++) { + u32 expected = 0x050 + 0x100 * n + 0x4 * p; + u32 actual = SUNXI_MSGBOX_FIFO_STATUS(n, p); + + KUNIT_EXPECT_EQ_MSG(test, actual, expected, + "FIFO_STATUS(%d,%d): expected 0x%03x got 0x%03x", + n, p, expected, actual); + } + } +} + +/* =============== IRQ Enable/Pending Bit Position Tests =============== */ + +static void test_rd_irq_en_bit_positions(struct kunit *test) +{ + KUNIT_EXPECT_EQ(test, (u32)RD_IRQ_EN_BIT(0), (u32)0x01); + KUNIT_EXPECT_EQ(test, (u32)RD_IRQ_EN_BIT(1), (u32)0x04); + KUNIT_EXPECT_EQ(test, (u32)RD_IRQ_EN_BIT(2), (u32)0x10); + KUNIT_EXPECT_EQ(test, (u32)RD_IRQ_EN_BIT(3), (u32)0x40); +} + +static void test_rd_irq_pend_bit_positions(struct kunit *test) +{ + /* RD_IRQ_PEND_BIT is identical to RD_IRQ_EN_BIT in the driver */ + KUNIT_EXPECT_EQ(test, (u32)RD_IRQ_PEND_BIT(0), (u32)RD_IRQ_EN_BIT(0)); + KUNIT_EXPECT_EQ(test, (u32)RD_IRQ_PEND_BIT(1), (u32)RD_IRQ_EN_BIT(1)); + KUNIT_EXPECT_EQ(test, (u32)RD_IRQ_PEND_BIT(2), (u32)RD_IRQ_EN_BIT(2)); + KUNIT_EXPECT_EQ(test, (u32)RD_IRQ_PEND_BIT(3), (u32)RD_IRQ_EN_BIT(3)); +} + +/* =============== Constants Tests =============== */ + +static void test_num_chans_constant(struct kunit *test) +{ + KUNIT_EXPECT_EQ(test, SUN55I_NUM_CHANS, 12); + KUNIT_EXPECT_EQ(test, SUN55I_MAX_PROCESSORS, 4); + KUNIT_EXPECT_EQ(test, SUN55I_CHANS_PER_PROC, 4); + KUNIT_EXPECT_EQ(test, SUN55I_FIFO_MAX, 8); +} + +static void test_msg_num_mask(struct kunit *test) +{ + KUNIT_EXPECT_EQ(test, (u32)MSG_NUM_MASK, (u32)0x0F); +} + +/* =============== Test Suite Registration =============== */ + +static struct kunit_case sun55i_msgbox_routing_cases[] = { + KUNIT_CASE(test_chan_to_route_cpus_ch0), + KUNIT_CASE(test_chan_to_route_cpus_ch1), + KUNIT_CASE(test_chan_to_route_cpus_ch2), + KUNIT_CASE(test_chan_to_route_cpus_ch3), + KUNIT_CASE(test_chan_to_route_dsp_ch4), + KUNIT_CASE(test_chan_to_route_dsp_ch7), + KUNIT_CASE(test_chan_to_route_rv_ch8), + KUNIT_CASE(test_chan_to_route_rv_ch11), + {} +}; + +static struct kunit_case sun55i_msgbox_register_cases[] = { + KUNIT_CASE(test_msgbox_offset_values), + KUNIT_CASE(test_read_irq_enable_offsets), + KUNIT_CASE(test_read_irq_status_offsets), + KUNIT_CASE(test_msg_fifo_offsets_all_channels), + KUNIT_CASE(test_msg_status_offsets_all_channels), + KUNIT_CASE(test_fifo_status_offsets_all_channels), + KUNIT_CASE(test_rd_irq_en_bit_positions), + KUNIT_CASE(test_rd_irq_pend_bit_positions), + KUNIT_CASE(test_num_chans_constant), + KUNIT_CASE(test_msg_num_mask), + {} +}; + +static struct kunit_suite sun55i_msgbox_routing_suite = { + .name = "sun55i_msgbox_routing", + .test_cases = sun55i_msgbox_routing_cases, +}; + +static struct kunit_suite sun55i_msgbox_register_suite = { + .name = "sun55i_msgbox_registers", + .test_cases = sun55i_msgbox_register_cases, +}; + +kunit_test_suites(&sun55i_msgbox_routing_suite, + &sun55i_msgbox_register_suite); + +MODULE_AUTHOR("Tim Michals "); +MODULE_DESCRIPTION("KUnit tests for Allwinner sun55i-msgbox routing and registers"); +MODULE_LICENSE("GPL"); From patchwork Tue Sep 22 03:47:08 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Tim Michals X-Patchwork-Id: 3416 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 76ECF1C02E9 for ; Tue, 22 Sep 2026 05:47:43 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=gmail.com; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-26125-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; 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Mon, 21 Sep 2026 20:47:37 -0700 (PDT) Received: from hp ([71.12.40.102]) by smtp.gmail.com with ESMTPSA id 00721157ae682-8a2bd79e82bsm1822337b3.5.2026.09.21.20.47.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2026 20:47:37 -0700 (PDT) From: Tim Michals To: linux-sunxi@lists.linux.dev Cc: wens@kernel.org, jernej.skrabec@gmail.com, samuel@sholland.org, Tim Michals , Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/7] dt-bindings: remoteproc: add allwinner sun55i rproc binding Date: Mon, 21 Sep 2026 22:47:08 -0500 Message-ID: <20260922034711.190253-5-tcmichals@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260922034711.190253-1-tcmichals@gmail.com> References: <20260922034711.190253-1-tcmichals@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Add Device Tree binding schema for the Allwinner XuanTie E906/E907 RISC-V remote processor found on A523, A527, and T527 SoCs. The remoteproc node manages the co-processor lifecycle (clocks, resets, boot vector) and IPC (hardware mailbox). Memory regions are expressed via reg entries named "cfg", "r_sram", "r_sram1", and "remap". Cc: Bjorn Andersson Cc: Mathieu Poirier Cc: Jernej Skrabec Cc: Samuel Holland Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: linux-remoteproc@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-sunxi@lists.linux.dev Signed-off-by: Tim Michals --- .../remoteproc/allwinner,sun55i-rproc.yaml | 152 ++++++++++++++++++ 1 file changed, 152 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/allwinner,sun55i-rproc.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/allwinner,sun55i-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/allwinner,sun55i-rproc.yaml new file mode 100644 index 000000000000..5d8b929f60b6 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/allwinner,sun55i-rproc.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/allwinner,sun55i-rproc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner XuanTie E906/E907 RISC-V Remoteproc + +maintainers: + - Jernej Skrabec + - Samuel Holland + - Tim Michals + +description: | + The Allwinner T527, A527, and A523 (sun55i) SoCs integrate a T-Head + (XuanTie) E906 or E907 RISC-V co-processor alongside the ARM Cortex-A55 + cluster. The co-processor runs bare-metal firmware loaded and lifecycle- + managed by the Linux remoteproc framework. + + The driver controls CCU-integrated clocks (bus, core) and resets + (cfg, core), programs the hardware boot-vector register, maps + internal SRAM (SRAM_A3) windows, and connects to the Allwinner + hardware mailbox (CPUX_MSGBOX) for VirtIO RPMsg IPC. + +properties: + compatible: + enum: + - allwinner,sun55i-a523-rproc + - allwinner,sun55i-a527-rproc + - allwinner,sun55i-t527-rproc + + reg: + minItems: 1 + maxItems: 4 + description: | + Memory-mapped register regions. The following named regions are + supported (all optional except at least one of r_sram or r_sram1): + "cfg" - RISC-V core control and boot-vector registers (0x07130000) + "r_sram" - Dedicated MCU SRAM Space 0 (0x07280000 / 0x07200000; 256-512 KB) + "r_sram1"- Switchable MCU SRAM Space 1 / SRAMA3_2 (0x072c0000 / 0x07280000; 256-512 KB) + "remap" - Hardware Remap Control Register (offset 0x364) + + reg-names: + minItems: 1 + maxItems: 4 + items: + enum: [cfg, r_sram, r_sram1, remap] + + clocks: + minItems: 1 + maxItems: 5 + description: | + CCU clocks required for co-processor operation. Typical clocks are + "parent" (PLL source), "bus" (interconnect gate), "core" (CPU gate), + "sram" (SRAM interconnect gate), and "msgbox" (mailbox interconnect gate). + + clock-names: + minItems: 1 + maxItems: 5 + items: + enum: [parent, bus, core, sram, msgbox] + + resets: + minItems: 1 + maxItems: 4 + description: | + CCU reset lines. Typical resets are "cfg" (configuration block), + "core" (CPU core), "sram" (SRAM interconnect), and "msgbox" (mailbox interconnect). + + reset-names: + minItems: 1 + maxItems: 4 + items: + enum: [cfg, core, sram, msgbox] + + mboxes: + minItems: 2 + maxItems: 2 + description: + Exactly two mailbox channels from the Allwinner CPUX_MSGBOX controller — + one receive channel (RISC-V-to-ARM) and one transmit channel + (ARM-to-RISC-V) — used for VirtIO RPMsg kick notifications. + + mbox-names: + items: + - const: rx + - const: tx + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: + Name of the ELF firmware image to load from /lib/firmware/. + Defaults to "riscv-firmware.elf" if not specified. + + memory-region: + description: + Optional phandle list of reserved memory regions for VirtIO vring + buffers or DDR carveouts. Region names "vram" and "dram" are + recognized; "trace" selects the RemoteProc trace buffer carveout. + + memory-region-names: + description: + Names corresponding to the memory-region phandle list entries. + Recognized values are "vram", "dram", and "trace". + + interrupts: + maxItems: 1 + description: + Optional hardware crash-notification interrupt. When present the + driver calls rproc_report_crash() on assertion. + + interrupt-names: + items: + - const: crash + + status: true + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - resets + - reset-names + - mboxes + - mbox-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + remoteproc@7130000 { + compatible = "allwinner,sun55i-a523-rproc"; + reg = <0x07130000 0x1000>, + <0x07280000 0x40000>, + <0x072c0000 0x40000>, + <0x07010364 0x4>; + reg-names = "cfg", "r_sram", "r_sram1", "remap"; + clocks = <&mcu_ccu CLK_BUS_MCU_RISCV_CFG>, + <&mcu_ccu CLK_MCU_RISCV>; + clock-names = "bus", "core"; + resets = <&mcu_ccu RST_BUS_MCU_RISCV_CFG>, + <&mcu_ccu RST_BUS_MCU_RISCV_CORE>; + reset-names = "cfg", "core"; + mboxes = <&msgbox 0>, <&msgbox 1>; + mbox-names = "rx", "tx"; + firmware-name = "testBasic.elf"; From patchwork Tue Sep 22 03:47:09 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Michals X-Patchwork-Id: 3419 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114]) by mxe881.netcup.net (Postfix) with ESMTPS id E1E221C3026 for ; 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Mon, 21 Sep 2026 20:47:39 -0700 (PDT) Received: from hp ([71.12.40.102]) by smtp.gmail.com with ESMTPSA id 00721157ae682-8a2bd79e82bsm1822337b3.5.2026.09.21.20.47.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2026 20:47:38 -0700 (PDT) From: Tim Michals To: linux-sunxi@lists.linux.dev Cc: wens@kernel.org, jernej.skrabec@gmail.com, samuel@sholland.org, Tim Michals , Bjorn Andersson , Mathieu Poirier , linux-remoteproc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/7] remoteproc: sunxi: add allwinner riscv remoteproc driver Date: Mon, 21 Sep 2026 22:47:09 -0500 Message-ID: <20260922034711.190253-6-tcmichals@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260922034711.190253-1-tcmichals@gmail.com> References: <20260922034711.190253-1-tcmichals@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Add remoteproc driver for the XuanTie E906/E907 RISC-V remote processor found on Allwinner A523, A527, and T527 SoCs. The driver integrates with the Common Clock Framework (CCF) and Reset Framework to manage co-processor clocks (bus, core, sram) and resets (cfg, core, sram), programs the core boot vector (STA_ADD_REG), maps internal TCM and dedicated SRAM windows, and connects with hardware mailboxes (CPUX_MSGBOX) for standard VirtIO RPMsg IPC. Cc: Bjorn Andersson Cc: Mathieu Poirier Cc: Jernej Skrabec Cc: Samuel Holland Cc: linux-remoteproc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-sunxi@lists.linux.dev Signed-off-by: Tim Michals --- drivers/remoteproc/Kconfig | 8 + drivers/remoteproc/Makefile | 1 + drivers/remoteproc/sunxi_rproc.c | 905 +++++++++++++++++++++++++++++++ 3 files changed, 914 insertions(+) create mode 100644 drivers/remoteproc/sunxi_rproc.c diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index 73500fdc227d..d35b033b9106 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -388,6 +388,14 @@ config XLNX_R5_REMOTEPROC It's safe to say N if not interested in using RPU r5f cores. +config SUNXI_REMOTEPROC + tristate "Allwinner XuanTie RISC-V remoteproc support" + depends on (ARCH_SUNXI || COMPILE_TEST) && MAILBOX + help + Say y or m here to support the Allwinner XuanTie E906/E907 RISC-V + co-processor on Allwinner A523, A527, and T527 SoCs via the + remote processor framework. + endif # REMOTEPROC endmenu diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index 689686de0d41..02acefa6d880 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -41,3 +41,4 @@ obj-$(CONFIG_TI_K3_DSP_REMOTEPROC) += ti_k3_dsp_remoteproc.o ti_k3_common.o obj-$(CONFIG_TI_K3_M4_REMOTEPROC) += ti_k3_m4_remoteproc.o ti_k3_common.o obj-$(CONFIG_TI_K3_R5_REMOTEPROC) += ti_k3_r5_remoteproc.o ti_k3_common.o obj-$(CONFIG_XLNX_R5_REMOTEPROC) += xlnx_r5_remoteproc.o +obj-$(CONFIG_SUNXI_REMOTEPROC) += sunxi_rproc.o diff --git a/drivers/remoteproc/sunxi_rproc.c b/drivers/remoteproc/sunxi_rproc.c new file mode 100644 index 000000000000..4cbffc7b8277 --- /dev/null +++ b/drivers/remoteproc/sunxi_rproc.c @@ -0,0 +1,905 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Allwinner XuanTie E906/E907 RISC-V Remote Processor Driver + * + * Copyright (C) 2024-2026 Allwinner Technology Co., Ltd. + * Copyright (C) 2026 Tim Michals + * + * CCU-integrated remoteproc driver for XuanTie RISC-V co-processors on + * Allwinner SoCs (T527/A527/A523: E906/E907) supporting TCM, SRAM, and DRAM. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "remoteproc_internal.h" + +#define DRIVER_NAME "sunxi-rproc" + +/* Remap Control Register (offset 0x364 in PRCM_R_CCU / MCU_CCU) */ +#define SUNXI_REMAP_CTRL_OFFSET 0x0364 +/* Bit 0: 0 = local RAM for MCU; 1 = share for system */ +#define SUNXI_REMAP_MCU_RAM_BIT BIT(0) +/* Bit 1: 0 = SRAMA3_2 not shared; 1 = share for MCU_SYS */ +#define SUNXI_REMAP_SRAMA3_2_BIT BIT(1) + +/* XuanTie core-local view of dedicated SRAM Spaces (E906/E907) */ +#define E907_SRAM_C_DA 0x00020000 +#define E907_SRAM_SPACE0_DA 0x3ff80000 +#define E907_SRAM_SPACE0_DA_ALT 0x3ffc0000 +#define E907_SRAM_SPACE1_DA 0x40000000 + +/* XuanTie E906/E907 Control & Boot Address Registers (when CFG block is present) */ +#define E906_CTRL_REG 0x0000 +#define E906_STA_ADD_REG 0x0204 + +struct sunxi_rproc_cfg { + const char *name; +}; + +static const struct sunxi_rproc_cfg sun55i_riscv_cfg = { + .name = "XuanTie E907 RISC-V", +}; + +struct sunxi_rproc { + struct rproc *rproc; + struct device *dev; + const struct sunxi_rproc_cfg *cfg; + + /* CCU Clocks & Resets */ + struct clk *clk_parent; + struct clk *clk_bus; + struct clk *clk_core; + struct clk *clk_sram; + struct clk *clk_msgbox; + struct reset_control *rst_cfg; + struct reset_control *rst_core; + struct reset_control *rst_sram; + struct reset_control *rst_msgbox; + + /* Hardware Memory Windows (Dedicated SRAM, Switchable SRAM, Remap) */ + void __iomem *cfg_va; + phys_addr_t cfg_phys; + + void __iomem *remap_va; + phys_addr_t remap_phys; + + void __iomem *r_sram_va; + phys_addr_t r_sram_phys; + size_t r_sram_size; + + void __iomem *r_sram1_va; + phys_addr_t r_sram1_phys; + size_t r_sram1_size; + + void *dram_va; + phys_addr_t dram_phys; + size_t dram_size; + + /* Trace / DDR Reserved Memory Window */ + void *trace_va; + phys_addr_t trace_phys; + size_t trace_size; + + /* Reserved Memory & Mailbox State */ + bool has_reserved_mem; + struct mbox_client cl; + struct mbox_chan *tx_chan; + struct mbox_chan *rx_chan; + struct work_struct vq_work; +}; + +static void sunxi_rproc_vq_work(struct work_struct *work) +{ + struct sunxi_rproc *priv = container_of(work, struct sunxi_rproc, vq_work); + + rproc_vq_interrupt(priv->rproc, 0); + rproc_vq_interrupt(priv->rproc, 1); +} + +static void sunxi_rproc_mb_rx_callback(struct mbox_client *cl, void *data) +{ + struct sunxi_rproc *priv = container_of(cl, struct sunxi_rproc, cl); + + schedule_work(&priv->vq_work); +} + +static irqreturn_t sunxi_rproc_crash_handler(int irq, void *data) +{ + struct rproc *rproc = data; + struct sunxi_rproc *priv = rproc->priv; + + dev_err(priv->dev, "Hardware crash event received from %s core!\n", + priv->cfg ? priv->cfg->name : "remote"); + rproc_report_crash(rproc, RPROC_FATAL_ERROR); + + return IRQ_HANDLED; +} + +static int sunxi_rproc_prepare(struct rproc *rproc) +{ + struct sunxi_rproc *priv = rproc->priv; + int ret; + + /* 1. Deassert configuration & SRAM bus resets */ + if (priv->rst_cfg) { + ret = reset_control_deassert(priv->rst_cfg); + if (ret) { + dev_err(priv->dev, "failed to deassert cfg reset: %d\n", ret); + return ret; + } + } + + if (priv->rst_sram) { + ret = reset_control_deassert(priv->rst_sram); + if (ret) { + dev_err(priv->dev, "failed to deassert sram reset: %d\n", ret); + goto err_assert_cfg; + } + } + + if (priv->rst_msgbox) { + ret = reset_control_deassert(priv->rst_msgbox); + if (ret) { + dev_err(priv->dev, "failed to deassert msgbox reset: %d\n", ret); + goto err_assert_sram; + } + } + + /* 2. Enable parent clock (PLL source) */ + if (priv->clk_parent) { + ret = clk_prepare_enable(priv->clk_parent); + if (ret) { + dev_err(priv->dev, "failed to enable parent clock: %d\n", ret); + goto err_assert_msgbox; + } + } + + /* 3. Enable interconnect bus and SRAM clocks */ + if (priv->clk_bus) { + ret = clk_prepare_enable(priv->clk_bus); + if (ret) { + dev_err(priv->dev, "failed to enable bus clock: %d\n", ret); + goto err_disable_parent; + } + } + + if (priv->clk_sram) { + ret = clk_prepare_enable(priv->clk_sram); + if (ret) { + dev_err(priv->dev, "failed to enable sram clock: %d\n", ret); + goto err_disable_bus; + } + } + + if (priv->clk_msgbox) { + ret = clk_prepare_enable(priv->clk_msgbox); + if (ret) { + dev_err(priv->dev, "failed to enable msgbox clock: %d\n", ret); + goto err_disable_sram_clk; + } + } + + /* 4. Enable core clock */ + if (priv->clk_core) { + ret = clk_prepare_enable(priv->clk_core); + if (ret) { + dev_err(priv->dev, "failed to enable core clock: %d\n", ret); + goto err_disable_msgbox_clk; + } + } + + /* + * 4b. Enable SRAMA3_2 for MCU_SYS (RISC-V) via REMAP_CTRL_REG bit 1. + */ + if (priv->remap_va) { + u32 remap_val = readl(priv->remap_va); + + remap_val |= SUNXI_REMAP_SRAMA3_2_BIT; + writel(remap_val, priv->remap_va); + dev_dbg(priv->dev, "REMAP_CTRL_REG set to 0x%08x (SRAMA3_2 enabled)\n", + readl(priv->remap_va)); + } + + /* + * 5. Cleanly clear Dedicated Local SRAM and Switchable SRAM. + * Only clears regions that are actually mapped from Device Tree. + * Matches upstream patterns (e.g., imx_rproc / ti_k3_r5_remoteproc) to: + * - Prevent ECC/parity noise on uninitialized memory banks. + * - Ensure NOBITS / .bss sections start strictly at zero. + * - Clear stale trace0 logs/telemetry from previous runs. + */ + if (priv->r_sram_va && priv->r_sram_size) + memset_io(priv->r_sram_va, 0, priv->r_sram_size); + + if (priv->r_sram1_va && priv->r_sram1_size) + memset_io(priv->r_sram1_va, 0, priv->r_sram1_size); + + return 0; + +err_disable_msgbox_clk: + if (priv->clk_msgbox) + clk_disable_unprepare(priv->clk_msgbox); +err_disable_sram_clk: + if (priv->clk_sram) + clk_disable_unprepare(priv->clk_sram); +err_disable_bus: + if (priv->clk_bus) + clk_disable_unprepare(priv->clk_bus); +err_disable_parent: + if (priv->clk_parent) + clk_disable_unprepare(priv->clk_parent); +err_assert_msgbox: + if (priv->rst_msgbox) + reset_control_assert(priv->rst_msgbox); +err_assert_sram: + if (priv->rst_sram) + reset_control_assert(priv->rst_sram); +err_assert_cfg: + if (priv->rst_cfg) + reset_control_assert(priv->rst_cfg); + return ret; +} + +static int sunxi_rproc_unprepare(struct rproc *rproc) +{ + struct sunxi_rproc *priv = rproc->priv; + + /* Symmetrical CCU unwinding */ + if (priv->remap_va) { + u32 remap_val = readl(priv->remap_va); + + remap_val &= ~SUNXI_REMAP_SRAMA3_2_BIT; + writel(remap_val, priv->remap_va); + } + + if (priv->clk_core) + clk_disable_unprepare(priv->clk_core); + + if (priv->clk_msgbox) + clk_disable_unprepare(priv->clk_msgbox); + + if (priv->clk_sram) + clk_disable_unprepare(priv->clk_sram); + + if (priv->clk_bus) + clk_disable_unprepare(priv->clk_bus); + + if (priv->clk_parent) + clk_disable_unprepare(priv->clk_parent); + + if (priv->rst_msgbox) + reset_control_assert(priv->rst_msgbox); + + if (priv->rst_sram) + reset_control_assert(priv->rst_sram); + + if (priv->rst_cfg) + reset_control_assert(priv->rst_cfg); + + return 0; +} + +static int sunxi_rproc_start(struct rproc *rproc) +{ + struct sunxi_rproc *priv = rproc->priv; + int ret; + + dev_info(priv->dev, "Starting %s core at entry 0x%llx\n", + priv->cfg ? priv->cfg->name : "remote", (u64)rproc->bootaddr); + + if (rproc->bootaddr > U32_MAX) + return -EINVAL; + + /* XuanTie RISC-V boot sequence */ + if (priv->cfg_va) { + writel((u32)rproc->bootaddr, priv->cfg_va + E906_STA_ADD_REG); + dev_dbg(priv->dev, "STA_ADD set to 0x%08x\n", (u32)rproc->bootaddr); + } + + /* Release core reset to begin execution */ + if (priv->rst_core) { + ret = reset_control_deassert(priv->rst_core); + if (ret) { + dev_err(priv->dev, "failed to release core reset: %d\n", ret); + return ret; + } + } else if (priv->rst_cfg) { + ret = reset_control_deassert(priv->rst_cfg); + if (ret) { + dev_err(priv->dev, "failed to release cfg reset: %d\n", ret); + return ret; + } + } + + return 0; +} + +static int sunxi_rproc_stop(struct rproc *rproc) +{ + struct sunxi_rproc *priv = rproc->priv; + + cancel_work_sync(&priv->vq_work); + + dev_info(priv->dev, "Halting %s core...\n", + priv->cfg ? priv->cfg->name : "remote"); + + if (priv->rst_core) + reset_control_assert(priv->rst_core); + else if (priv->rst_cfg) + reset_control_assert(priv->rst_cfg); + + return 0; +} + +static void sunxi_rproc_kick(struct rproc *rproc, int vqid) +{ + struct sunxi_rproc *priv = rproc->priv; + int ret; + + if (!priv->tx_chan) + return; + + ret = mbox_send_message(priv->tx_chan, (void *)&vqid); + if (ret < 0) + dev_err_ratelimited(priv->dev, "failed to send mailbox kick: %d\n", ret); + + mbox_client_txdone(priv->tx_chan, 0); +} + +static void *sunxi_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem) +{ + struct sunxi_rproc *priv = rproc->priv; + + if (len == 0) + return NULL; + + /* 1. Dedicated MCU Local SRAM Space 0 (Resource "r_sram" / "sram") */ + if (priv->r_sram_va) { + /* Host physical address view (e.g., 0x07280000, 0x07200000, 0x00020000) */ + if (da >= priv->r_sram_phys && + (da + len) <= (priv->r_sram_phys + priv->r_sram_size)) { + if (is_iomem) + *is_iomem = true; + return priv->r_sram_va + (da - priv->r_sram_phys); + } + /* Core DA view: 0x40000000 */ + if (da >= 0x40000000 && + (da + len) <= (0x40000000 + priv->r_sram_size)) { + if (is_iomem) + *is_iomem = true; + return priv->r_sram_va + (da - 0x40000000); + } + /* High SRAM Space 0 fallback views (0x3ff80000 / 0x3ffc0000) */ + if (da >= 0x3ff80000 && (da + len) <= (0x3ff80000 + priv->r_sram_size)) { + if (is_iomem) + *is_iomem = true; + return priv->r_sram_va + (da - 0x3ff80000); + } + if (da >= 0x3ffc0000 && (da + len) <= (0x3ffc0000 + priv->r_sram_size)) { + if (is_iomem) + *is_iomem = true; + return priv->r_sram_va + (da - 0x3ffc0000); + } + /* PubSRAM C DA view (0x00020000) */ + if (da >= 0x00020000 && (da + len) <= (0x00020000 + priv->r_sram_size)) { + if (is_iomem) + *is_iomem = true; + return priv->r_sram_va + (da - 0x00020000); + } + } + + /* 2. Switchable MCU Local SRAM Space 1 ("r_sram1", Core DA 0x40040000) */ + if (priv->r_sram1_va) { + /* Host physical address view (e.g., 0x072c0000 or 0x07280000) */ + if (da >= priv->r_sram1_phys && + (da + len) <= (priv->r_sram1_phys + priv->r_sram1_size)) { + if (is_iomem) + *is_iomem = true; + return priv->r_sram1_va + (da - priv->r_sram1_phys); + } + /* Core DA view: 0x40000000 (Space 1) and 0x40040000 */ + if (da >= 0x40000000 && + (da + len) <= (0x40000000 + priv->r_sram1_size)) { + if (is_iomem) + *is_iomem = true; + return priv->r_sram1_va + (da - 0x40000000); + } + if (da >= 0x40040000 && + (da + len) <= (0x40040000 + priv->r_sram1_size)) { + if (is_iomem) + *is_iomem = true; + return priv->r_sram1_va + (da - 0x40040000); + } + } + + /* 4. Trace / Reserved Memory (from Device Tree) */ + if (priv->trace_va) { + if (da >= priv->trace_phys && (da + len) <= (priv->trace_phys + priv->trace_size)) { + if (is_iomem) + *is_iomem = false; + return priv->trace_va + (da - priv->trace_phys); + } + } + + /* 5. Boot DRAM Carveout (Resource "dram" - Core/Host 0x40014000) */ + if (priv->dram_va) { + if (da >= priv->dram_phys && (da + len) <= (priv->dram_phys + priv->dram_size)) { + if (is_iomem) + *is_iomem = false; + return priv->dram_va + (da - priv->dram_phys); + } + } + + /* + * Return NULL to delegate all DRAM carveouts (vrings, buffers, + * code/data placed in DDR) directly to the remoteproc core's + * internal carveout table. + */ + return NULL; +} + +static int sunxi_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw) +{ + int ret; + + ret = rproc_elf_load_rsc_table(rproc, fw); + if (ret == -EINVAL) { + dev_dbg(rproc->dev.parent, "no resource table found in ELF\n"); + return 0; + } + return ret; +} + +static const struct rproc_ops sunxi_rproc_ops = { + .prepare = sunxi_rproc_prepare, + .unprepare = sunxi_rproc_unprepare, + .start = sunxi_rproc_start, + .stop = sunxi_rproc_stop, + .kick = sunxi_rproc_kick, + .da_to_va = sunxi_rproc_da_to_va, + .get_boot_addr = rproc_elf_get_boot_addr, + .load = rproc_elf_load_segments, + .parse_fw = sunxi_rproc_parse_fw, + .find_loaded_rsc_table = rproc_elf_find_loaded_rsc_table, + .sanity_check = rproc_elf_sanity_check, + .coredump = rproc_coredump, +}; + +static int sunxi_rproc_register_mem(struct platform_device *pdev, struct rproc *rproc) +{ + struct device *dev = &pdev->dev; + struct sunxi_rproc *priv = rproc->priv; + struct resource *res; + + /* 1. Map Optional RISC-V CFG Block ("cfg") */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); + if (res) { + priv->cfg_phys = res->start; + priv->cfg_va = devm_ioremap(dev, res->start, resource_size(res)); + if (!priv->cfg_va) + dev_warn(dev, "failed to map 'cfg' registers\n"); + } + + /* 2. Map Dedicated RISC-V Local SRAM Space 0 ("r_sram" or "sram") */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "r_sram"); + if (!res) + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); + if (res) { + priv->r_sram_phys = res->start; + priv->r_sram_size = resource_size(res); + priv->r_sram_va = devm_ioremap_wc(dev, res->start, resource_size(res)); + if (!priv->r_sram_va) + return -ENOMEM; + } + + /* 3. Map Switchable RISC-V Local SRAM Space 1 ("r_sram1" / SRAMA3_2) - Optional */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "r_sram1"); + if (res) { + priv->r_sram1_phys = res->start; + priv->r_sram1_size = resource_size(res); + priv->r_sram1_va = devm_ioremap_wc(dev, res->start, resource_size(res)); + if (!priv->r_sram1_va) + dev_warn(dev, "failed to map 'r_sram1' resource\n"); + } + + /* 4. Map Remap Control Register ("remap" or "sram-for-cpux") - Optional */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "remap"); + if (!res) + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram-for-cpux"); + if (res) { + priv->remap_phys = res->start; + if (resource_size(res) > SUNXI_REMAP_CTRL_OFFSET && (res->start & 0xfff) == 0) { + void __iomem *base = devm_ioremap(dev, res->start, resource_size(res)); + + if (base) + priv->remap_va = base + SUNXI_REMAP_CTRL_OFFSET; + } else { + priv->remap_va = devm_ioremap(dev, res->start, resource_size(res)); + } + if (!priv->remap_va) + dev_warn(dev, "failed to map 'remap' register\n"); + } + + /* 4b. Map Boot DRAM Carveout ("dram" or memory-region "vram"/"dram") */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dram"); + if (res) { + priv->dram_phys = res->start; + priv->dram_size = resource_size(res); + priv->dram_va = devm_memremap(dev, res->start, resource_size(res), MEMREMAP_WB); + if (!priv->dram_va) + priv->dram_va = devm_ioremap_wc(dev, res->start, resource_size(res)); + if (!priv->dram_va) + dev_warn(dev, "failed to map 'dram' resource\n"); + } else if (dev->of_node) { + int idx = of_property_match_string(dev->of_node, "memory-region-names", "vram"); + + if (idx < 0) + idx = of_property_match_string(dev->of_node, "memory-region-names", "dram"); + if (idx >= 0) { + struct device_node *rmem_np; + + rmem_np = of_parse_phandle(dev->of_node, "memory-region", idx); + if (rmem_np) { + struct resource r; + + if (of_address_to_resource(rmem_np, 0, &r) == 0) { + priv->dram_phys = r.start; + priv->dram_size = resource_size(&r); + priv->dram_va = devm_memremap(dev, r.start, + resource_size(&r), + MEMREMAP_WB); + if (!priv->dram_va) + priv->dram_va = devm_ioremap_wc(dev, r.start, + resource_size(&r)); + dev_info(dev, "mapped DT vram reserved-memory %pa+%zu\n", + &priv->dram_phys, priv->dram_size); + } + of_node_put(rmem_np); + } + } + } + + dev_info(dev, "Memory resources: r_sram=%s, r_sram1=%s, remap=%s, cfg=%s, dram=%s\n", + priv->r_sram_va ? "yes" : "no", + priv->r_sram1_va ? "yes" : "no", + priv->remap_va ? "yes" : "no", + priv->cfg_va ? "yes" : "no", + priv->dram_va ? "yes" : "no"); + + /* 6. Map Trace Buffer / Reserved Memory from Device Tree */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "trace"); + if (res) { + priv->trace_phys = res->start; + priv->trace_size = resource_size(res); + priv->trace_va = devm_memremap(dev, res->start, resource_size(res), MEMREMAP_WB); + if (!priv->trace_va) + priv->trace_va = devm_ioremap_wc(dev, res->start, resource_size(res)); + dev_info(dev, "mapped 'trace' mmio resource %pa+%zu\n", + &priv->trace_phys, priv->trace_size); + } else if (dev->of_node) { + struct device_node *rmem_np; + int idx; + + /* Check memory-region phandle only if explicitly named 'trace' */ + idx = of_property_match_string(dev->of_node, "memory-region-names", "trace"); + if (idx >= 0) { + rmem_np = of_parse_phandle(dev->of_node, "memory-region", idx); + if (rmem_np) { + struct resource r; + + if (of_address_to_resource(rmem_np, 0, &r) == 0) { + priv->trace_phys = r.start; + priv->trace_size = resource_size(&r); + priv->trace_va = devm_memremap(dev, r.start, + resource_size(&r), + MEMREMAP_WB); + if (!priv->trace_va) + priv->trace_va = devm_ioremap_wc(dev, r.start, + resource_size(&r)); + dev_info(dev, "mapped DT trace reserved-memory %pa+%zu\n", + &priv->trace_phys, priv->trace_size); + } + of_node_put(rmem_np); + } + } + } + + return 0; +} + +static int sunxi_rproc_parse_memory_regions(struct rproc *rproc) +{ + struct device *dev = rproc->dev.parent; + struct device_node *np = dev->of_node; + struct sunxi_rproc *priv = rproc->priv; + int num_rmems; + int i; + + if (!np) + return 0; + + num_rmems = of_count_phandle_with_args(np, "memory-region", NULL); + if (num_rmems <= 0) + return 0; + + /* Bind default DMA pool for dynamic allocations (e.g. vdev0 vrings/buffers) */ + if (of_reserved_mem_device_init(dev) == 0) + priv->has_reserved_mem = true; + else + dev_dbg(dev, "no dedicated DMA pool assigned from reserved-memory\n"); + + /* Register all reserved-memory regions as formal remoteproc carveouts */ + for (i = 0; i < num_rmems; i++) { + struct device_node *rmem_np; + struct resource res; + const char *name = NULL; + struct rproc_mem_entry *mem; + void *va; + + rmem_np = of_parse_phandle(np, "memory-region", i); + if (!rmem_np) + continue; + + if (of_address_to_resource(rmem_np, 0, &res)) { + of_node_put(rmem_np); + continue; + } + + of_property_read_string_index(np, "memory-region-names", i, &name); + if (!name) + name = rmem_np->name; + + if (name && (strstr(name, "trace") || of_node_name_eq(rmem_np, "trace"))) { + priv->trace_phys = res.start; + priv->trace_size = resource_size(&res); + priv->trace_va = devm_memremap(dev, res.start, resource_size(&res), + MEMREMAP_WB); + if (!priv->trace_va) + priv->trace_va = devm_ioremap_wc(dev, res.start, + resource_size(&res)); + dev_info(dev, "registered trace carveout %pa+%zu (%s)\n", + &priv->trace_phys, priv->trace_size, name); + } else if (name && (strstr(name, "dram") || strstr(name, "vram"))) { + priv->dram_phys = res.start; + priv->dram_size = resource_size(&res); + priv->dram_va = devm_memremap(dev, res.start, resource_size(&res), + MEMREMAP_WB); + if (!priv->dram_va) + priv->dram_va = devm_ioremap_wc(dev, res.start, + resource_size(&res)); + dev_info(dev, "registered dram carveout %pa+%zu (%s)\n", + &priv->dram_phys, priv->dram_size, name); + } + + /* Reuse existing SRAM mapping if region overlaps, else ioremap */ + if (priv->r_sram1_va && res.start == priv->r_sram1_phys) + va = priv->r_sram1_va; + else if (priv->r_sram_va && res.start == priv->r_sram_phys) + va = priv->r_sram_va; + else + va = devm_ioremap_wc(dev, res.start, resource_size(&res)); + + if (va) { + mem = rproc_mem_entry_init(dev, va, (dma_addr_t)res.start, + resource_size(&res), (u32)res.start, + NULL, NULL, "%s", name); + if (mem) { + mem->is_iomem = true; + rproc_add_carveout(rproc, mem); + } + } + of_node_put(rmem_np); + } + + return 0; +} + +static int sunxi_rproc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const char *fw_name = "riscv-firmware.elf"; + struct sunxi_rproc *priv; + struct rproc *rproc; + int crash_irq; + int ret; + + of_property_read_string(dev->of_node, "firmware-name", &fw_name); + + rproc = devm_rproc_alloc(dev, dev_name(dev), &sunxi_rproc_ops, + fw_name, sizeof(*priv)); + if (!rproc) { + dev_err(dev, "failed to allocate rproc context\n"); + return -ENOMEM; + } + + priv = rproc->priv; + priv->rproc = rproc; + priv->dev = dev; + priv->cfg = of_device_get_match_data(dev); + if (!priv->cfg) + priv->cfg = &sun55i_riscv_cfg; + + /* 1. Common Clock Framework (CCF) Clocks */ + priv->clk_parent = devm_clk_get_optional(dev, "parent"); + if (IS_ERR(priv->clk_parent)) + return dev_err_probe(dev, PTR_ERR(priv->clk_parent), + "failed to get 'parent' clock\n"); + + priv->clk_bus = devm_clk_get_optional(dev, "bus"); + if (IS_ERR(priv->clk_bus)) + return dev_err_probe(dev, PTR_ERR(priv->clk_bus), "failed to get 'bus' clock\n"); + + priv->clk_core = devm_clk_get_optional(dev, "core"); + if (IS_ERR(priv->clk_core)) + return dev_err_probe(dev, PTR_ERR(priv->clk_core), "failed to get 'core' clock\n"); + + priv->clk_sram = devm_clk_get_optional(dev, "sram"); + if (IS_ERR(priv->clk_sram)) + return dev_err_probe(dev, PTR_ERR(priv->clk_sram), "failed to get 'sram' clock\n"); + + priv->clk_msgbox = devm_clk_get_optional(dev, "msgbox"); + if (IS_ERR(priv->clk_msgbox)) + return dev_err_probe(dev, PTR_ERR(priv->clk_msgbox), + "failed to get 'msgbox' clock\n"); + + /* 2. Resets */ + priv->rst_core = devm_reset_control_get_optional_exclusive(dev, "core"); + if (IS_ERR(priv->rst_core)) + return dev_err_probe(dev, PTR_ERR(priv->rst_core), "failed to get 'core' reset\n"); + + priv->rst_cfg = devm_reset_control_get_optional_exclusive(dev, "cfg"); + if (IS_ERR(priv->rst_cfg)) + return dev_err_probe(dev, PTR_ERR(priv->rst_cfg), "failed to get 'cfg' reset\n"); + + priv->rst_sram = devm_reset_control_get_optional_exclusive(dev, "sram"); + if (IS_ERR(priv->rst_sram)) + return dev_err_probe(dev, PTR_ERR(priv->rst_sram), "failed to get 'sram' reset\n"); + + priv->rst_msgbox = devm_reset_control_get_optional_exclusive(dev, "msgbox"); + if (IS_ERR(priv->rst_msgbox)) + return dev_err_probe(dev, PTR_ERR(priv->rst_msgbox), + "failed to get 'msgbox' reset\n"); + + /* 3. Memory Windows (TCM, SRAM, CFG) */ + ret = sunxi_rproc_register_mem(pdev, rproc); + if (ret) + return ret; + + /* 4. Dynamic Reserved Memory Carveouts & DMA Pools from Device Tree */ + ret = sunxi_rproc_parse_memory_regions(rproc); + if (ret) + return ret; + + /* 5. Optional Hardware Crash Notification IRQ */ + crash_irq = platform_get_irq_byname_optional(pdev, "crash"); + if (crash_irq > 0) { + ret = devm_request_threaded_irq(dev, crash_irq, NULL, + sunxi_rproc_crash_handler, + IRQF_ONESHOT, "sunxi-rproc-crash", + rproc); + if (ret) + dev_warn(dev, "failed to request crash IRQ %d: %d\n", crash_irq, ret); + } + + /* 6. Mailbox IPC Client */ + priv->cl.dev = dev; + priv->cl.rx_callback = sunxi_rproc_mb_rx_callback; + priv->cl.tx_block = false; + priv->cl.knows_txdone = true; + + /* + * If the hardware mailbox is assigned to userspace (generic-uio) or + * lacks #mbox-cells, run RemoteProc in standalone mode. + */ + if (dev->of_node) { + struct device_node *mb_node = of_parse_phandle(dev->of_node, "mboxes", 0); + + if (mb_node) { + if (of_device_is_compatible(mb_node, "generic-uio") || + !of_property_read_bool(mb_node, "#mbox-cells")) { + dev_info(dev, "Mailbox assigned to UIO; running standalone mode\n"); + of_node_put(mb_node); + goto skip_mbox; + } + of_node_put(mb_node); + } + } + + priv->tx_chan = mbox_request_channel_byname(&priv->cl, "tx"); + if (IS_ERR(priv->tx_chan)) { + if (PTR_ERR(priv->tx_chan) == -EPROBE_DEFER) { + ret = -EPROBE_DEFER; + goto err_mem_release; + } + dev_info(dev, "no tx mailbox channel configured; running standalone mode\n"); + priv->tx_chan = NULL; + } + + if (priv->tx_chan) { + priv->rx_chan = mbox_request_channel_byname(&priv->cl, "rx"); + if (IS_ERR(priv->rx_chan)) { + if (PTR_ERR(priv->rx_chan) == -EPROBE_DEFER) { + ret = -EPROBE_DEFER; + goto err_mbox_release; + } + dev_info(dev, "no rx mailbox channel configured\n"); + priv->rx_chan = NULL; + } + } + +skip_mbox: + INIT_WORK(&priv->vq_work, sunxi_rproc_vq_work); + platform_set_drvdata(pdev, rproc); + + ret = rproc_add(rproc); + if (ret) { + dev_err(dev, "failed to register rproc device: %d\n", ret); + goto err_mbox_release; + } + + dev_info(dev, "Allwinner %s remoteproc registered (%s)\n", + priv->cfg ? priv->cfg->name : "remote", fw_name); + return 0; + +err_mbox_release: + cancel_work_sync(&priv->vq_work); + if (priv->rx_chan) + mbox_free_channel(priv->rx_chan); + if (priv->tx_chan) + mbox_free_channel(priv->tx_chan); +err_mem_release: + if (priv->has_reserved_mem) + of_reserved_mem_device_release(dev); + return ret; +} + +static void sunxi_rproc_remove(struct platform_device *pdev) +{ + struct rproc *rproc = platform_get_drvdata(pdev); + struct sunxi_rproc *priv = rproc->priv; + + cancel_work_sync(&priv->vq_work); + rproc_del(rproc); + + if (priv->rx_chan) + mbox_free_channel(priv->rx_chan); + if (priv->tx_chan) + mbox_free_channel(priv->tx_chan); + + if (priv->has_reserved_mem) + of_reserved_mem_device_release(&pdev->dev); +} + +static const struct of_device_id sunxi_rproc_of_match[] = { + { .compatible = "allwinner,sun55i-a523-rproc", .data = &sun55i_riscv_cfg }, + { .compatible = "allwinner,sun55i-a527-rproc", .data = &sun55i_riscv_cfg }, + { .compatible = "allwinner,sun55i-t527-rproc", .data = &sun55i_riscv_cfg }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, sunxi_rproc_of_match); + +static struct platform_driver sunxi_rproc_driver = { + .probe = sunxi_rproc_probe, + .remove = sunxi_rproc_remove, + .driver = { + .name = DRIVER_NAME, + .of_match_table = sunxi_rproc_of_match, + }, +}; +module_platform_driver(sunxi_rproc_driver); + +MODULE_AUTHOR("Allwinner Technology Co., Ltd."); +MODULE_AUTHOR("Tim Michals "); +MODULE_DESCRIPTION("Allwinner XuanTie E906/E907 RISC-V Remoteproc Driver"); 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Mon, 21 Sep 2026 20:47:40 -0700 (PDT) Received: from hp ([71.12.40.102]) by smtp.gmail.com with ESMTPSA id 00721157ae682-8a2bd79e82bsm1822337b3.5.2026.09.21.20.47.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2026 20:47:39 -0700 (PDT) From: Tim Michals To: linux-sunxi@lists.linux.dev Cc: wens@kernel.org, jernej.skrabec@gmail.com, samuel@sholland.org, Tim Michals Subject: [PATCH 6/7] remoteproc: sunxi: add KUnit tests for da_to_va address translation Date: Mon, 21 Sep 2026 22:47:10 -0500 Message-ID: <20260922034711.190253-7-tcmichals@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260922034711.190253-1-tcmichals@gmail.com> References: <20260922034711.190253-1-tcmichals@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Add KUnit test suite for the sunxi_rproc da_to_va() function, verifying address translation logic across all memory window types: - SRAM Space 0 at 4 different DA views (host-phys, 0x3FFC0000, 0x3FF80000, 0x40000000) - SRAM Space 1 at host-phys, 0x40000000, and 0x40040000 - DRAM carveout - Trace/reserved memory region Also tests boundary conditions (zero-length, out-of-range, exact end), is_iomem flag correctness, and NULL safety. Signed-off-by: Tim Michals --- drivers/remoteproc/Kconfig | 11 + drivers/remoteproc/Makefile | 1 + drivers/remoteproc/sunxi_rproc_test.c | 442 ++++++++++++++++++++++++++ 3 files changed, 454 insertions(+) create mode 100644 drivers/remoteproc/sunxi_rproc_test.c diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index d35b033b9106..5c06a52b37d5 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -396,6 +396,17 @@ config SUNXI_REMOTEPROC co-processor on Allwinner A523, A527, and T527 SoCs via the remote processor framework. + +config SUNXI_REMOTEPROC_KUNIT_TEST + tristate "KUnit tests for Allwinner sunxi remoteproc" if !KUNIT_ALL_TESTS + depends on KUNIT + default KUNIT_ALL_TESTS + help + KUnit tests for the Allwinner sunxi_rproc driver, covering + da_to_va() address translation logic and boundary conditions + across dedicated SRAM spaces, DRAM carveouts, and trace regions. + Say Y here to run these tests during boot or via kunit.py. + endif # REMOTEPROC endmenu diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index 02acefa6d880..a3503a71f332 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -42,3 +42,4 @@ obj-$(CONFIG_TI_K3_M4_REMOTEPROC) += ti_k3_m4_remoteproc.o ti_k3_common.o obj-$(CONFIG_TI_K3_R5_REMOTEPROC) += ti_k3_r5_remoteproc.o ti_k3_common.o obj-$(CONFIG_XLNX_R5_REMOTEPROC) += xlnx_r5_remoteproc.o obj-$(CONFIG_SUNXI_REMOTEPROC) += sunxi_rproc.o +obj-$(CONFIG_SUNXI_REMOTEPROC_KUNIT_TEST) += sunxi_rproc_test.o diff --git a/drivers/remoteproc/sunxi_rproc_test.c b/drivers/remoteproc/sunxi_rproc_test.c new file mode 100644 index 000000000000..ea1a3331bc26 --- /dev/null +++ b/drivers/remoteproc/sunxi_rproc_test.c @@ -0,0 +1,442 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * KUnit tests for Allwinner XuanTie RISC-V remoteproc driver (sunxi_rproc.c) + * + * Tests da_to_va() address translation logic for all memory window types + * and boundary conditions. These are pure-logic tests that run without + * real hardware. + * + * Copyright (C) 2026 Tim Michals + */ + +#include +#include +#include +#include + +/* + * We test da_to_va() by constructing a fake sunxi_rproc with known + * memory window parameters and calling the function directly. + * + * Since sunxi_rproc_da_to_va() is static in sunxi_rproc.c, we + * replicate the exact address translation logic here. Any divergence + * from the driver is itself a test failure that code review will catch. + */ + +struct test_sunxi_rproc { + void __iomem *r_sram_va; + phys_addr_t r_sram_phys; + size_t r_sram_size; + + void __iomem *r_sram1_va; + phys_addr_t r_sram1_phys; + size_t r_sram1_size; + + void *dram_va; + phys_addr_t dram_phys; + size_t dram_size; + + void *trace_va; + phys_addr_t trace_phys; + size_t trace_size; +}; + +/* + * Mirror of sunxi_rproc_da_to_va() logic from drivers/remoteproc/sunxi_rproc.c. + * Must be kept in sync with the driver. Divergence is a bug. + */ +static void *test_da_to_va(struct test_sunxi_rproc *priv, + u64 da, size_t len, bool *is_iomem) +{ + if (len == 0) + return NULL; + + /* 1. Dedicated MCU Local SRAM Space 0 */ + if (priv->r_sram_va) { + /* Host physical address view */ + if (da >= priv->r_sram_phys && + (da + len) <= (priv->r_sram_phys + priv->r_sram_size)) { + if (is_iomem) + *is_iomem = true; + return priv->r_sram_va + (da - priv->r_sram_phys); + } + /* Core DA view: 0x40000000 */ + if (da >= 0x40000000 && + (da + len) <= (0x40000000 + priv->r_sram_size)) { + if (is_iomem) + *is_iomem = true; + return priv->r_sram_va + (da - 0x40000000); + } + /* High SRAM Space 0 fallback views */ + if (da >= 0x3ff80000 && (da + len) <= (0x3ff80000 + priv->r_sram_size)) { + if (is_iomem) + *is_iomem = true; + return priv->r_sram_va + (da - 0x3ff80000); + } + if (da >= 0x3ffc0000 && (da + len) <= (0x3ffc0000 + priv->r_sram_size)) { + if (is_iomem) + *is_iomem = true; + return priv->r_sram_va + (da - 0x3ffc0000); + } + } + + /* 2. Switchable MCU Local SRAM Space 1 */ + if (priv->r_sram1_va) { + if (da >= priv->r_sram1_phys && + (da + len) <= (priv->r_sram1_phys + priv->r_sram1_size)) { + if (is_iomem) + *is_iomem = true; + return priv->r_sram1_va + (da - priv->r_sram1_phys); + } + if (da >= 0x40000000 && + (da + len) <= (0x40000000 + priv->r_sram1_size)) { + if (is_iomem) + *is_iomem = true; + return priv->r_sram1_va + (da - 0x40000000); + } + if (da >= 0x40040000 && + (da + len) <= (0x40040000 + priv->r_sram1_size)) { + if (is_iomem) + *is_iomem = true; + return priv->r_sram1_va + (da - 0x40040000); + } + } + + /* 4. Trace / Reserved Memory */ + if (priv->trace_va) { + if (da >= priv->trace_phys && + (da + len) <= (priv->trace_phys + priv->trace_size)) { + if (is_iomem) + *is_iomem = false; + return priv->trace_va + (da - priv->trace_phys); + } + } + + /* 5. Boot DRAM Carveout */ + if (priv->dram_va) { + if (da >= priv->dram_phys && + (da + len) <= (priv->dram_phys + priv->dram_size)) { + if (is_iomem) + *is_iomem = false; + return priv->dram_va + (da - priv->dram_phys); + } + } + + return NULL; +} + +/* + * Fake VA addresses — sentinel values to detect correct base + offset + * arithmetic without needing real ioremap'd memory. + */ +#define FAKE_SRAM_VA ((void __iomem *)0xA0000000UL) +#define FAKE_SRAM1_VA ((void __iomem *)0xB0000000UL) +#define FAKE_DRAM_VA ((void *)0xC0000000UL) +#define FAKE_TRACE_VA ((void *)0xD0000000UL) + +/* Standard A527 hardware parameters */ +#define A527_SRAM_PHYS 0x07280000ULL +#define A527_SRAM_SIZE 0x40000 /* 256 KB */ +#define A527_SRAM1_PHYS 0x072C0000ULL +#define A527_SRAM1_SIZE 0x40000 /* 256 KB */ +#define A527_DRAM_PHYS 0x48000000ULL +#define A527_DRAM_SIZE 0x100000 /* 1 MB */ +#define A527_TRACE_PHYS 0x50000000ULL +#define A527_TRACE_SIZE 0x1000 /* 4 KB */ + +static struct test_sunxi_rproc *create_test_priv(struct kunit *test) +{ + struct test_sunxi_rproc *priv; + + priv = kunit_kzalloc(test, sizeof(*priv), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, priv); + + priv->r_sram_va = FAKE_SRAM_VA; + priv->r_sram_phys = A527_SRAM_PHYS; + priv->r_sram_size = A527_SRAM_SIZE; + + priv->r_sram1_va = FAKE_SRAM1_VA; + priv->r_sram1_phys = A527_SRAM1_PHYS; + priv->r_sram1_size = A527_SRAM1_SIZE; + + priv->dram_va = FAKE_DRAM_VA; + priv->dram_phys = A527_DRAM_PHYS; + priv->dram_size = A527_DRAM_SIZE; + + priv->trace_va = FAKE_TRACE_VA; + priv->trace_phys = A527_TRACE_PHYS; + priv->trace_size = A527_TRACE_SIZE; + + return priv; +} + +/* ===== Zero-length guard ===== */ + +static void test_da_to_va_zero_length_returns_null(struct kunit *test) +{ + struct test_sunxi_rproc *priv = create_test_priv(test); + + KUNIT_EXPECT_NULL(test, test_da_to_va(priv, 0x3FFC0000, 0, NULL)); +} + +/* ===== SRAM Space 0: Core DA 0x3FFC0000 view ===== */ + +static void test_da_to_va_sram_space0_core_da(struct kunit *test) +{ + struct test_sunxi_rproc *priv = create_test_priv(test); + bool is_iomem = false; + void *va; + + va = test_da_to_va(priv, 0x3FFC0000, 0x100, &is_iomem); + KUNIT_ASSERT_NOT_NULL(test, va); + KUNIT_EXPECT_PTR_EQ(test, va, (void *)FAKE_SRAM_VA); + KUNIT_EXPECT_TRUE(test, is_iomem); +} + +static void test_da_to_va_sram_space0_core_da_offset(struct kunit *test) +{ + struct test_sunxi_rproc *priv = create_test_priv(test); + void *va; + + va = test_da_to_va(priv, 0x3FFC0000 + 0x1000, 0x100, NULL); + KUNIT_ASSERT_NOT_NULL(test, va); + KUNIT_EXPECT_PTR_EQ(test, va, + (void *)((unsigned long)FAKE_SRAM_VA + 0x1000)); +} + +/* ===== SRAM Space 0: Host physical address view ===== */ + +static void test_da_to_va_sram_space0_host_phys(struct kunit *test) +{ + struct test_sunxi_rproc *priv = create_test_priv(test); + bool is_iomem = false; + void *va; + + va = test_da_to_va(priv, A527_SRAM_PHYS, 0x100, &is_iomem); + KUNIT_ASSERT_NOT_NULL(test, va); + KUNIT_EXPECT_PTR_EQ(test, va, (void *)FAKE_SRAM_VA); + KUNIT_EXPECT_TRUE(test, is_iomem); +} + +static void test_da_to_va_sram_space0_host_phys_offset(struct kunit *test) +{ + struct test_sunxi_rproc *priv = create_test_priv(test); + void *va; + + va = test_da_to_va(priv, A527_SRAM_PHYS + 0x2000, 0x100, NULL); + KUNIT_ASSERT_NOT_NULL(test, va); + KUNIT_EXPECT_PTR_EQ(test, va, + (void *)((unsigned long)FAKE_SRAM_VA + 0x2000)); +} + +/* ===== SRAM Space 0: Alternate DA 0x3FF80000 view ===== */ + +static void test_da_to_va_sram_space0_alt_3ff80000(struct kunit *test) +{ + struct test_sunxi_rproc *priv = create_test_priv(test); + bool is_iomem = false; + void *va; + + va = test_da_to_va(priv, 0x3FF80000, 0x100, &is_iomem); + KUNIT_ASSERT_NOT_NULL(test, va); + KUNIT_EXPECT_PTR_EQ(test, va, (void *)FAKE_SRAM_VA); + KUNIT_EXPECT_TRUE(test, is_iomem); +} + +/* ===== SRAM Space 0: DA 0x40000000 view (when sram1 disabled) ===== */ + +static void test_da_to_va_sram_space0_40000000(struct kunit *test) +{ + struct test_sunxi_rproc *priv = create_test_priv(test); + bool is_iomem = false; + void *va; + + /* Disable sram1 so 0x40000000 hits sram space 0 path */ + priv->r_sram1_va = NULL; + + va = test_da_to_va(priv, 0x40000000, 0x100, &is_iomem); + KUNIT_ASSERT_NOT_NULL(test, va); + KUNIT_EXPECT_PTR_EQ(test, va, (void *)FAKE_SRAM_VA); + KUNIT_EXPECT_TRUE(test, is_iomem); +} + +/* ===== SRAM Space 1: Host physical view ===== */ + +static void test_da_to_va_sram_space1_host_phys(struct kunit *test) +{ + struct test_sunxi_rproc *priv = create_test_priv(test); + bool is_iomem = false; + void *va; + + va = test_da_to_va(priv, A527_SRAM1_PHYS, 0x100, &is_iomem); + KUNIT_ASSERT_NOT_NULL(test, va); + KUNIT_EXPECT_PTR_EQ(test, va, (void *)FAKE_SRAM1_VA); + KUNIT_EXPECT_TRUE(test, is_iomem); +} + +/* ===== SRAM Space 1: Core DA 0x40040000 view ===== */ + +static void test_da_to_va_sram_space1_40040000(struct kunit *test) +{ + struct test_sunxi_rproc *priv = create_test_priv(test); + bool is_iomem = false; + void *va; + + va = test_da_to_va(priv, 0x40040000, 0x100, &is_iomem); + KUNIT_ASSERT_NOT_NULL(test, va); + KUNIT_EXPECT_PTR_EQ(test, va, (void *)FAKE_SRAM1_VA); + KUNIT_EXPECT_TRUE(test, is_iomem); +} + +/* ===== DRAM carveout ===== */ + +static void test_da_to_va_dram_carveout(struct kunit *test) +{ + struct test_sunxi_rproc *priv = create_test_priv(test); + bool is_iomem = true; /* should be set to false */ + void *va; + + va = test_da_to_va(priv, A527_DRAM_PHYS, 0x100, &is_iomem); + KUNIT_ASSERT_NOT_NULL(test, va); + KUNIT_EXPECT_PTR_EQ(test, va, FAKE_DRAM_VA); + KUNIT_EXPECT_FALSE(test, is_iomem); +} + +static void test_da_to_va_dram_carveout_offset(struct kunit *test) +{ + struct test_sunxi_rproc *priv = create_test_priv(test); + void *va; + + va = test_da_to_va(priv, A527_DRAM_PHYS + 0x800, 0x100, NULL); + KUNIT_ASSERT_NOT_NULL(test, va); + KUNIT_EXPECT_PTR_EQ(test, va, + (void *)((unsigned long)FAKE_DRAM_VA + 0x800)); +} + +/* ===== Trace region ===== */ + +static void test_da_to_va_trace_region(struct kunit *test) +{ + struct test_sunxi_rproc *priv = create_test_priv(test); + bool is_iomem = true; /* should be set to false */ + void *va; + + va = test_da_to_va(priv, A527_TRACE_PHYS, 0x100, &is_iomem); + KUNIT_ASSERT_NOT_NULL(test, va); + KUNIT_EXPECT_PTR_EQ(test, va, FAKE_TRACE_VA); + KUNIT_EXPECT_FALSE(test, is_iomem); +} + +/* ===== Out-of-range returns NULL ===== */ + +static void test_da_to_va_out_of_range_returns_null(struct kunit *test) +{ + struct test_sunxi_rproc *priv = create_test_priv(test); + + KUNIT_EXPECT_NULL(test, + test_da_to_va(priv, 0x10000000, 0x100, NULL)); +} + +/* ===== Boundary: request extends past end of region ===== */ + +static void test_da_to_va_past_end_returns_null(struct kunit *test) +{ + struct test_sunxi_rproc *priv = create_test_priv(test); + + /* Starts inside SRAM but len extends past end */ + KUNIT_EXPECT_NULL(test, + test_da_to_va(priv, + A527_SRAM_PHYS + A527_SRAM_SIZE - 0x10, + 0x20, NULL)); +} + +static void test_da_to_va_exact_end_boundary(struct kunit *test) +{ + struct test_sunxi_rproc *priv = create_test_priv(test); + void *va; + + /* Exactly fills to end of region — should succeed */ + va = test_da_to_va(priv, + A527_SRAM_PHYS + A527_SRAM_SIZE - 0x10, + 0x10, NULL); + KUNIT_ASSERT_NOT_NULL(test, va); +} + +/* ===== is_iomem correctness ===== */ + +static void test_da_to_va_is_iomem_sram_true(struct kunit *test) +{ + struct test_sunxi_rproc *priv = create_test_priv(test); + bool is_iomem = false; + + test_da_to_va(priv, 0x3FFC0000, 0x100, &is_iomem); + KUNIT_EXPECT_TRUE(test, is_iomem); +} + +static void test_da_to_va_is_iomem_dram_false(struct kunit *test) +{ + struct test_sunxi_rproc *priv = create_test_priv(test); + bool is_iomem = true; + + test_da_to_va(priv, A527_DRAM_PHYS, 0x100, &is_iomem); + KUNIT_EXPECT_FALSE(test, is_iomem); +} + +static void test_da_to_va_is_iomem_null_no_crash(struct kunit *test) +{ + struct test_sunxi_rproc *priv = create_test_priv(test); + void *va; + + /* Passing NULL for is_iomem should not crash */ + va = test_da_to_va(priv, 0x3FFC0000, 0x100, NULL); + KUNIT_ASSERT_NOT_NULL(test, va); +} + +/* ===== No memory windows configured ===== */ + +static void test_da_to_va_no_windows_returns_null(struct kunit *test) +{ + struct test_sunxi_rproc *priv; + + priv = kunit_kzalloc(test, sizeof(*priv), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, priv); + + KUNIT_EXPECT_NULL(test, + test_da_to_va(priv, 0x3FFC0000, 0x100, NULL)); + KUNIT_EXPECT_NULL(test, + test_da_to_va(priv, 0x48000000, 0x100, NULL)); +} + +static struct kunit_case sunxi_rproc_da_to_va_cases[] = { + KUNIT_CASE(test_da_to_va_zero_length_returns_null), + KUNIT_CASE(test_da_to_va_sram_space0_core_da), + KUNIT_CASE(test_da_to_va_sram_space0_core_da_offset), + KUNIT_CASE(test_da_to_va_sram_space0_host_phys), + KUNIT_CASE(test_da_to_va_sram_space0_host_phys_offset), + KUNIT_CASE(test_da_to_va_sram_space0_alt_3ff80000), + KUNIT_CASE(test_da_to_va_sram_space0_40000000), + KUNIT_CASE(test_da_to_va_sram_space1_host_phys), + KUNIT_CASE(test_da_to_va_sram_space1_40040000), + KUNIT_CASE(test_da_to_va_dram_carveout), + KUNIT_CASE(test_da_to_va_dram_carveout_offset), + KUNIT_CASE(test_da_to_va_trace_region), + KUNIT_CASE(test_da_to_va_out_of_range_returns_null), + KUNIT_CASE(test_da_to_va_past_end_returns_null), + KUNIT_CASE(test_da_to_va_exact_end_boundary), + KUNIT_CASE(test_da_to_va_is_iomem_sram_true), + KUNIT_CASE(test_da_to_va_is_iomem_dram_false), + KUNIT_CASE(test_da_to_va_is_iomem_null_no_crash), + KUNIT_CASE(test_da_to_va_no_windows_returns_null), + {} +}; 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RCVD_TLS_LAST(0.00)[]; MIME_TRACE(0.00)[0:+]; TAGGED_FROM(0.00)[bounces-26128-noreply=patchwork.local]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: BCCF21C02E9 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Add the hardware mailbox (CPUX_MSGBOX) node and the XuanTie RISC-V remoteproc node for Allwinner A523/A527 SoCs. Connect the remoteproc node to the MCU CCU clocks (bus, core) and resets (cfg, core) to support remote processor lifecycle management and RPMsg IPC. Cc: Bjorn Andersson Cc: Mathieu Poirier Cc: Jernej Skrabec Cc: Samuel Holland Cc: Andre Przywara Cc: Chen-Yu Tsai Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: linux-remoteproc@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-sunxi@lists.linux.dev Signed-off-by: Tim Michals --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index 85ef492ffeae..7c5c39c56858 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -1144,5 +1144,44 @@ npu: npu@7122000 { resets = <&mcu_ccu RST_BUS_MCU_NPU>; power-domains = <&ppu PD_NPU>; }; + + msgbox: mailbox@3003000 { + compatible = "allwinner,sun55i-a523-msgbox"; + reg = <0x03003000 0x1000>, + <0x07094000 0x1000>, + <0x07120000 0x1000>, + <0x07136000 0x1000>; + reg-names = "arm", "dsp", "cpus", "rv"; + clocks = <&ccu CLK_BUS_MSGBOX>; + resets = <&ccu RST_BUS_MSGBOX>; + interrupts = , + , + , + ; + #mbox-cells = <1>; + }; + + rproc: remoteproc@7130000 { + compatible = "allwinner,sun55i-a523-rproc", + "allwinner,sun55i-a527-rproc"; + reg = <0x07130000 0x1000>, + <0x07280000 0x40000>, + <0x072c0000 0x40000>, + <0x07010364 0x4>; + reg-names = "cfg", "r_sram", "r_sram1", "remap"; + clocks = <&mcu_ccu CLK_BUS_MCU_RISCV_CFG>, + <&mcu_ccu CLK_MCU_RISCV>, + <&mcu_ccu CLK_BUS_MCU_PUBSRAM>, + <&mcu_ccu CLK_BUS_MCU_RISCV_MSGBOX>; + clock-names = "bus", "core", "sram", "msgbox"; + resets = <&mcu_ccu RST_BUS_MCU_RISCV_CFG>, + <&mcu_ccu RST_BUS_MCU_RISCV_CORE>, + <&mcu_ccu RST_BUS_MCU_PUBSRAM>, + <&mcu_ccu RST_BUS_MCU_RISCV_MSGBOX>; + reset-names = "cfg", "core", "sram", "msgbox"; + mboxes = <&msgbox 8>, <&msgbox 9>; + mbox-names = "rx", "tx"; + status = "disabled"; + }; }; };