From patchwork Wed Sep 23 05:36:14 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hilliard X-Patchwork-Id: 3426 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 022BA1C1038 for ; Wed, 23 Sep 2026 07:36:46 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=gmail.com; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-26159-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; envelope-from=linux-sunxi+bounces-26159-noreply=patchwork.local@lists.linux.dev; helo=sea.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sea.lore.kernel.org (Postfix) with ESMTP id 084A42C6B8 for ; Wed, 23 Sep 2026 05:36:27 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D4F264349B9; Wed, 23 Sep 2026 05:36:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="sE8n6NLt" X-Original-To: linux-sunxi@lists.linux.dev Received: from mail-oi2-f13.google.com (mail-oi2-f13.google.com [74.125.231.205]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F67A3F6C55 for ; Wed, 23 Sep 2026 05:36:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.231.205 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790141786; cv=none; b=RMGXnbgqAoPLedsDAhxxGR6i5mTKGz0X3990wRvrU5Xz4nMv9pXaPNwY3oq+B1FXdjt3bJnKU7vXTkJX/CtwXCO+zGbTIa9GLkK5MJNx5jZdG69F28Im7qyLHTanHfI6rLdgSDBDLZdAw1OIJSPyKDuz/dKkt8yP4DKlowzRWGQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790141786; c=relaxed/simple; bh=5k9VLU6OvtrGZi0gO1yZy16OfwqfrZmQwujeqIifWv0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pLpt5d7wYxF2U4P6fQdFtY+fMyldZd3yyuJmL213WjW+q0clX4Xp34798MumbmZaiIKxfrmEhDhshf847vt8iTdxpYEKq4qOJTZfenZOcC4hMN+I5VlmrKBzhMq1tIqVUAFyjIErAoox1VI1GZfdpgcNNpyBwsjDrb6WCXnw6cM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=sE8n6NLt; arc=none smtp.client-ip=74.125.231.205 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-oi2-f13.google.com with SMTP id 5614622812f47-4b37a3688a2so516005b6e.0 for ; Tue, 22 Sep 2026 22:36:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1790141784; x=1790746584; darn=lists.linux.dev; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=M4cUR/bgVx/Ef4Tc/Iqux+0dgmZ5BenjLrR4X+eBZEU=; b=sE8n6NLtWLFvddfvL9/e7QdrDyxIIIuyXDGjUNjEKpAqIWPckZHoJT3v+Ybrjq0v/d LlTIIFB83JIR+q+xzt21rmGRjpnD1BhTu9Cbjqq3Dn/bz5JKX5qc6LX+tmydwFOM1NlL AwuZPUmP6lPxaUTd75PsYPPYDmQzfHu5GWBf5tvYjEI+Ino56/yJLwEgJmpEQ9sfnsx+ jZ+/WsmwdPpm0RJ/04JB0mqXtA+247HrQ6nF7h6L8CgJDcwhJthzYJ6EAhzSsoCauwqc KWLbcta6nvMibUd2NwoXUK71P/EurRpUkn/o5LiSCmLuiPWRPEIL1NFrT2INGp6Wcl42 RK7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1790141784; x=1790746584; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=M4cUR/bgVx/Ef4Tc/Iqux+0dgmZ5BenjLrR4X+eBZEU=; b=0KdHZBvpdjnxCo2ScrS2+3/KGJLyyI1MpPGNLRV8/islS6tsCCgbB2yMTCLjzesxZs ny363m9/tPMKkOlX8Alhe4FzRMDLqS/teju7H0E0+15CNO8O6CRL/hqvGw9XJzrSJnYd YnJ6WpQzTq3JvtFdedUJuq6wLnn2SDW1w1JnJ0INtkckWW/Xt5XjDDlP56/dVHq2X5KU G0U+q3LxWJdupLMq32ncQ5Z5fB2Fx/badeMzKvan4mF6uWcvTWNhJKwJxrfzKYP7pngG CxpW+6+I7Cqf+7jjZbR7Rg16hAANMJ3aaSMu44PjaaHUM7PrYgHxaNgNiHpxM1qgPmzy gtfg== X-Forwarded-Encrypted: i=1; AKwUvBxUgPlha3jwo3ZBoZEHJUys3tHE6Y1Dz2lhA7tEPXAp9rt+trxkvrsgIqHu7+AbPBXOtjIAZtw1vrdmmw==@lists.linux.dev X-Gm-Message-State: AFuF++mqv80pKtSvpxp20RAAQIlvXgGD2IPHgSkuHKxJ0FCUPqHYFi1S kvls2yrQcWn8zf7eLqU4Vzk8SZDzzlOmLzArv8EZkowbv7MN6NMuD3oIGABQlvxM X-Gm-Gg: AYBFou15YGQf6KxvW+LNHKcg1eY64TjK/EVplXspG4bx7SeQlYufjDr+RK9g2f1+AUl 1qi+yiJRTtSeWtmeUeyyj9JMyXvUw9Xk+z4ujAYaHxCo9ZLoYxLRzYeVGi8nlEi2hm7pMSGU4tn 7a8l8YiJDyMYCIreV6ve/8xsbF7oaFVdW+968/UtqV+z2VuuwykBKNlO+edCcTj2JPSW8yjbx9G j/Q46JdJOrGOmMRG39XhU3BW2By1rO3ZLHL7cEYDMlckSc1h8Cc5fTns0QDTn/ahe68oPe97HKX n/ogNMHUnNq5f6k/EQvQDJ+LJcnCObqUKwofeDijAKCDGUQs1S1t8vLhtYqAmXA0jLDbHiCPDAb 9XLggMvCI0Djo1foSaZ3CbULAhaPcl0PNALW400xqsLoZb/SF3il0HaoUMeAMO2cpAdn/5czo4D 9vgEfq4PuVKBE5sR3b8O7yhVVDj8cQtnd9zDiuffQZzBAE6QeVWX1FsadqmHUdPZIsOi/1SQL6f 9t19KuTVaQPwAW52oR5Yuqql2dVALgPr36O8oGFGQSA/0RJYZ5PUGYCNCsba84GzjaMrwJYUE/q 9wseI5nl93X+QVeZkz7LUz2L25SklNWRZFEnBLe2XQ37VqnZp7lIEvqjRloFLOzq1iTH/x78SIC yamcpS4L6yQ1ZmV0cF28Q X-Received: by 2002:a05:6808:6b8a:b0:4c1:9127:c0fb with SMTP id 5614622812f47-4d5ba3c38b4mr1883196b6e.36.1790141784089; Tue, 22 Sep 2026 22:36:24 -0700 (PDT) Received: from [127.0.1.1] (174-29-1-49.hlrn.qwest.net. [174.29.1.49]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4d5c4aed99bsm1436896b6e.12.2026.09.22.22.36.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 22:36:23 -0700 (PDT) From: James Hilliard Date: Tue, 22 Sep 2026 23:36:14 -0600 Subject: [PATCH v10 1/5] dt-bindings: pwm: allwinner: add h616 pwm compatible Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260922-h616-pwm-v8-v10-1-dccebbe1aabf@gmail.com> References: <20260922-h616-pwm-v8-v10-0-dccebbe1aabf@gmail.com> In-Reply-To: <20260922-h616-pwm-v8-v10-0-dccebbe1aabf@gmail.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Stephen Boyd , Brian Masney , Jerome Brunet , Richard Genoud , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard Cc: Philipp Zabel , Michael Turquette , Paul Kocialkowski , Thomas Petazzoni , John Stultz , Joao Schim , bigunclemax@gmail.com, linux-pwm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, James Hilliard , Conor Dooley X-Mailer: b4 0.15.2 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-1.16 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.234.253.10:from]; SUSPICIOUS_RECIPS(1.50)[]; DMARC_POLICY_SOFTFAIL(1.00)[gmail.com : SPF not aligned (relaxed), No valid DKIM,none]; MAILLIST(-0.15)[generic]; MIME_GOOD(-0.10)[text/plain]; BAD_REP_POLICIES(0.10)[]; HAS_LIST_UNSUB(-0.01)[]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; RCPT_COUNT_TWELVE(0.00)[27]; FROM_HAS_DN(0.00)[]; PRECEDENCE_BULK(0.00)[]; TAGGED_RCPT(0.00)[clk,dt]; FORGED_SENDER_MAILLIST(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[sea.lore.kernel.org:rdns,sea.lore.kernel.org:helo,microchip.com:email,bootlin.com:email]; FREEMAIL_CC(0.00)[pengutronix.de,baylibre.com,sys-base.io,bootlin.com,google.com,schimsalabim.eu,gmail.com,vger.kernel.org,lists.infradead.org,lists.linux.dev,microchip.com]; RCVD_VIA_SMTP_AUTH(0.00)[]; RCVD_COUNT_FIVE(0.00)[6]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; FREEMAIL_FROM(0.00)[gmail.com]; R_SPF_ALLOW(0.00)[+ip4:172.234.253.10]; TO_DN_SOME(0.00)[]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[174.29.1.49:received,100.90.174.1:received]; FROM_NEQ_ENVFROM(0.00)[jameshilliard1@gmail.com,linux-sunxi@lists.linux.dev]; FREEMAIL_TO(0.00)[kernel.org,redhat.com,baylibre.com,bootlin.com,gmail.com,sholland.org]; MIME_TRACE(0.00)[0:+]; TAGGED_FROM(0.00)[bounces-26159-noreply=patchwork.local]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; RCVD_TLS_LAST(0.00)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.234.253.10:from] X-Rspamd-Queue-Id: 022BA1C1038 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= From: Richard Genoud The Allwinner H616 PWM block differs from the A10 and H6 blocks, but it uses the same input clocks as H6, so extend the existing Allwinner PWM binding. The block has six channels that can generate PWM waveforms. Each channel also has a bypass that turns its output into a clock suitable for consumers such as the integrated X-Powers AC200 or AC300 Ethernet PHY. Require #clock-cells for H616 because the bypass clocks are part of its provider interface, while continuing to disallow the property for the older variants. Acked-by: Conor Dooley Signed-off-by: Richard Genoud Signed-off-by: James Hilliard --- .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 33 +++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml index 1197858e431f..3b1819c8630c 100644 --- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml @@ -14,6 +14,13 @@ properties: "#pwm-cells": const: 3 + "#clock-cells": + const: 1 + description: + The cell selects the PWM channel whose hardware bypass path is exported + as a clock. Its rate follows the selected shared pair source and divider; + the PWM period, duty-cycle and polarity logic is bypassed. + compatible: oneOf: - const: allwinner,sun4i-a10-pwm @@ -36,6 +43,7 @@ properties: - const: allwinner,sun50i-h5-pwm - const: allwinner,sun5i-a13-pwm - const: allwinner,sun50i-h6-pwm + - const: allwinner,sun50i-h616-pwm reg: maxItems: 1 @@ -62,7 +70,9 @@ allOf: properties: compatible: contains: - const: allwinner,sun50i-h6-pwm + enum: + - allwinner,sun50i-h6-pwm + - allwinner,sun50i-h616-pwm then: properties: @@ -83,6 +93,27 @@ allOf: clocks: maxItems: 1 + - if: + properties: + compatible: + contains: + const: allwinner,sun50i-h616-pwm + + then: + properties: + clocks: + minItems: 2 + + clock-names: + minItems: 2 + + required: + - "#clock-cells" + + else: + properties: + "#clock-cells": false + required: - compatible - reg From patchwork Wed Sep 23 05:36:15 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hilliard X-Patchwork-Id: 3429 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 8194F1C0750 for ; Wed, 23 Sep 2026 07:37:43 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=gmail.com; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-26162-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; envelope-from=linux-sunxi+bounces-26162-noreply=patchwork.local@lists.linux.dev; helo=sea.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sea.lore.kernel.org (Postfix) with ESMTP id 42B4839860 for ; Wed, 23 Sep 2026 05:36:36 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5FAE543CE46; Wed, 23 Sep 2026 05:36:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gMd9NIgs" X-Original-To: linux-sunxi@lists.linux.dev Received: from mail-oi2-f13.google.com (mail-oi2-f13.google.com [74.125.231.205]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0F954399DB for ; Wed, 23 Sep 2026 05:36:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.231.205 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790141793; cv=none; b=tnUm/vGRVsX397PrYJn6EcLDpExExGxoUerOFIE8MZNDWPJmreXDJeoCmBRSogGPcNLBiTmY3277iGVC2c3AYD/KmexFjWRefCZdqyp3bTEBSGmHfJJUx+S9GozgghTsHP5aXwh5RYxD9ZgZxw60Nw8xYWSxRa3MOiKP4zdfgbM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790141793; c=relaxed/simple; bh=NaP5go48DIg7ZP2vsh8v9L0+32c55LUSiW/3zQ6evCw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ieyai7nzf+TIUD0WLZO+8Vnd/wq2vo8jec9nOI62nZIVTiw1RdBPJMNAJMSYBxHoMZsilOeYqR4tNnGxl7zdfWUaGRn5+X9HvIslZ5jLMOHIplllFhVfh5Cs8PkVx3glLiBxGDda3KPuy9oPHfDufCH06Vq8NekuSMeuc6RFgj4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=gMd9NIgs; arc=none smtp.client-ip=74.125.231.205 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-oi2-f13.google.com with SMTP id 5614622812f47-4c6d6660191so427598b6e.2 for ; Tue, 22 Sep 2026 22:36:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1790141786; x=1790746586; darn=lists.linux.dev; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=TmixJAuwq8ENbvDysNd8oI5Iik3FUsXX4Zkq+YJZJ3g=; b=gMd9NIgsyj0W+lVd2cqqcZ3+Nsgf79AwpAIO0sXNp/m/aYJ/bBMqfzXefhVi55RrJb jmSq5Uo8dVxhR26Zj5dbwlrDE/hNmpiU82UXj7DVjOvYXTFKWLaeV7AI7k7r8SP5HPkE 1iMOMxx1RBlPG97chFuI5aBtYpzZm59O5/KbIuPmDnq4G/ksl07kg9Cu0mGrogQ+icVE K2l0xGK+kYc2LHqw2OChn3wlRnKVHoWrSErhpQ999kd/O5kWnS+vyPH6TkkWNN1HDAJT gYPJpyK8rz2CBCaPGtc/QjaE1OM74DKVIsM7i/OBWDOf8K1AIOikY9sGby1Dpi4RKphm rmFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1790141786; x=1790746586; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=TmixJAuwq8ENbvDysNd8oI5Iik3FUsXX4Zkq+YJZJ3g=; b=Xvyua3UZ1DmWo2tokhVl208eonawFC56uXlGvRv26R23zLIaKRnsd4d3vyH53rjNSx IJBqNOxewghnzGwAAYNVRCl4k55blhP/QoJSv1unYu+09x+w3hSabnsEPZP1OJxNsa+L cByJ18lIikJVaFXQzYlYQrQF3TrjkxFIXYaivGAOvyFTnlzglLSHKuV+jPR6PpcR8CZ/ pW8eIXsQJON/T6BKh6BhwRaxWDUtlKZ2YiYuaVmd8qz6jvFiFCbiAFiQ/5OBNRhGXZFh zNWpB/Zt8pD7WhG3UeEXqQuIpBfEnTKMuAgzQiByKJCMOP3Pw/dIREheyd/AY2dDbMuK eH3A== X-Forwarded-Encrypted: i=1; AKwUvBxNXN+mr2ebZaxzpCkYq4U6toHwY+pITvJ22KZbS9FqMqvy8zr6K7dDjdSo0Ax9E/BHOFI4DuE4pI7fog==@lists.linux.dev X-Gm-Message-State: AFuF++mNSARAtVMO43v0kPfTa9wA4wgA3IDJg41znnpi5QzDzmkldXgg Q+wc/8bxPTMIPrFf5CHc1M3g5thOvSIxi9lyPb9w1FMUgptX1vpraJog X-Gm-Gg: AYBFou150MTgHX3v9Uf33cjqPHOkU1/NwS72e9wRQi4td3XxGtvqJMFyHmbuMw7XQ6k 4YdxSC5JKwPd2bGBn3RXFTaxwgn5Ym1qnoMzvNArCvAQ/oGBEvdh26r/0sfg8fKJ+ULYj7W6Scc gx5Jy0A80w0CgaqGgONJ5Kc8F7uwtJa2s9Kr6Eh59i0h7BDjSjDy5R9OBKMc0mcHwzogO9pJEue wl6cy55ULDv2JO1wvo11SZWPwLVSlAORN9XPoFEjG3jWaQD/kOG2zSqpz3oCgWpOMVEdXAxxTRm raNbn7onIxTdE7F2Yk+pvFXtiZuJwouaqZFqppGo10FlMqySX8SGOxGGk7JW9AwNDzNEoypeJ1s rxtNsrGB0mfZozS/+pbvp+GronhoWHRZwu79MJwePtiamiIMuTj5tO+S7sTkl3h1Durg2P6g/z6 6wo96okwfeobRDKUIuSVtksUnMKYyU9WQWlm9uNnYcxqkKVdTgkyBoCbSldIdoAYX8widMUOIyQ s/g4K094PBhGHeciK+WMfXm0qFHzgPDBr90+yfbj8ys8Gir5hKK1Rczhq4sjFKk531I4sxzl0+g GWp7Mbi9DT4eKvgJrzb6MJ4NKQc+vyfQNuzXNiMcGNmvxVH5zMwxcsNyAMFjNHGq83avLbL++Uo 7D06ZsgCJgc6/939ABVY7JwwjcDsdHcdS X-Received: by 2002:a05:6808:1383:b0:4c4:a240:9c3a with SMTP id 5614622812f47-4d5b6eea244mr1774765b6e.4.1790141785549; Tue, 22 Sep 2026 22:36:25 -0700 (PDT) Received: from [127.0.1.1] (174-29-1-49.hlrn.qwest.net. [174.29.1.49]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4d5c4aed99bsm1436896b6e.12.2026.09.22.22.36.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 22:36:24 -0700 (PDT) From: James Hilliard Date: Tue, 22 Sep 2026 23:36:15 -0600 Subject: [PATCH v10 2/5] pwm: sun8i: Add H616 PWM support Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260922-h616-pwm-v8-v10-2-dccebbe1aabf@gmail.com> References: <20260922-h616-pwm-v8-v10-0-dccebbe1aabf@gmail.com> In-Reply-To: <20260922-h616-pwm-v8-v10-0-dccebbe1aabf@gmail.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Stephen Boyd , Brian Masney , Jerome Brunet , Richard Genoud , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard Cc: Philipp Zabel , Michael Turquette , Paul Kocialkowski , Thomas Petazzoni , John Stultz , Joao Schim , bigunclemax@gmail.com, linux-pwm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, James Hilliard X-Mailer: b4 0.15.2 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-1.16 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.234.253.10:from]; SUSPICIOUS_RECIPS(1.50)[]; DMARC_POLICY_SOFTFAIL(1.00)[gmail.com : SPF not aligned (relaxed), No valid DKIM,none]; MAILLIST(-0.15)[generic]; BAD_REP_POLICIES(0.10)[]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; RCVD_COUNT_FIVE(0.00)[6]; FROM_HAS_DN(0.00)[]; FORGED_SENDER_MAILLIST(0.00)[]; RCPT_COUNT_TWELVE(0.00)[26]; PRECEDENCE_BULK(0.00)[]; FREEMAIL_CC(0.00)[pengutronix.de,baylibre.com,sys-base.io,bootlin.com,google.com,schimsalabim.eu,gmail.com,vger.kernel.org,lists.infradead.org,lists.linux.dev]; TAGGED_RCPT(0.00)[clk,dt]; DBL_BLOCKED_OPENRESOLVER(0.00)[bootlin.com:email,sea.lore.kernel.org:rdns,sea.lore.kernel.org:helo]; FROM_NEQ_ENVFROM(0.00)[jameshilliard1@gmail.com,linux-sunxi@lists.linux.dev]; TAGGED_FROM(0.00)[bounces-26162-noreply=patchwork.local]; FREEMAIL_FROM(0.00)[gmail.com]; R_SPF_ALLOW(0.00)[+ip4:172.234.253.10]; TO_DN_SOME(0.00)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.234.253.10:from]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[100.90.174.1:received,74.125.231.205:received,174.29.1.49:received]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; FREEMAIL_TO(0.00)[kernel.org,redhat.com,baylibre.com,bootlin.com,gmail.com,sholland.org]; MIME_TRACE(0.00)[0:+]; MID_RHS_MATCH_FROM(0.00)[]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; RCVD_TLS_LAST(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 8194F1C0750 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= From: Richard Genoud Add waveform support for the six-channel Allwinner H616 PWM controller. Each pair of outputs shares a source mux, gate and power-of-two divider; each channel has its own prescaler and period/duty registers. Model the shared pair clocks in CCF and program the channel-local dividers directly. Protect the pair rate while a PWM is active. Also check the hardware enable bits before retuning or gating a pair, since firmware may have left an output running without a Linux consumer. Preserve such outputs until a consumer explicitly changes them; do not implement an unused-PWM sweep. Round period, duty and offset in the order required by the waveform API, including the hardware bypass path and the 65536-tick period boundary. Wait for pending period updates and quiesce the channel when changing its clock, prescaler, polarity or bypass mode. Live period updates additionally require PCLK to be faster than the PWM clock, as specified by the manual. Encode the channel register values during waveform conversion. Keep rate protection, safe quiescing and clock rollback in one preparation helper, leaving the write callback to apply the prepared values. Select candidates using one ordered comparison while retaining the bounded divider search. Pulse and coupled dead-zone modes cannot be represented by this API. Reject active unsupported modes, but clear dormant dead-zone configuration before programming an ordinary waveform. Allocate the fixed six-channel topology with the pwm_chip. Register the per-device clocks with managed helpers after deasserting reset. Acquire separate pair-clock consumer handles only while PWMs are requested, so internal clock references cannot prevent module removal. Use CCF's provider-owned handles for notifiers and rate readback, including readback of channels which have not been requested. Signed-off-by: Richard Genoud Co-developed-by: James Hilliard Signed-off-by: James Hilliard --- drivers/pwm/Kconfig | 11 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sun8i.c | 1080 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1092 insertions(+) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 729776086879..d87d166e7836 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -748,6 +748,17 @@ config PWM_SUN4I To compile this driver as a module, choose M here: the module will be called pwm-sun4i. +config PWM_SUN8I + tristate "Allwinner sun8i/sun50i PWM support" + depends on ARCH_SUNXI || COMPILE_TEST + depends on HAS_IOMEM && COMMON_CLK + help + PWM framework driver for Allwinner controllers whose channels share + paired source clocks. + + To compile this driver as a module, choose M here: the module + will be called pwm-sun8i. + config PWM_SUNPLUS tristate "Sunplus PWM support" depends on ARCH_SUNPLUS || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 5630a521a7cf..9c922b1fd0b4 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -68,6 +68,7 @@ obj-$(CONFIG_PWM_STM32) += pwm-stm32.o obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o +obj-$(CONFIG_PWM_SUN8I) += pwm-sun8i.o obj-$(CONFIG_PWM_SUNPLUS) += pwm-sunplus.o obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o obj-$(CONFIG_PWM_TH1520) += pwm_th1520.o diff --git a/drivers/pwm/pwm-sun8i.c b/drivers/pwm/pwm-sun8i.c new file mode 100644 index 000000000000..7e6c39815c18 --- /dev/null +++ b/drivers/pwm/pwm-sun8i.c @@ -0,0 +1,1080 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Driver for Allwinner sun8i Pulse Width Modulation Controller + * + * (C) Copyright 2025 Richard Genoud, Bootlin + * (C) Copyright 2026 James Hilliard + * + * Based on drivers/pwm/pwm-sun4i.c with Copyright: + * + * Copyright (C) 2014 Alexandre Belloni + * + * Channels are paired (0/1, 2/3, 4/5). Each pair shares a clock source and + * first prescaler (div_m), while each channel has its own second prescaler + * (div_k) and bypass path. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SUN8I_PWM_NPWM 6 +#define SUN8I_PWM_NPAIRS (SUN8I_PWM_NPWM / 2) + +/* PWMCC Pairs Clock Configuration Registers */ +#define SUN8I_PWM_PCCR(pair) (0x20 + ((pair) * 0x4)) +#define SUN8I_PWM_PCCR_SRC_SHIFT 7 +#define SUN8I_PWM_PCCR_SRC_MASK GENMASK(1, 0) +#define SUN8I_PWM_PCCR_GATE_BIT 4 +#define SUN8I_PWM_PCCR_GATE BIT(SUN8I_PWM_PCCR_GATE_BIT) +#define SUN8I_PWM_PCCR_BYPASS_BIT(chan) ((chan) % 2 + 5) +#define SUN8I_PWM_PCCR_DIV_M_SHIFT 0 +#define SUN8I_PWM_PCCR_DIV_M_WIDTH 4 + +/* PWM Enable Register */ +#define SUN8I_PWM_PER 0x40 +#define SUN8I_PWM_ENABLE(chan) BIT(chan) + +/* PWM Control Register */ +#define SUN8I_PWM_PCR(chan) (0x60 + (chan) * 0x20) +#define SUN8I_PWM_PCR_PRESCAL_K_MASK GENMASK(7, 0) +#define SUN8I_PWM_PCR_ACTIVE_STATE BIT(8) +#define SUN8I_PWM_PCR_MODE BIT(9) +#define SUN8I_PWM_PCR_PULSE_START BIT(10) +#define SUN8I_PWM_PCR_PERIOD_READY BIT(11) /* 0: ready, 1: busy */ +#define SUN8I_PWM_PCR_WAVEFORM_MASK (SUN8I_PWM_PCR_PRESCAL_K_MASK | \ + SUN8I_PWM_PCR_ACTIVE_STATE) + +/* PWM Period Register */ +#define SUN8I_PWM_PPR(chan) (0x64 + (chan) * 0x20) +#define SUN8I_PWM_PPR_PERIOD_MASK GENMASK(31, 16) +#define SUN8I_PWM_PPR_DUTY_MASK GENMASK(15, 0) +#define SUN8I_PWM_PPR_PERIOD_VALUE(reg) (FIELD_GET(SUN8I_PWM_PPR_PERIOD_MASK, reg) + 1) +#define SUN8I_PWM_PPR_DUTY_VALUE(reg) FIELD_GET(SUN8I_PWM_PPR_DUTY_MASK, reg) +#define SUN8I_PWM_PPR_PERIOD(prd) FIELD_PREP(SUN8I_PWM_PPR_PERIOD_MASK, (prd) - 1) +#define SUN8I_PWM_PPR_DUTY(dty) FIELD_PREP(SUN8I_PWM_PPR_DUTY_MASK, dty) +#define SUN8I_PWM_PPR_PERIOD_MAX (FIELD_MAX(SUN8I_PWM_PPR_PERIOD_MASK) + 1) + +/* PWM pair dead-zone control registers. */ +#define SUN8I_PWM_PDZCR(pair) (0x30 + ((pair) * 0x4)) +#define SUN8I_PWM_PDZCR_ENABLE BIT(0) + +#define SUN8I_PWM_PERIOD_READY_MARGIN_US 50 +#define SUN8I_PWM_PERIOD_READY_MIN_POLL_US 10 +#define SUN8I_PWM_PERIOD_READY_MAX_POLL_US 10000 +#define SUN8I_PWM_PERIOD_READY_POLL_COUNT 1024 + +#define SUN8I_PWM_PAIR_IDX(chan) ((chan) >> 1) + +/* + * Block diagram of the PWM clock controller: + * + * _____ ______ ________ + * OSC24M --->| | | | | | + * APB1 ----->| Mux |--->| Gate |--->| /div_m |-----> SUN8I_PWM_clock_src_xy + * |_____| |______| |________| + * ________ + * | | + * +->| /div_k |---> SUN8I_PWM_clock_x + * | |________| + * | ______ + * | | | + * +-->| Gate |----> SUN8I_PWM_bypass_clock_x + * | |______| + * SUN8I_PWM_clock_src_xy ---+ ________ + * | | | + * +->| /div_k |---> SUN8I_PWM_clock_y + * | |________| + * | ______ + * | | | + * +-->| Gate |----> SUN8I_PWM_bypass_clock_y + * |______| + * + * NB: when the bypass is set, all the PWM logic is bypassed. + * So, the duty cycle and polarity can't be modified (we just have a clock). + * The bypass in PWM mode is used to achieve a 1/2 relative duty cycle with the + * fastest clock. + * + */ + +/* /div_m is a power-of-two divider limited to /256. */ +static const struct clk_div_table sun8i_pwm_div_m_table[] = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 8 }, + { .val = 4, .div = 16 }, + { .val = 5, .div = 32 }, + { .val = 6, .div = 64 }, + { .val = 7, .div = 128 }, + { .val = 8, .div = 256 }, + { /* sentinel */ } +}; + +struct sun8i_pwm_chip; + +struct sun8i_pwm_pair { + struct clk_mux mux; + struct clk_hw gate_hw; + struct clk_divider divider; + struct clk_hw *hw; + struct notifier_block rate_nb; + struct sun8i_pwm_chip *chip; + unsigned int index; +}; + +struct sun8i_pwm_channel { + /* Separate CCF consumer, held only from PWM request to free. */ + struct clk *pair_clk; + u64 pending_period_ns; + bool rate_exclusive; +}; + +struct sun8i_pwm_chip { + struct sun8i_pwm_pair pairs[SUN8I_PWM_NPAIRS]; + struct sun8i_pwm_channel channels[SUN8I_PWM_NPWM]; + struct clk *bus_clk; + void __iomem *base; + /* Protects shared registers and rate_exclusive. */ + spinlock_t lock; +}; + +struct sun8i_pwm_waveform { + u32 pcr; + u32 ppr; + u32 pair_rate; + bool enabled; + bool bypass_en; +}; + +static inline struct sun8i_pwm_chip *sun8i_pwm_from_chip(const struct pwm_chip *chip) +{ + return pwmchip_get_drvdata(chip); +} + +static unsigned long sun8i_pwm_get_pair_rate(struct sun8i_pwm_chip *sun8i_chip, + unsigned int idx) +{ + struct sun8i_pwm_pair *pair = &sun8i_chip->pairs[SUN8I_PWM_PAIR_IDX(idx)]; + + /* Readback also runs on channels without a PWM request. */ + return clk_get_rate(pair->hw->clk); +} + +static inline u32 sun8i_pwm_readl(struct sun8i_pwm_chip *sun8i_chip, + unsigned long offset) +{ + return readl(sun8i_chip->base + offset); +} + +static inline void sun8i_pwm_writel(struct sun8i_pwm_chip *sun8i_chip, + u32 val, unsigned long offset) +{ + writel(val, sun8i_chip->base + offset); +} + +static void sun8i_pwm_set_bypass_locked(struct sun8i_pwm_chip *sun8i_chip, + unsigned int idx, bool enable) +{ + unsigned long reg_offset; + u32 val; + + lockdep_assert_held(&sun8i_chip->lock); + + reg_offset = SUN8I_PWM_PCCR(SUN8I_PWM_PAIR_IDX(idx)); + val = sun8i_pwm_readl(sun8i_chip, reg_offset); + if (enable) + val |= BIT(SUN8I_PWM_PCCR_BYPASS_BIT(idx)); + else + val &= ~BIT(SUN8I_PWM_PCCR_BYPASS_BIT(idx)); + + sun8i_pwm_writel(sun8i_chip, val, reg_offset); +} + +static void sun8i_pwm_set_enabled_locked(struct sun8i_pwm_chip *sun8i_chip, + unsigned int idx, bool enable) +{ + u32 val; + + lockdep_assert_held(&sun8i_chip->lock); + + val = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PER); + if (enable) + val |= SUN8I_PWM_ENABLE(idx); + else + val &= ~SUN8I_PWM_ENABLE(idx); + sun8i_pwm_writel(sun8i_chip, val, SUN8I_PWM_PER); +} + +static bool +sun8i_pwm_channel_is_enabled_locked(struct sun8i_pwm_chip *sun8i_chip, + unsigned int idx) +{ + unsigned int pair = SUN8I_PWM_PAIR_IDX(idx); + u32 pccr, per; + + lockdep_assert_held(&sun8i_chip->lock); + + pccr = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PCCR(pair)); + per = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PER); + + return (pccr & SUN8I_PWM_PCCR_GATE) && + (per & SUN8I_PWM_ENABLE(idx)); +} + +static u32 sun8i_pwm_pair_enable_mask(unsigned int pair) +{ + return GENMASK(pair * 2 + 1, pair * 2); +} + +static inline struct sun8i_pwm_pair * +sun8i_pwm_pair_from_gate_hw(struct clk_hw *hw) +{ + return container_of(hw, struct sun8i_pwm_pair, gate_hw); +} + +static int sun8i_pwm_pair_gate_enable(struct clk_hw *hw) +{ + struct sun8i_pwm_pair *pair = sun8i_pwm_pair_from_gate_hw(hw); + struct sun8i_pwm_chip *sun8i_chip = pair->chip; + u32 pccr; + + guard(spinlock_irqsave)(&sun8i_chip->lock); + pccr = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PCCR(pair->index)); + pccr |= SUN8I_PWM_PCCR_GATE; + sun8i_pwm_writel(sun8i_chip, pccr, SUN8I_PWM_PCCR(pair->index)); + + return 0; +} + +static void sun8i_pwm_pair_gate_disable(struct clk_hw *hw) +{ + struct sun8i_pwm_pair *pair = sun8i_pwm_pair_from_gate_hw(hw); + struct sun8i_pwm_chip *sun8i_chip = pair->chip; + unsigned long reg = SUN8I_PWM_PCCR(pair->index); + u32 pccr, per; + + /* CCF counts do not include outputs awaiting firmware-state handoff. */ + guard(spinlock_irqsave)(&sun8i_chip->lock); + per = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PER); + if (!(per & sun8i_pwm_pair_enable_mask(pair->index))) { + pccr = sun8i_pwm_readl(sun8i_chip, reg); + pccr &= ~SUN8I_PWM_PCCR_GATE; + sun8i_pwm_writel(sun8i_chip, pccr, reg); + } +} + +static int sun8i_pwm_pair_gate_is_enabled(struct clk_hw *hw) +{ + struct sun8i_pwm_pair *pair = sun8i_pwm_pair_from_gate_hw(hw); + struct sun8i_pwm_chip *sun8i_chip = pair->chip; + unsigned long reg = SUN8I_PWM_PCCR(pair->index); + + guard(spinlock_irqsave)(&sun8i_chip->lock); + + return !!(sun8i_pwm_readl(sun8i_chip, reg) & SUN8I_PWM_PCCR_GATE); +} + +static const struct clk_ops sun8i_pwm_pair_gate_ops = { + .enable = sun8i_pwm_pair_gate_enable, + .disable = sun8i_pwm_pair_gate_disable, + .is_enabled = sun8i_pwm_pair_gate_is_enabled, +}; + +static int sun8i_pwm_pair_rate_notifier(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct sun8i_pwm_pair *pair = + container_of(nb, struct sun8i_pwm_pair, rate_nb); + struct sun8i_pwm_chip *sun8i_chip = pair->chip; + bool active; + + if (event != PRE_RATE_CHANGE) + return NOTIFY_DONE; + + guard(spinlock_irqsave)(&sun8i_chip->lock); + active = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PER) & + sun8i_pwm_pair_enable_mask(pair->index); + + return active ? NOTIFY_BAD : NOTIFY_OK; +} + +static void sun8i_pwm_put_rate(struct sun8i_pwm_chip *sun8i_chip, + unsigned int idx) +{ + struct sun8i_pwm_channel *chan = &sun8i_chip->channels[idx]; + bool exclusive; + + scoped_guard(spinlock_irqsave, &sun8i_chip->lock) { + exclusive = chan->rate_exclusive; + chan->rate_exclusive = false; + } + /* CCF takes the prepare mutex and may call back into this driver. */ + if (exclusive) + clk_rate_exclusive_put(chan->pair_clk); +} + +static int sun8i_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct sun8i_pwm_chip *sun8i_chip = sun8i_pwm_from_chip(chip); + struct sun8i_pwm_channel *chan = &sun8i_chip->channels[pwm->hwpwm]; + unsigned int idx = pwm->hwpwm; + struct clk_hw *parent = sun8i_chip->pairs[SUN8I_PWM_PAIR_IDX(idx)].hw; + bool was_enabled; + int ret; + + scoped_guard(spinlock_irqsave, &sun8i_chip->lock) { + was_enabled = + sun8i_pwm_channel_is_enabled_locked(sun8i_chip, idx); + } + + chan->pair_clk = clk_hw_get_clk(parent, NULL); + if (IS_ERR(chan->pair_clk)) { + ret = PTR_ERR(chan->pair_clk); + goto err_clear_clock; + } + + if (was_enabled) { + ret = clk_rate_exclusive_get(chan->pair_clk); + if (ret) + goto err_put_clock; + scoped_guard(spinlock_irqsave, &sun8i_chip->lock) + chan->rate_exclusive = true; + } + + ret = clk_prepare_enable(chan->pair_clk); + if (ret) { + sun8i_pwm_put_rate(sun8i_chip, idx); + goto err_put_clock; + } + + return 0; + +err_put_clock: + clk_put(chan->pair_clk); +err_clear_clock: + chan->pair_clk = NULL; + + return ret; +} + +static void sun8i_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct sun8i_pwm_chip *sun8i_chip = sun8i_pwm_from_chip(chip); + struct sun8i_pwm_channel *chan = &sun8i_chip->channels[pwm->hwpwm]; + + scoped_guard(spinlock_irqsave, &sun8i_chip->lock) { + sun8i_pwm_set_enabled_locked(sun8i_chip, pwm->hwpwm, false); + sun8i_pwm_set_bypass_locked(sun8i_chip, pwm->hwpwm, false); + } + + sun8i_pwm_put_rate(sun8i_chip, pwm->hwpwm); + clk_disable_unprepare(chan->pair_clk); + clk_put(chan->pair_clk); + chan->pair_clk = NULL; +} + +static int sun8i_pwm_read_waveform(struct pwm_chip *chip, + struct pwm_device *pwm, + void *_wfhw) +{ + struct sun8i_pwm_waveform *wfhw = _wfhw; + struct sun8i_pwm_chip *sun8i_chip = sun8i_pwm_from_chip(chip); + unsigned int pair = SUN8I_PWM_PAIR_IDX(pwm->hwpwm); + unsigned long pair_rate; + u32 pccr, pcr, pdzcr, per, ppr; + + pair_rate = sun8i_pwm_get_pair_rate(sun8i_chip, pwm->hwpwm); + if (pair_rate > U32_MAX) + return -ERANGE; + + scoped_guard(spinlock_irqsave, &sun8i_chip->lock) { + pccr = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PCCR(pair)); + per = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PER); + pcr = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PCR(pwm->hwpwm)); + ppr = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PPR(pwm->hwpwm)); + pdzcr = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PDZCR(pair)); + } + + *wfhw = (struct sun8i_pwm_waveform) { + .enabled = !!(pccr & SUN8I_PWM_PCCR_GATE) && + !!(per & SUN8I_PWM_ENABLE(pwm->hwpwm)), + .bypass_en = !!(pccr & + BIT(SUN8I_PWM_PCCR_BYPASS_BIT(pwm->hwpwm))), + .pcr = pcr & SUN8I_PWM_PCR_WAVEFORM_MASK, + .ppr = ppr, + .pair_rate = pair_rate, + }; + + /* The waveform API cannot describe coupled dead-zone or pulse mode. */ + if (wfhw->enabled && !wfhw->bypass_en && + ((pdzcr & SUN8I_PWM_PDZCR_ENABLE) || (pcr & SUN8I_PWM_PCR_MODE))) + return -EOPNOTSUPP; + + return 0; +} + +static u64 sun8i_pwm_ticks_to_ns(u32 ticks, u16 div_k, u32 pair_rate) +{ + return DIV_ROUND_UP_ULL(NSEC_PER_SEC * (u64)ticks * div_k, + pair_rate); +} + +static u64 sun8i_pwm_period_ns(const struct sun8i_pwm_waveform *wfhw) +{ + if (wfhw->bypass_en) + return DIV_ROUND_UP_ULL(NSEC_PER_SEC, wfhw->pair_rate); + + return sun8i_pwm_ticks_to_ns(SUN8I_PWM_PPR_PERIOD_VALUE(wfhw->ppr), + FIELD_GET(SUN8I_PWM_PCR_PRESCAL_K_MASK, wfhw->pcr) + 1, + wfhw->pair_rate); +} + +static void +__sun8i_pwm_round_waveform_fromhw(const struct sun8i_pwm_waveform *wfhw, + struct pwm_waveform *wf) +{ + u32 pair_rate = wfhw->pair_rate; + u32 period_ticks = SUN8I_PWM_PPR_PERIOD_VALUE(wfhw->ppr); + u32 duty_ticks = SUN8I_PWM_PPR_DUTY_VALUE(wfhw->ppr); + u16 div_k = FIELD_GET(SUN8I_PWM_PCR_PRESCAL_K_MASK, wfhw->pcr) + 1; + + wf->duty_offset_ns = 0; + + if (!wfhw->enabled || !pair_rate) { + wf->period_length_ns = 0; + wf->duty_length_ns = 0; + return; + } + + wf->period_length_ns = sun8i_pwm_period_ns(wfhw); + if (wfhw->bypass_en) { + wf->duty_length_ns = + DIV_ROUND_UP_ULL(NSEC_PER_SEC, + 2ULL * pair_rate); + return; + } + + duty_ticks = min(duty_ticks, period_ticks); + if (!(wfhw->pcr & SUN8I_PWM_PCR_ACTIVE_STATE)) { + /* Constant outputs have no edge and therefore no offset. */ + if (duty_ticks && duty_ticks < period_ticks) + wf->duty_offset_ns = + sun8i_pwm_ticks_to_ns(duty_ticks, div_k, pair_rate); + duty_ticks = period_ticks - duty_ticks; + } + wf->duty_length_ns = sun8i_pwm_ticks_to_ns(duty_ticks, div_k, pair_rate); +} + +static int sun8i_pwm_round_waveform_fromhw(struct pwm_chip *chip, + struct pwm_device *pwm, + const void *_wfhw, + struct pwm_waveform *wf) +{ + const struct sun8i_pwm_waveform *wfhw = _wfhw; + + __sun8i_pwm_round_waveform_fromhw(wfhw, wf); + + dev_dbg(pwmchip_parent(chip), + "pwm#%u: pair-rate=%u, pcr=%#x, ppr=%#x, bypass=%u -> %llu/%llu [+%llu]\n", + pwm->hwpwm, wfhw->pair_rate, wfhw->pcr, wfhw->ppr, + wfhw->bypass_en, + wf->duty_length_ns, wf->period_length_ns, + wf->duty_offset_ns); + + return 0; +} + +static bool +sun8i_pwm_pair_rate_constrained(struct sun8i_pwm_chip *sun8i_chip, + unsigned int idx) +{ + unsigned int sibling = idx ^ 1; + + guard(spinlock_irqsave)(&sun8i_chip->lock); + return sun8i_chip->channels[sibling].rate_exclusive || + sun8i_pwm_channel_is_enabled_locked(sun8i_chip, sibling); +} + +static int sun8i_pwm_clear_idle_deadzone(struct sun8i_pwm_chip *sun8i_chip, + unsigned int idx) +{ + unsigned int pair = SUN8I_PWM_PAIR_IDX(idx); + u32 pdzcr, per; + + guard(spinlock_irqsave)(&sun8i_chip->lock); + pdzcr = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PDZCR(pair)); + if (!(pdzcr & SUN8I_PWM_PDZCR_ENABLE)) + return 0; + + per = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PER); + if (per & sun8i_pwm_pair_enable_mask(pair)) + return -EOPNOTSUPP; + + pdzcr &= ~SUN8I_PWM_PDZCR_ENABLE; + sun8i_pwm_writel(sun8i_chip, pdzcr, SUN8I_PWM_PDZCR(pair)); + + return 0; +} + +static u64 sun8i_pwm_max_period_ns(struct sun8i_pwm_chip *sun8i_chip, + unsigned int idx) +{ + unsigned long pair_rate; + u32 pcr; + u16 div_k; + + pair_rate = sun8i_pwm_get_pair_rate(sun8i_chip, idx); + if (!pair_rate || pair_rate > U32_MAX) + return 0; + + scoped_guard(spinlock_irqsave, &sun8i_chip->lock) { + pcr = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PCR(idx)); + } + div_k = FIELD_GET(SUN8I_PWM_PCR_PRESCAL_K_MASK, pcr) + 1; + + return sun8i_pwm_ticks_to_ns(SUN8I_PWM_PPR_PERIOD_MAX, div_k, + pair_rate); +} + +static int sun8i_pwm_wait_period_ready(struct pwm_chip *chip, unsigned int idx) +{ + struct sun8i_pwm_chip *sun8i_chip = sun8i_pwm_from_chip(chip); + struct sun8i_pwm_channel *chan = &sun8i_chip->channels[idx]; + unsigned long poll_us; + u64 period_ns, timeout_us; + u32 val; + int ret; + + /* PPR contains the pending value, not necessarily the active period. */ + period_ns = chan->pending_period_ns; + if (!period_ns) + period_ns = sun8i_pwm_max_period_ns(sun8i_chip, idx); + timeout_us = DIV_ROUND_UP_ULL(period_ns, NSEC_PER_USEC) + + SUN8I_PWM_PERIOD_READY_MARGIN_US; + poll_us = clamp_t(u64, + DIV_ROUND_UP_ULL(timeout_us, + SUN8I_PWM_PERIOD_READY_POLL_COUNT), + SUN8I_PWM_PERIOD_READY_MIN_POLL_US, + SUN8I_PWM_PERIOD_READY_MAX_POLL_US); + + ret = readl_poll_timeout(sun8i_chip->base + SUN8I_PWM_PCR(idx), val, + !(val & SUN8I_PWM_PCR_PERIOD_READY), poll_us, + timeout_us); + if (!ret) + chan->pending_period_ns = 0; + else + dev_err_ratelimited(pwmchip_parent(chip), + "pwm#%u: update timeout after %llu us\n", + idx, timeout_us); + + return ret; +} + +/* + * Protect the rate and quiesce the output if a live update is unsafe. On + * failure restore the old clock before restarting an output we stopped. + * CCF operations must stay outside the register lock. + */ +static int sun8i_pwm_prepare_update(struct pwm_chip *chip, unsigned int idx, + const struct sun8i_pwm_waveform *wfhw, + struct sun8i_pwm_waveform *old) +{ + struct sun8i_pwm_chip *sun8i_chip = sun8i_pwm_from_chip(chip); + struct sun8i_pwm_channel *chan = &sun8i_chip->channels[idx]; + unsigned long rate, bus_rate; + bool had_exclusive, stop; + u32 pccr; + int ret, restore_ret; + + scoped_guard(spinlock_irqsave, &sun8i_chip->lock) + had_exclusive = chan->rate_exclusive; + + if (!had_exclusive) { + ret = clk_rate_exclusive_get(chan->pair_clk); + if (ret) + return ret; + scoped_guard(spinlock_irqsave, &sun8i_chip->lock) + chan->rate_exclusive = true; + } + + /* Sample the old rate only after excluding other rate changes. */ + rate = sun8i_pwm_get_pair_rate(sun8i_chip, idx); + if (!rate || rate > U32_MAX) { + ret = -ERANGE; + goto put_rate; + } + old->pair_rate = rate; + scoped_guard(spinlock_irqsave, &sun8i_chip->lock) { + old->enabled = sun8i_pwm_channel_is_enabled_locked(sun8i_chip, idx); + pccr = sun8i_pwm_readl(sun8i_chip, + SUN8I_PWM_PCCR(SUN8I_PWM_PAIR_IDX(idx))); + old->bypass_en = !!(pccr & BIT(SUN8I_PWM_PCCR_BYPASS_BIT(idx))); + old->pcr = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PCR(idx)); + old->ppr = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PPR(idx)); + } + + if (rate != wfhw->pair_rate && + sun8i_pwm_pair_rate_constrained(sun8i_chip, idx)) { + ret = -EBUSY; + goto put_rate; + } + + /* Live PPR updates require unchanged configuration and a faster PCLK. */ + bus_rate = clk_get_rate(sun8i_chip->bus_clk); + stop = old->enabled && + (old->bypass_en != wfhw->bypass_en || rate != wfhw->pair_rate || + (!wfhw->bypass_en && + (((old->pcr ^ wfhw->pcr) & + (SUN8I_PWM_PCR_WAVEFORM_MASK | SUN8I_PWM_PCR_MODE)) || + bus_rate <= DIV_ROUND_UP_ULL(wfhw->pair_rate, + FIELD_GET(SUN8I_PWM_PCR_PRESCAL_K_MASK, wfhw->pcr) + 1)))); + if (stop) { + scoped_guard(spinlock_irqsave, &sun8i_chip->lock) + sun8i_pwm_set_enabled_locked(sun8i_chip, idx, false); + } + + if (rate == wfhw->pair_rate) + return 0; + + ret = clk_set_rate(chan->pair_clk, wfhw->pair_rate); + if (!ret && sun8i_pwm_get_pair_rate(sun8i_chip, idx) == wfhw->pair_rate) + return 0; + if (!ret) + ret = -EINVAL; + + if (sun8i_pwm_get_pair_rate(sun8i_chip, idx) != rate) { + restore_ret = clk_set_rate(chan->pair_clk, rate); + if (restore_ret || sun8i_pwm_get_pair_rate(sun8i_chip, idx) != rate) { + dev_err(pwmchip_parent(chip), + "pwm#%u: failed to restore pair clock rate %lu\n", + idx, rate); + goto put_rate; + } + } + if (stop) { + scoped_guard(spinlock_irqsave, &sun8i_chip->lock) + sun8i_pwm_set_enabled_locked(sun8i_chip, idx, true); + } +put_rate: + if (!had_exclusive) + sun8i_pwm_put_rate(sun8i_chip, idx); + + return ret; +} + +static int sun8i_pwm_write_waveform(struct pwm_chip *chip, + struct pwm_device *pwm, const void *_wfhw) +{ + const struct sun8i_pwm_waveform *wfhw = _wfhw; + struct sun8i_pwm_chip *sun8i_chip = sun8i_pwm_from_chip(chip); + struct sun8i_pwm_channel *chan = &sun8i_chip->channels[pwm->hwpwm]; + struct sun8i_pwm_waveform old; + u64 old_ns = 0, new_ns; + u32 pcr; + int ret; + + if (!wfhw->enabled) { + scoped_guard(spinlock_irqsave, &sun8i_chip->lock) { + sun8i_pwm_set_enabled_locked(sun8i_chip, pwm->hwpwm, false); + sun8i_pwm_set_bypass_locked(sun8i_chip, pwm->hwpwm, false); + } + sun8i_pwm_put_rate(sun8i_chip, pwm->hwpwm); + return 0; + } + + if (!wfhw->bypass_en) { + ret = sun8i_pwm_clear_idle_deadzone(sun8i_chip, pwm->hwpwm); + if (ret) + return ret; + ret = sun8i_pwm_wait_period_ready(chip, pwm->hwpwm); + if (ret) + return ret; + } + + ret = sun8i_pwm_prepare_update(chip, pwm->hwpwm, wfhw, &old); + if (ret) + return ret; + + if (!wfhw->bypass_en) { + /* Apply only waveform fields; never replay status or W1S bits. */ + pcr = old.pcr & ~(SUN8I_PWM_PCR_WAVEFORM_MASK | + SUN8I_PWM_PCR_MODE | SUN8I_PWM_PCR_PULSE_START | + SUN8I_PWM_PCR_PERIOD_READY); + sun8i_pwm_writel(sun8i_chip, pcr | wfhw->pcr, + SUN8I_PWM_PCR(pwm->hwpwm)); + + if (old.enabled && !old.bypass_en) + old_ns = sun8i_pwm_period_ns(&old); + new_ns = sun8i_pwm_period_ns(wfhw); + chan->pending_period_ns = max(old_ns, new_ns); + sun8i_pwm_writel(sun8i_chip, wfhw->ppr, SUN8I_PWM_PPR(pwm->hwpwm)); + } + + scoped_guard(spinlock_irqsave, &sun8i_chip->lock) { + sun8i_pwm_set_bypass_locked(sun8i_chip, pwm->hwpwm, wfhw->bypass_en); + sun8i_pwm_set_enabled_locked(sun8i_chip, pwm->hwpwm, true); + } + + return 0; +} + +struct sun8i_pwm_rounding { + const struct pwm_waveform *requested; + struct sun8i_pwm_waveform best; + struct pwm_waveform best_wf; + u32 current_pair_rate; + bool have_best; +}; + +static void +sun8i_pwm_choose_waveform(struct sun8i_pwm_rounding *rounding, + const struct sun8i_pwm_waveform *candidate) +{ + const struct pwm_waveform *requested = rounding->requested; + const struct pwm_waveform *best = &rounding->best_wf; + struct pwm_waveform wf; + bool better; + + __sun8i_pwm_round_waveform_fromhw(candidate, &wf); + /* A zero-duty, zero-offset cycle-mode candidate always exists. */ + if (wf.duty_length_ns > requested->duty_length_ns || + wf.duty_offset_ns > requested->duty_offset_ns) + return; + + if (!rounding->have_best) { + better = true; + } else if (wf.period_length_ns != best->period_length_ns) { + /* Prefer the longest period below the request, else the shortest. */ + if (wf.period_length_ns > requested->period_length_ns) + better = wf.period_length_ns < best->period_length_ns; + else + better = best->period_length_ns > requested->period_length_ns || + wf.period_length_ns > best->period_length_ns; + } else if (wf.duty_length_ns != best->duty_length_ns) { + better = wf.duty_length_ns > best->duty_length_ns; + } else if (wf.duty_offset_ns != best->duty_offset_ns) { + better = wf.duty_offset_ns > best->duty_offset_ns; + } else { + /* Prefer the current pair rate when waveforms are equivalent. */ + better = candidate->pair_rate == rounding->current_pair_rate && + rounding->best.pair_rate != rounding->current_pair_rate; + } + if (!better) + return; + + rounding->best = *candidate; + rounding->best_wf = wf; + rounding->have_best = true; +} + +static struct sun8i_pwm_waveform +sun8i_pwm_round_cycle(const struct pwm_waveform *requested, u32 pair_rate, + u16 div_k) +{ + struct sun8i_pwm_waveform candidate = { + .enabled = true, + .pair_rate = pair_rate, + .pcr = FIELD_PREP(SUN8I_PWM_PCR_PRESCAL_K_MASK, div_k - 1), + }; + u64 denominator = NSEC_PER_SEC * (u64)div_k; + u64 duty_ticks, period_ticks; + u32 inactive_ticks; + + /* Floor division rounds down, except for the minimum one-tick period. */ + period_ticks = mul_u64_u64_div_u64(requested->period_length_ns, + pair_rate, denominator); + period_ticks = clamp_t(u64, period_ticks, 1, SUN8I_PWM_PPR_PERIOD_MAX); + duty_ticks = mul_u64_u64_div_u64(requested->duty_length_ns, + pair_rate, denominator); + duty_ticks = min(duty_ticks, period_ticks); + + /* + * Zero active ticks encode either constant level. For a toggling + * waveform, active-low mode places the rising edge after the inactive + * part, which is the only non-zero offset supported by the hardware. + */ + if (!duty_ticks) { + candidate.pcr |= SUN8I_PWM_PCR_ACTIVE_STATE; + } else if (duty_ticks == period_ticks) { + duty_ticks = 0; + } else { + inactive_ticks = period_ticks - duty_ticks; + if (sun8i_pwm_ticks_to_ns(inactive_ticks, div_k, pair_rate) <= + requested->duty_offset_ns) + duty_ticks = inactive_ticks; + else + candidate.pcr |= SUN8I_PWM_PCR_ACTIVE_STATE; + } + + candidate.ppr = SUN8I_PWM_PPR_PERIOD(period_ticks) | + SUN8I_PWM_PPR_DUTY(duty_ticks); + + return candidate; +} + +static void +sun8i_pwm_consider_pair_rate(struct sun8i_pwm_rounding *rounding, u32 pair_rate) +{ + struct sun8i_pwm_waveform candidate; + + for (unsigned int div_k = 1; div_k <= 256; div_k++) { + candidate = sun8i_pwm_round_cycle(rounding->requested, pair_rate, div_k); + sun8i_pwm_choose_waveform(rounding, &candidate); + } + + candidate = (struct sun8i_pwm_waveform) { + .pair_rate = pair_rate, + .enabled = true, + .bypass_en = true, + }; + sun8i_pwm_choose_waveform(rounding, &candidate); +} + +static int sun8i_pwm_round_waveform_tohw(struct pwm_chip *chip, + struct pwm_device *pwm, + const struct pwm_waveform *wf, + void *_wfhw) +{ + struct sun8i_pwm_chip *sun8i_chip = sun8i_pwm_from_chip(chip); + struct sun8i_pwm_pair *pair = + &sun8i_chip->pairs[SUN8I_PWM_PAIR_IDX(pwm->hwpwm)]; + struct sun8i_pwm_waveform *wfhw = _wfhw; + struct sun8i_pwm_rounding rounding = { + .requested = wf, + }; + unsigned long current_rate; + + if (!wf->period_length_ns) { + *wfhw = (struct sun8i_pwm_waveform) { + .enabled = false, + }; + return 0; + } + + current_rate = sun8i_pwm_get_pair_rate(sun8i_chip, pwm->hwpwm); + if (!current_rate || current_rate > U32_MAX) + return -ERANGE; + rounding.current_pair_rate = current_rate; + + if (sun8i_pwm_pair_rate_constrained(sun8i_chip, pwm->hwpwm)) { + sun8i_pwm_consider_pair_rate(&rounding, current_rate); + } else { + for (unsigned int parent_idx = 0; + parent_idx < clk_hw_get_num_parents(pair->hw); + parent_idx++) { + struct clk_hw *parent; + unsigned long parent_rate; + + parent = clk_hw_get_parent_by_index(pair->hw, parent_idx); + if (!parent) + continue; + parent_rate = clk_hw_get_rate(parent); + if (!parent_rate) + continue; + + for (unsigned int i = 0; sun8i_pwm_div_m_table[i].div; + i++) { + u16 div_m = sun8i_pwm_div_m_table[i].div; + u64 pair_rate; + + pair_rate = DIV_ROUND_UP_ULL(parent_rate, div_m); + if (!pair_rate || pair_rate > U32_MAX) + continue; + sun8i_pwm_consider_pair_rate(&rounding, pair_rate); + } + } + } + + if (!rounding.have_best) + return -EINVAL; + *wfhw = rounding.best; + + dev_dbg(pwmchip_parent(chip), + "pwm#%u: %llu/%llu [+%llu] -> pair-rate=%u, pcr=%#x, ppr=%#x, bypass=%u\n", + pwm->hwpwm, wf->duty_length_ns, wf->period_length_ns, + wf->duty_offset_ns, wfhw->pair_rate, wfhw->pcr, wfhw->ppr, + wfhw->bypass_en); + + return rounding.best_wf.period_length_ns > wf->period_length_ns; +} + +static const struct pwm_ops sun8i_pwm_ops = { + .request = sun8i_pwm_request, + .free = sun8i_pwm_free, + .sizeof_wfhw = sizeof(struct sun8i_pwm_waveform), + .round_waveform_tohw = sun8i_pwm_round_waveform_tohw, + .round_waveform_fromhw = sun8i_pwm_round_waveform_fromhw, + .read_waveform = sun8i_pwm_read_waveform, + .write_waveform = sun8i_pwm_write_waveform, +}; + +/* Register the shared mux, gate and /div_m clock for each channel pair. */ +static int sun8i_pwm_register_pair_clocks(struct device *dev, + struct sun8i_pwm_chip *sun8i_chip) +{ + static const struct clk_parent_data parent_data[] = { + { .index = 0 }, + { .index = 1 }, + }; + + for (unsigned int i = 0; i < SUN8I_PWM_NPAIRS; i++) { + struct sun8i_pwm_pair *pair = &sun8i_chip->pairs[i]; + void __iomem *reg = sun8i_chip->base + SUN8I_PWM_PCCR(i); + const char *name; + int ret; + + name = devm_kasprintf(dev, GFP_KERNEL, + "%s#pwm-clk-src%u%u", dev_name(dev), + i * 2, i * 2 + 1); + if (!name) + return -ENOMEM; + + pair->mux.reg = reg; + pair->mux.shift = SUN8I_PWM_PCCR_SRC_SHIFT; + pair->mux.mask = SUN8I_PWM_PCCR_SRC_MASK; + pair->mux.flags = CLK_MUX_ROUND_CLOSEST; + pair->mux.lock = &sun8i_chip->lock; + + pair->chip = sun8i_chip; + pair->index = i; + + pair->divider.reg = reg; + pair->divider.shift = SUN8I_PWM_PCCR_DIV_M_SHIFT; + pair->divider.width = SUN8I_PWM_PCCR_DIV_M_WIDTH; + pair->divider.table = sun8i_pwm_div_m_table; + pair->divider.lock = &sun8i_chip->lock; + + pair->hw = devm_clk_hw_register_composite_pdata(dev, name, + parent_data, + ARRAY_SIZE(parent_data), + &pair->mux.hw, &clk_mux_ops, + &pair->divider.hw, &clk_divider_ops, + &pair->gate_hw, &sun8i_pwm_pair_gate_ops, 0); + if (IS_ERR(pair->hw)) + return dev_err_probe(dev, PTR_ERR(pair->hw), + "Failed to register pair %u clock\n", i); + + /* Borrow CCF's handle so registration cannot pin this module. */ + pair->rate_nb.notifier_call = sun8i_pwm_pair_rate_notifier; + ret = devm_clk_notifier_register(dev, pair->hw->clk, &pair->rate_nb); + if (ret) + return dev_err_probe(dev, ret, + "Failed to protect pair %u clock rate\n", i); + } + + return 0; +} + +/* + * A disabled pair gate makes any set PER bits ineffective. Clear those stale + * enables before a clock consumer can turn the shared gate on and expose an + * unrequested output. + */ +static void +sun8i_pwm_sanitize_disabled_pairs(struct sun8i_pwm_chip *sun8i_chip) +{ + u32 per; + + guard(spinlock_irqsave)(&sun8i_chip->lock); + per = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PER); + for (unsigned int pair = 0; pair < SUN8I_PWM_NPAIRS; pair++) { + unsigned int first = pair * 2; + u32 pccr; + + pccr = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PCCR(pair)); + if (pccr & SUN8I_PWM_PCCR_GATE) + continue; + + per &= ~sun8i_pwm_pair_enable_mask(pair); + pccr &= ~BIT(SUN8I_PWM_PCCR_BYPASS_BIT(first)); + pccr &= ~BIT(SUN8I_PWM_PCCR_BYPASS_BIT(first + 1)); + sun8i_pwm_writel(sun8i_chip, pccr, SUN8I_PWM_PCCR(pair)); + } + sun8i_pwm_writel(sun8i_chip, per, SUN8I_PWM_PER); +} + +static int sun8i_pwm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct sun8i_pwm_chip *sun8i_chip; + struct reset_control *rst; + struct pwm_chip *chip; + int ret; + + chip = devm_pwmchip_alloc(dev, SUN8I_PWM_NPWM, sizeof(*sun8i_chip)); + if (IS_ERR(chip)) + return dev_err_probe(dev, PTR_ERR(chip), + "Failed to allocate pwmchip\n"); + + sun8i_chip = sun8i_pwm_from_chip(chip); + spin_lock_init(&sun8i_chip->lock); + sun8i_chip->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sun8i_chip->base)) + return dev_err_probe(dev, PTR_ERR(sun8i_chip->base), + "Failed to get PWM base address\n"); + + sun8i_chip->bus_clk = devm_clk_get_enabled(dev, "bus"); + if (IS_ERR(sun8i_chip->bus_clk)) + return dev_err_probe(dev, PTR_ERR(sun8i_chip->bus_clk), + "Failed to get bus clock\n"); + + rst = devm_reset_control_get_shared_deasserted(dev, NULL); + if (IS_ERR(rst)) + return dev_err_probe(dev, PTR_ERR(rst), + "Failed to get reset control\n"); + + chip->ops = &sun8i_pwm_ops; + + sun8i_pwm_sanitize_disabled_pairs(sun8i_chip); + + ret = sun8i_pwm_register_pair_clocks(dev, sun8i_chip); + if (ret) + return ret; + + ret = devm_pwmchip_add(dev, chip); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to add PWM chip\n"); + + return 0; +} + +static const struct of_device_id sun8i_pwm_dt_ids[] = { + { + .compatible = "allwinner,sun50i-h616-pwm", + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, sun8i_pwm_dt_ids); + +static struct platform_driver sun8i_pwm_driver = { + .driver = { + .name = "sun8i-pwm", + .of_match_table = sun8i_pwm_dt_ids, + }, + .probe = sun8i_pwm_probe, +}; +module_platform_driver(sun8i_pwm_driver); + +MODULE_AUTHOR("Richard Genoud "); +MODULE_DESCRIPTION("Allwinner sun8i PWM driver"); +MODULE_LICENSE("GPL"); From patchwork Wed Sep 23 05:36:16 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hilliard X-Patchwork-Id: 3425 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114]) by mxe881.netcup.net (Postfix) with ESMTPS id 814891C103A for ; Wed, 23 Sep 2026 07:36:47 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=gmail.com; spf=pass (sender IP is 172.105.105.114) smtp.mailfrom=linux-sunxi+bounces-26160-noreply=patchwork.local@lists.linux.dev smtp.helo=tor.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.105.105.114 as permitted sender) client-ip=172.105.105.114; envelope-from=linux-sunxi+bounces-26160-noreply=patchwork.local@lists.linux.dev; helo=tor.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by tor.lore.kernel.org (Postfix) with ESMTP id CA6B034DA1 for ; Wed, 23 Sep 2026 05:36:35 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0B24843BDBC; Wed, 23 Sep 2026 05:36:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="a0KZBcXI" X-Original-To: linux-sunxi@lists.linux.dev Received: from mail-oi2-f12.google.com (mail-oi2-f12.google.com [74.125.231.204]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE480395D8B for ; Wed, 23 Sep 2026 05:36:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.231.204 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790141792; cv=none; b=FwV4Na1oJxoEVpe1DOkya7nOqI32r+3c99xl6DU/QTDRqZQdW9AgN6z4LhflcIi2Tki7quJwNbRi79hjHYHIHWPWA7AtcGg2NSH0qKQ6MZpBy4iokAJbxenh7YjAwRBBhnUB66Wdu/qSykpRvrJMhmetLeV0igX97eHmLy6AwPo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790141792; c=relaxed/simple; bh=qEF0C4lsHKeFuSDGZ09aNZCGxWyI9mBkVDKPyBuQmvA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FHHr/XqfcHQmp9Ow8Wsgb87bWvtsjAQYEM1rGYKVj/poXzuQAk0AEF0cwob2FJDulTSLbiY6cSu9w2ZvTgqTdXv+hbC3HwT7NLpuS6E6PzDrbxMoNWwadVIxN5HgrLkmSGzXu5R6XwQLf/q0IWtDGmg3qQ4hqUv73FgTQrokc9I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=a0KZBcXI; arc=none smtp.client-ip=74.125.231.204 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-oi2-f12.google.com with SMTP id 5614622812f47-4c0766cbe64so379005b6e.3 for ; Tue, 22 Sep 2026 22:36:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1790141787; x=1790746587; darn=lists.linux.dev; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=NgzL3+0VR2vstrnTbSdTY8Jq1CjVKq1PLO3C8WC/P48=; b=a0KZBcXI6B3rXNPhZwiEyPpiOVUsrdtGrpgDh2qUqL7zZ6ggZsitsQl3/eUKiWOVTR oOx9cI+dTNMRB66y6wA20ABffo1MZA8acltdzfMeg6KMWkgjc6LfYAhAL3fHBGevQ9oM jo3kb/qTs1GPxOMlEy9rKEoJUYVnXHGaWieH9zNXKKVeeXmFOrhgfwAMMDqalsxlXkXi PiE93odpwSbSODu4rKIU1WQgjSYBhGikfkTLJ6pxX+wGNjjnCBSBeAwnXuvXZGGtKJ/I SdusASu1R949aucytuygjqyJYsW/Z4WeOUSkvfygPdnTHo4vjFI4/ddoIMTXNMIGORKD MhMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1790141787; x=1790746587; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=NgzL3+0VR2vstrnTbSdTY8Jq1CjVKq1PLO3C8WC/P48=; b=uSjxP4ccDF94yr0AeKMQDK14Ltx5d5M/NTPc0so0IDqsT5x/YcmV+PYy0TCcW+SCFJ mEnbXCN1HBthHDgk53U/4PNCrfI8e4DbopcEdfEeI5rqpzkv43fNuc/8m9JcbELxZ6Yy obtpNzkCiS51ER9c0AHlj2TzqVKhR6OxJjkZ3yCteXu828dEz3tlCwoKuQfHV4PedhZP YLxM9/V3C+puLO44ncMJ6pM6vqZFeuGjM8j8bWddgBEATujEJVF3AV05zypLqp5FOyTs zzKcgIC2VedfxmskpwdTLaA7Adgz78kjJHKvcCvPhcHHFL7SUBYDYbztFrJ5l1en8dJw iTBQ== X-Forwarded-Encrypted: i=1; AKwUvByH3IrSUXg6YNCBHu5MCWQpag7Zvhef6miZiLVpfNPSGChZTULur0vH2KaLw2bxINtVowA5nVbD/MM/+A==@lists.linux.dev X-Gm-Message-State: AFuF++kBYASNnLEZrmObARAyxEn4GlT8ia1IiRVyttJrlfzwj37gE3Fk Ly3z8KePbmr5mSot+tRdDILI6hKLhPDop0FtOMqpQIfpncfjG6PXhyCu X-Gm-Gg: AYBFou1Et9Ux3zIsvS6Yb0QWcdvY/cFOcbE3xw/Hoamf7lU5JIX1lsLvo9QHq+tWXzO x3r5tiVHlMqImahMd5Y9V7rcfd6XkFbvGccDNRhoewbjWK/4jZGe3RZ43bS6Iz7ZCGDkAofYYtn mMmIs/etOqDrH/LI29dfq0DNlgVJbhJcs33tC/LNzljE7JoDRs46BltHM8x999HAjFqy9JMF0YG uNRPrZbc2mhqvlYdF41tD2/gL7lzuyjnzqW1A4PJpBgucpcSo6UAWOp8qyvYkzRNtHdLuYKOfW6 ujBEVK95ml8pPzmRN7SCFJZCMxzeTBFAMX/J/vsvxXii/kmbKGlVMoE7hllP9+P7EStjKV+f+Mg kHU3XR7IMHwfYgY1+L6rtql6Js9XcTumT/lgO+fN8IXVdNL0iNibD8cBaegqK+6PQi61GPKaqMI m1h0k51uTRuIPjrkkbOYtc7QE2HCioVUkhQxcPOMpKWuMrfJMK1uLO6gdv8B54uuogjY2/r7nuX w6nRgOuDPTsqyMFtP3EqrXNY9kIA3/8k8OXr33gs+8k5g9AFL6QnAshcwvuU2SLt8/wRbZC+knU yDwQs9/c1hPsKv3T9swf8M79oYnvuERRkapbmzPI+J1SMN+FFmNHBLIG39kEPQfhoQyVi0ssQe7 jkfnr5uy+sX2Or9M5PCKo X-Received: by 2002:a05:6808:4701:b0:4c3:ee9e:200d with SMTP id 5614622812f47-4d5b6eeed37mr1593391b6e.7.1790141786875; Tue, 22 Sep 2026 22:36:26 -0700 (PDT) Received: from [127.0.1.1] (174-29-1-49.hlrn.qwest.net. [174.29.1.49]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4d5c4aed99bsm1436896b6e.12.2026.09.22.22.36.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 22:36:26 -0700 (PDT) From: James Hilliard Date: Tue, 22 Sep 2026 23:36:16 -0600 Subject: [PATCH v10 3/5] pwm: sun8i: export the bypass outputs as clocks Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260922-h616-pwm-v8-v10-3-dccebbe1aabf@gmail.com> References: <20260922-h616-pwm-v8-v10-0-dccebbe1aabf@gmail.com> In-Reply-To: <20260922-h616-pwm-v8-v10-0-dccebbe1aabf@gmail.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Stephen Boyd , Brian Masney , Jerome Brunet , Richard Genoud , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard Cc: Philipp Zabel , Michael Turquette , Paul Kocialkowski , Thomas Petazzoni , John Stultz , Joao Schim , bigunclemax@gmail.com, linux-pwm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, James Hilliard X-Mailer: b4 0.15.2 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= From: Richard Genoud Expose each H616 PWM channel's hardware bypass as a CCF clock. Consumers such as the co-packaged AC200/AC300 PHY need a clock rather than PWM duty or polarity control. Keep the pair source protected for the complete prepared lifetime, and arbitrate ownership between PWM requests and clock prepare so both interfaces cannot drive the same output. drivers/clk/clk-pwm.c advertises a fixed frequency without reading back the rounded PWM rate. A 42 ns, 21 ns request does select 24 MHz bypass when it is available. However, with the pair constrained to 100 MHz by its sibling, the PWM rounding rules select a 40 ns, 20 ns waveform (25 MHz), while a pwm-clock configured for 24 MHz still reports 24 MHz. The direct provider instead reports the actual pair rate and makes its shared-rate protection visible to CCF. Consumers must still check the rate they receive. Use CLK_IGNORE_UNUSED to preserve unclaimed firmware bypass outputs, just as the PWM path preserves inherited waveforms. Normal consumer disable still turns the output off and releases its shared gate reference. Signed-off-by: Richard Genoud Co-developed-by: James Hilliard Signed-off-by: James Hilliard --- drivers/pwm/Kconfig | 3 +- drivers/pwm/pwm-sun8i.c | 180 +++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 180 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index d87d166e7836..d3c35a11859f 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -754,7 +754,8 @@ config PWM_SUN8I depends on HAS_IOMEM && COMMON_CLK help PWM framework driver for Allwinner controllers whose channels share - paired source clocks. + paired source clocks. In addition to PWM operation, each channel's + hardware bypass path can be exported as a clock output. To compile this driver as a module, choose M here: the module will be called pwm-sun8i. diff --git a/drivers/pwm/pwm-sun8i.c b/drivers/pwm/pwm-sun8i.c index 7e6c39815c18..2a687ecb6adc 100644 --- a/drivers/pwm/pwm-sun8i.c +++ b/drivers/pwm/pwm-sun8i.c @@ -113,6 +113,9 @@ * The bypass in PWM mode is used to achieve a 1/2 relative duty cycle with the * fastest clock. * + * SUN8I_PWM_clock_x/y serve for the PWM purpose. + * SUN8I_PWM_bypass_clock_x/y serve for the clock-provider purpose. + * */ /* /div_m is a power-of-two divider limited to /256. */ @@ -129,6 +132,12 @@ static const struct clk_div_table sun8i_pwm_div_m_table[] = { { /* sentinel */ } }; +enum sun8i_pwm_mode { + SUN8I_PWM_MODE_NONE, + SUN8I_PWM_MODE_PWM, + SUN8I_PWM_MODE_CLK, +}; + struct sun8i_pwm_chip; struct sun8i_pwm_pair { @@ -142,8 +151,12 @@ struct sun8i_pwm_pair { }; struct sun8i_pwm_channel { + struct clk_hw bypass_hw; + struct sun8i_pwm_chip *chip; + unsigned int index; /* Separate CCF consumer, held only from PWM request to free. */ struct clk *pair_clk; + enum sun8i_pwm_mode mode; u64 pending_period_ns; bool rate_exclusive; }; @@ -153,7 +166,7 @@ struct sun8i_pwm_chip { struct sun8i_pwm_channel channels[SUN8I_PWM_NPWM]; struct clk *bus_clk; void __iomem *base; - /* Protects shared registers and rate_exclusive. */ + /* Protects shared registers, channel ownership and rate_exclusive. */ spinlock_t lock; }; @@ -317,6 +330,101 @@ static int sun8i_pwm_pair_rate_notifier(struct notifier_block *nb, return active ? NOTIFY_BAD : NOTIFY_OK; } +static inline struct sun8i_pwm_channel * +sun8i_pwm_channel_from_hw(struct clk_hw *hw) +{ + return container_of(hw, struct sun8i_pwm_channel, bypass_hw); +} + +static int sun8i_pwm_bypass_prepare(struct clk_hw *hw) +{ + struct sun8i_pwm_channel *chan = sun8i_pwm_channel_from_hw(hw); + struct sun8i_pwm_chip *sun8i_chip = chan->chip; + + guard(spinlock_irqsave)(&sun8i_chip->lock); + if (chan->mode != SUN8I_PWM_MODE_NONE) + return -EBUSY; + + chan->mode = SUN8I_PWM_MODE_CLK; + return 0; +} + +static void sun8i_pwm_bypass_unprepare(struct clk_hw *hw) +{ + struct sun8i_pwm_channel *chan = sun8i_pwm_channel_from_hw(hw); + struct sun8i_pwm_chip *sun8i_chip = chan->chip; + + guard(spinlock_irqsave)(&sun8i_chip->lock); + if (chan->mode != SUN8I_PWM_MODE_CLK) + return; + + chan->mode = SUN8I_PWM_MODE_NONE; +} + +static int sun8i_pwm_bypass_enable(struct clk_hw *hw) +{ + struct sun8i_pwm_channel *chan = sun8i_pwm_channel_from_hw(hw); + struct sun8i_pwm_chip *sun8i_chip = chan->chip; + unsigned int pair = SUN8I_PWM_PAIR_IDX(chan->index); + u32 pccr, per; + + guard(spinlock_irqsave)(&sun8i_chip->lock); + if (chan->mode != SUN8I_PWM_MODE_CLK) + return -EBUSY; + + pccr = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PCCR(pair)); + per = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PER); + if (!(pccr & BIT(SUN8I_PWM_PCCR_BYPASS_BIT(chan->index))) || + !(per & SUN8I_PWM_ENABLE(chan->index))) { + sun8i_pwm_set_enabled_locked(sun8i_chip, chan->index, false); + sun8i_pwm_set_bypass_locked(sun8i_chip, chan->index, true); + sun8i_pwm_set_enabled_locked(sun8i_chip, chan->index, true); + } + + return 0; +} + +static void sun8i_pwm_bypass_disable(struct clk_hw *hw) +{ + struct sun8i_pwm_channel *chan = sun8i_pwm_channel_from_hw(hw); + struct sun8i_pwm_chip *sun8i_chip = chan->chip; + + guard(spinlock_irqsave)(&sun8i_chip->lock); + if (chan->mode != SUN8I_PWM_MODE_CLK) + return; + + sun8i_pwm_set_enabled_locked(sun8i_chip, chan->index, false); + sun8i_pwm_set_bypass_locked(sun8i_chip, chan->index, false); +} + +static int sun8i_pwm_bypass_is_enabled(struct clk_hw *hw) +{ + struct sun8i_pwm_channel *chan = sun8i_pwm_channel_from_hw(hw); + struct sun8i_pwm_chip *sun8i_chip = chan->chip; + unsigned int pair = SUN8I_PWM_PAIR_IDX(chan->index); + bool enabled; + u32 val; + + guard(spinlock_irqsave)(&sun8i_chip->lock); + + val = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PCCR(pair)); + enabled = (val & SUN8I_PWM_PCCR_GATE) && + (val & BIT(SUN8I_PWM_PCCR_BYPASS_BIT(chan->index))); + + val = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_PER); + enabled = enabled && (val & SUN8I_PWM_ENABLE(chan->index)); + + return enabled; +} + +static const struct clk_ops sun8i_pwm_bypass_ops = { + .prepare = sun8i_pwm_bypass_prepare, + .unprepare = sun8i_pwm_bypass_unprepare, + .enable = sun8i_pwm_bypass_enable, + .disable = sun8i_pwm_bypass_disable, + .is_enabled = sun8i_pwm_bypass_is_enabled, +}; + static void sun8i_pwm_put_rate(struct sun8i_pwm_chip *sun8i_chip, unsigned int idx) { @@ -342,8 +450,12 @@ static int sun8i_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) int ret; scoped_guard(spinlock_irqsave, &sun8i_chip->lock) { + if (chan->mode != SUN8I_PWM_MODE_NONE) + return -EBUSY; + was_enabled = sun8i_pwm_channel_is_enabled_locked(sun8i_chip, idx); + chan->mode = SUN8I_PWM_MODE_PWM; } chan->pair_clk = clk_hw_get_clk(parent, NULL); @@ -372,6 +484,8 @@ static int sun8i_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) clk_put(chan->pair_clk); err_clear_clock: chan->pair_clk = NULL; + scoped_guard(spinlock_irqsave, &sun8i_chip->lock) + chan->mode = SUN8I_PWM_MODE_NONE; return ret; } @@ -382,6 +496,9 @@ static void sun8i_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) struct sun8i_pwm_channel *chan = &sun8i_chip->channels[pwm->hwpwm]; scoped_guard(spinlock_irqsave, &sun8i_chip->lock) { + if (chan->mode != SUN8I_PWM_MODE_PWM) + return; + sun8i_pwm_set_enabled_locked(sun8i_chip, pwm->hwpwm, false); sun8i_pwm_set_bypass_locked(sun8i_chip, pwm->hwpwm, false); } @@ -390,6 +507,9 @@ static void sun8i_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) clk_disable_unprepare(chan->pair_clk); clk_put(chan->pair_clk); chan->pair_clk = NULL; + + scoped_guard(spinlock_irqsave, &sun8i_chip->lock) + chan->mode = SUN8I_PWM_MODE_NONE; } static int sun8i_pwm_read_waveform(struct pwm_chip *chip, @@ -510,7 +630,8 @@ sun8i_pwm_pair_rate_constrained(struct sun8i_pwm_chip *sun8i_chip, unsigned int sibling = idx ^ 1; guard(spinlock_irqsave)(&sun8i_chip->lock); - return sun8i_chip->channels[sibling].rate_exclusive || + return sun8i_chip->channels[sibling].mode == SUN8I_PWM_MODE_CLK || + sun8i_chip->channels[sibling].rate_exclusive || sun8i_pwm_channel_is_enabled_locked(sun8i_chip, sibling); } @@ -984,6 +1105,42 @@ static int sun8i_pwm_register_pair_clocks(struct device *dev, return 0; } +/* Register the bypass clock for each channel. */ +static int sun8i_pwm_register_bypass_clocks(struct device *dev, + struct sun8i_pwm_chip *sun8i_chip) +{ + for (unsigned int i = 0; i < SUN8I_PWM_NPWM; i++) { + struct sun8i_pwm_channel *chan = &sun8i_chip->channels[i]; + struct clk_hw *parent = sun8i_chip->pairs[SUN8I_PWM_PAIR_IDX(i)].hw; + const char *name; + int ret; + + name = devm_kasprintf(dev, GFP_KERNEL, "%s#pwm-bypass%u", + dev_name(dev), i); + if (!name) + return -ENOMEM; + + chan->chip = sun8i_chip; + chan->index = i; + /* + * Protect the shared rate while prepared. Preserve unclaimed + * firmware outputs through CCF's unused-clock cleanup, as for + * PWM waveforms; only a consumer may turn them off. + */ + chan->bypass_hw.init = + CLK_HW_INIT_HW(name, parent, &sun8i_pwm_bypass_ops, + CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE | + CLK_IGNORE_UNUSED); + + ret = devm_clk_hw_register(dev, &chan->bypass_hw); + if (ret) + return dev_err_probe(dev, ret, + "Failed to register bypass clock %u\n", i); + } + + return 0; +} + /* * A disabled pair gate makes any set PER bits ineffective. Clear those stale * enables before a clock consumer can turn the shared gate on and expose an @@ -1012,6 +1169,17 @@ sun8i_pwm_sanitize_disabled_pairs(struct sun8i_pwm_chip *sun8i_chip) sun8i_pwm_writel(sun8i_chip, per, SUN8I_PWM_PER); } +static struct clk_hw *sun8i_pwm_get_clk_hw(struct of_phandle_args *clkspec, + void *data) +{ + struct sun8i_pwm_chip *sun8i_chip = data; + + if (clkspec->args_count != 1 || clkspec->args[0] >= SUN8I_PWM_NPWM) + return ERR_PTR(-EINVAL); + + return &sun8i_chip->channels[clkspec->args[0]].bypass_hw; +} + static int sun8i_pwm_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1050,6 +1218,14 @@ static int sun8i_pwm_probe(struct platform_device *pdev) if (ret) return ret; + ret = sun8i_pwm_register_bypass_clocks(dev, sun8i_chip); + if (ret) + return ret; + + ret = devm_of_clk_add_hw_provider(dev, sun8i_pwm_get_clk_hw, sun8i_chip); + if (ret) + return dev_err_probe(dev, ret, "Failed to add HW clock provider\n"); + ret = devm_pwmchip_add(dev, chip); if (ret < 0) return dev_err_probe(dev, ret, "Failed to add PWM chip\n"); From patchwork Wed Sep 23 05:36:17 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hilliard X-Patchwork-Id: 3428 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id F2FA91C1049 for ; Wed, 23 Sep 2026 07:37:33 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=gmail.com; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-26161-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; envelope-from=linux-sunxi+bounces-26161-noreply=patchwork.local@lists.linux.dev; helo=sea.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sea.lore.kernel.org (Postfix) with ESMTP id A0347394E7 for ; Wed, 23 Sep 2026 05:36:35 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0892143BDB3; Wed, 23 Sep 2026 05:36:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="eN4b+Q0H" X-Original-To: linux-sunxi@lists.linux.dev Received: from mail-oi2-f13.google.com (mail-oi2-f13.google.com [74.125.231.205]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B78043803B for ; Wed, 23 Sep 2026 05:36:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.231.205 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790141792; cv=none; b=JXjMMolT3Tkuj+5j05BlYzlUwMNdiXNDM78cwf5a3++eolI4sah28SSITvh1r+3SfONcJRQRXGqPHTnke3IKbRhIcGHSuTrau7FFv49EGxDHTSDfxqRhcehxgcoK+x8weI3CZjCXGLibFjef1G/36XVPoDN5M3f+RwIY+OCPj3o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790141792; c=relaxed/simple; bh=cxjDKZ0MA9VUms6JcpknLJlKdT7ZoJ5aaylgo7tCtYM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=I8oD9aTVA0usfTIE9TDBj4gZg8cOiac6sZoFmhWWhfILbdCPzzli+MKJ6v0YOu2mv87sukV6OmcOHG4MYPzaGrLKxIu329xZg3WWyfZN5Eq77LZ4bMey3PYAQMwwN2yNtmMh4UZuKmoSQcCx0cgutt+ohO9S16z+XUwHcdey8v8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=eN4b+Q0H; arc=none smtp.client-ip=74.125.231.205 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-oi2-f13.google.com with SMTP id 5614622812f47-4c4bf3defecso442126b6e.3 for ; Tue, 22 Sep 2026 22:36:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1790141788; x=1790746588; darn=lists.linux.dev; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=FHj476tA2byKc8arhZaw8Ci81fHtdMiGqz0hVZIDFng=; b=eN4b+Q0HKDzC8jCURvF+ChM35xSfVSZyC7KjIqEIznSbdXNpRm/+uCZGFkzLX99QS6 TYbeZROH8+IA37wVV4dHk93LzpmS0KER7yddIrj6wf5zWRe3Mih72Bcy/+ouCUYr2EiK SJIZQ0Bq+ThiT9hAZjN6VKFP1GDGmWWheiz67NyEA5Mpp+tTL3ZTcBWyDBzUgFEWDSph 6LhJkqrEfS2wh+4kzZGFCK9/Z4P4Bvutum0WTInqVbF9fQ53yD9yAfoZbVKJuwzjVVvt ig3gdFVp0/prsaj37eTHOSa3OMUdmws519kCS8rto1S7QsuCi2047FGb6HohEXaamtzL P5hA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1790141788; x=1790746588; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=FHj476tA2byKc8arhZaw8Ci81fHtdMiGqz0hVZIDFng=; b=j+3lt9FlsOX1Fk758eJojo+/yw0h3mSWlSR34miUM8tPt2l9nIYT82vtT5kGIfZAWt hTVWPXHr9GzYqkMix6kd8Rvl8G66vDstmkPlNyjp6GFR3rfUKJkTfsDBD2v4+HULEQnY b0ZbY9L3ZeFbA1EDHN672J89bEl+drEMRT6zU6nTZJqFQ7k8W3YEfZSYIR+v+VQ3D0xu Urs7d0DMksDHuaX5Nur35ge/CJ/NYs6znotlFLy+fnODky75mG4XQkMQ8sJH5IPB3eSU ITUm0SS1/OwuJ2fgNrg/eYti66zEQKNZ2lzGg2SA0A+svfuppfAzduTrIeoWZ3TR46aO KTgQ== X-Forwarded-Encrypted: i=1; AKwUvByYnjBKLDQLcY/NKWpzchj5Gx/QKpqs2Thegkq5xobaf/6CzG2vxG78AjHQnt2MazfV5mmcLOeHpTEnvg==@lists.linux.dev X-Gm-Message-State: AFuF++m1sh65B6j5Yg0Q1cBG2jojrgIUG/AQqKq/zlV5xFnTmy187cH9 8MOo4faAa8Sul3EPo6N+8pwXUrYleq7biYPn7vKRXLQS4b4N4OpXrZsL X-Gm-Gg: AYBFou0yT4U457Omr/VIH4i/1BVKFX+dzULaV6mi/6o2QnJD+MdbIfawlteEQdnjJeB wWM4TAbKIX0fWnubUW9w8L5U+ETjHdK6QHu3v3RCsuwLZ+F5vJL228ErYq19mA1fB1bqLZHS99l lR2T1Dg8dD/atTTLpl9hUVYDJHWwBfikPcTBLN9Wj9my2BXvAsRhIhO4ndAfIg4JZq4QWYVwfRU QKmNOUmdAp15mSNbVyH/Ldj5M+uq7GakKHSfImNzw63ZMCkl2MvwXx+CpPeAvT81X0g47g7QjQE NCPjh1iX4i88ZvjdiCnbdlcAAmqGYRUiaS2u6SfPrY/FON5x94ZkygvGM8rEcw2jEM1mHBN62cM 4Kt9za/VD0cvjCZ7MguoQNR5Ljz7p7VBTjQvAhW0kWeGQCobMziw6ZL5Psf41UYzSi/KbS7c8gO 57Dd81XUNz3HBRvygyfOdBTYq/3jMSQlWG7S2MpQghX9VKOx6Dk6wq+et5nIIPZvfZ08luiIX9d JdMypK70y5PUFPHWy3AcZ/SmpmYqaGsYphPPzI+UDkqQuODQAlZxudhFX/B1p5GNuFvw24BbIdB hH2ZYD9S0Px6v2TUUkOFLndIKTX9fYGvSQX77Voy+3eO7oy5byLopba39a/YsedSuIr5L0z/Sdj WDsdkuIpPJWCLpuKpn5wi X-Received: by 2002:a05:6808:1783:b0:4c6:eddf:ca6f with SMTP id 5614622812f47-4d5b6bda069mr1922304b6e.12.1790141788407; Tue, 22 Sep 2026 22:36:28 -0700 (PDT) Received: from [127.0.1.1] (174-29-1-49.hlrn.qwest.net. [174.29.1.49]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4d5c4aed99bsm1436896b6e.12.2026.09.22.22.36.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 22:36:27 -0700 (PDT) From: James Hilliard Date: Tue, 22 Sep 2026 23:36:17 -0600 Subject: [PATCH v10 4/5] arm64: dts: allwinner: h616: add PWM controller Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260922-h616-pwm-v8-v10-4-dccebbe1aabf@gmail.com> References: <20260922-h616-pwm-v8-v10-0-dccebbe1aabf@gmail.com> In-Reply-To: <20260922-h616-pwm-v8-v10-0-dccebbe1aabf@gmail.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Stephen Boyd , Brian Masney , Jerome Brunet , Richard Genoud , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard Cc: Philipp Zabel , Michael Turquette , Paul Kocialkowski , Thomas Petazzoni , John Stultz , Joao Schim , bigunclemax@gmail.com, linux-pwm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, James Hilliard X-Mailer: b4 0.15.2 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-1.16 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.234.253.10:from]; SUSPICIOUS_RECIPS(1.50)[]; DMARC_POLICY_SOFTFAIL(1.00)[gmail.com : SPF not aligned (relaxed), No valid DKIM,none]; MAILLIST(-0.15)[generic]; BAD_REP_POLICIES(0.10)[]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; RCVD_COUNT_FIVE(0.00)[6]; FROM_HAS_DN(0.00)[]; FORGED_SENDER_MAILLIST(0.00)[]; RCPT_COUNT_TWELVE(0.00)[26]; PRECEDENCE_BULK(0.00)[]; FREEMAIL_CC(0.00)[pengutronix.de,baylibre.com,sys-base.io,bootlin.com,google.com,schimsalabim.eu,gmail.com,vger.kernel.org,lists.infradead.org,lists.linux.dev]; TAGGED_RCPT(0.00)[clk,dt]; DBL_BLOCKED_OPENRESOLVER(0.00)[bootlin.com:email,sea.lore.kernel.org:rdns,sea.lore.kernel.org:helo]; FROM_NEQ_ENVFROM(0.00)[jameshilliard1@gmail.com,linux-sunxi@lists.linux.dev]; TAGGED_FROM(0.00)[bounces-26161-noreply=patchwork.local]; FREEMAIL_FROM(0.00)[gmail.com]; R_SPF_ALLOW(0.00)[+ip4:172.234.253.10]; TO_DN_SOME(0.00)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.234.253.10:from]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[74.125.231.205:received,100.90.174.1:received,174.29.1.49:received]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; FREEMAIL_TO(0.00)[kernel.org,redhat.com,baylibre.com,bootlin.com,gmail.com,sholland.org]; MIME_TRACE(0.00)[0:+]; MID_RHS_MATCH_FROM(0.00)[]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; RCVD_TLS_LAST(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: F2FA91C1049 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= From: Richard Genoud The H616 has a PWM controller that can provide PWM signals, but also plain clocks. Add the PWM controller node and pins in the device tree. Signed-off-by: Richard Genoud Signed-off-by: James Hilliard --- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 47 ++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index 1598e86259ab..90fe56a1d3cd 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -281,6 +281,17 @@ watchdog: watchdog@30090a0 { clocks = <&osc24M>; }; + pwm: pwm@300a000 { + compatible = "allwinner,sun50i-h616-pwm"; + reg = <0x0300a000 0x400>; + clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; + clock-names = "mod", "bus"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <3>; + #clock-cells = <1>; + status = "disabled"; + }; + pio: pinctrl@300b000 { compatible = "allwinner,sun50i-h616-pinctrl"; reg = <0x0300b000 0x400>; @@ -385,6 +396,42 @@ nand_rb1_pin: nand-rb1-pin { bias-pull-up; }; + /omit-if-no-ref/ + pwm0_pin: pwm0-pin { + pins = "PD28"; + function = "pwm0"; + }; + + /omit-if-no-ref/ + pwm1_pin: pwm1-pin { + pins = "PG19"; + function = "pwm1"; + }; + + /omit-if-no-ref/ + pwm2_pin: pwm2-pin { + pins = "PH2"; + function = "pwm2"; + }; + + /omit-if-no-ref/ + pwm3_pin: pwm3-pin { + pins = "PH0"; + function = "pwm3"; + }; + + /omit-if-no-ref/ + pwm4_pin: pwm4-pin { + pins = "PI14"; + function = "pwm4"; + }; + + /omit-if-no-ref/ + pwm5_pin: pwm5-pin { + pins = "PA12"; + function = "pwm5"; + }; + /omit-if-no-ref/ spi0_pins: spi0-pins { pins = "PC0", "PC2", "PC4"; From patchwork Wed Sep 23 05:36:18 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hilliard X-Patchwork-Id: 3427 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sin.lore.kernel.org (sin.lore.kernel.org [104.64.211.4]) by mxe881.netcup.net (Postfix) with ESMTPS id 80C411C1035 for ; Wed, 23 Sep 2026 07:36:51 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=gmail.com; spf=pass (sender IP is 104.64.211.4) smtp.mailfrom=linux-sunxi+bounces-26163-noreply=patchwork.local@lists.linux.dev smtp.helo=sin.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 104.64.211.4 as permitted sender) client-ip=104.64.211.4; envelope-from=linux-sunxi+bounces-26163-noreply=patchwork.local@lists.linux.dev; helo=sin.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by sin.lore.kernel.org (Postfix) with ESMTP id 8692629BAC for ; Wed, 23 Sep 2026 05:36:40 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E928843CE70; Wed, 23 Sep 2026 05:36:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OdmuxrTj" X-Original-To: linux-sunxi@lists.linux.dev Received: from mail-oi2-f13.google.com (mail-oi2-f13.google.com [74.125.231.205]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40CF54349B9 for ; Wed, 23 Sep 2026 05:36:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.231.205 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790141793; cv=none; b=NdFrXMVSjM7U/gqVEHUk6fTNNoSpc50mIH3d+NLP8zrF1Yp2dQV7EZtYYNI2RMQo8KOpGdM++k0hhMvyVIc8vCbay0sefmDB6g92j78LezqZd4OTR8axnRDcNmxoUELasXnRbTFkyP8mmUc/LUb1pu09sKQqwE27OM/i4oW3H8w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790141793; c=relaxed/simple; bh=OJS6mQlRWmTTimOyj6kC0TvQSBszoDm45iW9XPqV2AQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=B8BD+Pnshjd3MVh6CX9dKNCJKEcLAwQs+r4e+eHC9cPAX6KEj+b9lrELKD4zBmdamhF56/GpVwLlN/XGEjM4sOtQE1sLN3d0DuV09U0wN2L24q5Wc2dpz1C7DTl6EOUd84FYAjbglFZx6d84ES9bYERnzicTuR0CYCXFvalNMGM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=OdmuxrTj; arc=none smtp.client-ip=74.125.231.205 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-oi2-f13.google.com with SMTP id 5614622812f47-4c537df4daaso283894b6e.1 for ; Tue, 22 Sep 2026 22:36:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1790141790; x=1790746590; darn=lists.linux.dev; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=xhBI/4MYKZ9FiatfUTHQXDlddZz4ARJ+4t2N8WN0Mwk=; b=OdmuxrTj8Rg0L8Xfojy0qbxLMJ1AeUI1z2cgKzw74VWpnIGK0QeFEAhGVFVuV93KFm r82IGYhK8m8P7v3U15ANMISkxet2fDUQBPxKkQrfYCBIs/ZXE+jD2hB/yKYYFE0V7kcz iFzIPEDdiJEz+vOx6J+viiqojLifSm6uU3MmuHRNrrQ0vKFo6/M1T1jiLKZ3LLwA7CM3 ezh71HLGoujfy68kJZi+utVm/RgYTkVJNsL8vY8qavpYAvrU8PIoESrx2cqTRhmjhDOp hkGcHMM4vixGijtxjCCZP0Yw9N0uIWe3wtWZejLSzbQi2qatNGZQss+OcTXGCDIqP2xN cCXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1790141790; x=1790746590; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=xhBI/4MYKZ9FiatfUTHQXDlddZz4ARJ+4t2N8WN0Mwk=; b=iWlujqPiy8tHAdAlnmuQXyoplXpb2pQuMlJErJvxU+TRGsRUH7zujR6W24g0ZAVmY4 g8ozDTlkypE8SVgBunfzY0P+fQimc9IMK8Mb17nG0HG31FphtEjc3qoRP9K7iAvvZiYN /e0VwqLilD6c7rTTZwMaXSVe526fOYQ55XFZ6jMJrr0Udyl7uPyOKpigZvZmpGoRqo/B KZviI45YeY66b2cM5Fk3ytPUk2UcqnkhGOEFUMLxQfwXCKIjtRjEpDwtlz4trLi884zT rLVeDrQO9XbZA7qP5ULPBOIzBXYD+hziKP/75FDfpD4wBFNKB7O+KK8hlPujeOnMzqGr Hudg== X-Forwarded-Encrypted: i=1; AKwUvBzhVxxiwOA87SP27OyCuZq1oNxBwV3CYvBsQWrgpxKSSFikikSQoiAZGCkOa1Fho/mTd/gG6og6NmZy1A==@lists.linux.dev X-Gm-Message-State: AFuF++ki9hU8dNMZtbzg7FAb2Lnh4tgoAYkUMNVe4MOGd5cXCbVnlC6o aEULhcOAfzePdebfl2yhsROOxN4jcuaOq/6eMXyCWSlZaSono+3IzWkZ X-Gm-Gg: AYBFou2RF/wTUhIRIFp6M5gqBd1H27O4fBRkybpk68SflofoEpyq+bQgt7c+zW0T1fj iQbdB6s+cimuvNaWDjlLX5bgwqARhY79/VI24JPk8eFNaBFwpkYxsCaRiPLwbjcmPsDzxzYGmez 3BJQKuDIP9VLDseUKXHjcMchJC/Y4ILb3HCwwL2qUdn12tiUy0OOfwOdhFST8Chs8kpgXCBcmFl FJFqGNumpbZrOminH95Nk/uAWeDnGcwfLu97VSu3Rshj91lumWcm63Z5Af+Qy8M8jgeUABVISqR UrEuSklh86i3g4+XCxaXpjiQ/pZnEZcONml5fj4iGc18UbEqrSbZuXPGtiyAQG57OiSgTClwYP6 OBrX9QWozTsk1g9LJd50pAwlMjAXMnjFPXMkphGQvMdCMBc/0JZOwMnmxsAOHF2nW3hJo9qEE/8 GcY4oB4dV98zR9axsnZzyk6JmFFe+Pdq4z+FW1zAduKMdyD5Rz2cvU4YQ9bnXDEIm9owBz6LT5O N36VuiUAt6HrL61EibIOmrnLhMJ4d13Aj6If8L1w1hBWJisWVhdx4Sesol2siCgjwv+URQrjmRK HRD4gQBIrR9+lSLI5ni5ViL7Wo2DI4HtI+/x7yKcXId7NhjappMqTS4DlIlefFK/nmfvb4gokf9 jYCB7AhODRH+uz4ARxJLA X-Received: by 2002:a05:6808:1495:b0:4b9:e5fa:8a1d with SMTP id 5614622812f47-4d5ba092ea7mr1861997b6e.34.1790141789974; Tue, 22 Sep 2026 22:36:29 -0700 (PDT) Received: from [127.0.1.1] (174-29-1-49.hlrn.qwest.net. [174.29.1.49]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4d5c4aed99bsm1436896b6e.12.2026.09.22.22.36.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 22:36:29 -0700 (PDT) From: James Hilliard Date: Tue, 22 Sep 2026 23:36:18 -0600 Subject: [PATCH v10 5/5] MAINTAINERS: Add entry on Allwinner sun8i/H616 PWM driver Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20260922-h616-pwm-v8-v10-5-dccebbe1aabf@gmail.com> References: <20260922-h616-pwm-v8-v10-0-dccebbe1aabf@gmail.com> In-Reply-To: <20260922-h616-pwm-v8-v10-0-dccebbe1aabf@gmail.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Stephen Boyd , Brian Masney , Jerome Brunet , Richard Genoud , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard Cc: Philipp Zabel , Michael Turquette , Paul Kocialkowski , Thomas Petazzoni , John Stultz , Joao Schim , bigunclemax@gmail.com, linux-pwm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, James Hilliard X-Mailer: b4 0.15.2 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= From: Richard Genoud Add myself as maintainer of Allwinner SUN8I PWM driver. Signed-off-by: Richard Genoud Signed-off-by: James Hilliard --- MAINTAINERS | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cc3cae2e378b..d9713b1044c2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -918,6 +918,11 @@ S: Maintained F: Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml F: drivers/hwspinlock/sun6i_hwspinlock.c +ALLWINNER SUN8I PWM DRIVER +M: Richard Genoud +S: Maintained +F: drivers/pwm/pwm-sun8i.c + ALLWINNER THERMAL DRIVER M: Vasily Khoruzhick M: Yangtao Li