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[78.137.176.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae5c8a44sm177243566b.20.2026.09.23.13.17.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 13:17:33 -0700 (PDT) From: Pablo Mazzini To: Brian Masney , Chen-Yu Tsai , Conor Dooley , Jernej Skrabec , Jerome Brunet , Krzysztof Kozlowski , Maxime Ripard , Philipp Zabel , Rob Herring , Samuel Holland , Stephen Boyd Cc: Pablo Mazzini , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v1 01/11] dt-bindings: clock: add Allwinner B288 CCU Date: Wed, 23 Sep 2026 21:16:51 +0100 Message-ID: <20260923201701.43391-1-pmazzini@gmail.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [0.34 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.232.135.74:from]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; DMARC_POLICY_SOFTFAIL(1.00)[gmail.com : SPF not aligned (relaxed), No valid DKIM,none]; R_MISSING_CHARSET(0.50)[]; MAILLIST(-0.15)[generic]; BAD_REP_POLICIES(0.10)[]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; PRECEDENCE_BULK(0.00)[]; FROM_HAS_DN(0.00)[]; TAGGED_RCPT(0.00)[clk,dt]; FREEMAIL_CC(0.00)[gmail.com,vger.kernel.org,lists.infradead.org,lists.linux.dev]; FORGED_SENDER_MAILLIST(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[sto.lore.kernel.org:rdns,sto.lore.kernel.org:helo,csie.org:email]; RCPT_COUNT_TWELVE(0.00)[17]; FROM_NEQ_ENVFROM(0.00)[pmazzini@gmail.com,linux-sunxi@lists.linux.dev]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; R_SPF_ALLOW(0.00)[+ip4:172.232.135.74:c]; FREEMAIL_FROM(0.00)[gmail.com]; TO_DN_SOME(0.00)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.232.135.74:from]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[100.90.174.1:received,78.137.176.146:received]; RCVD_COUNT_FIVE(0.00)[6]; FREEMAIL_TO(0.00)[redhat.com,kernel.org,gmail.com,baylibre.com,pengutronix.de,sholland.org]; MIME_TRACE(0.00)[0:+]; TAGGED_FROM(0.00)[bounces-26206-noreply=patchwork.local]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; ASN(0.00)[asn:63949, ipnet:172.232.128.0/19, country:SG]; RCVD_TLS_LAST(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 70D451C014B X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The B288 (sun8iw10p1) is a dual Cortex-A7 SoC used in e-book readers. Signed-off-by: Pablo Mazzini --- .../clock/allwinner,sun8i-b288-ccu.yaml | 55 ++++++++++++ include/dt-bindings/clock/sun8i-b288-ccu.h | 90 +++++++++++++++++++ include/dt-bindings/reset/sun8i-b288-ccu.h | 45 ++++++++++ 3 files changed, 190 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/allwinner,sun8i-b288-ccu.yaml create mode 100644 include/dt-bindings/clock/sun8i-b288-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-b288-ccu.h diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun8i-b288-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun8i-b288-ccu.yaml new file mode 100644 index 000000000000..22b59d5b652c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun8i-b288-ccu.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun8i-b288-ccu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner B288 Clock Control Unit + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + compatible: + const: allwinner,sun8i-b288-ccu + + reg: + maxItems: 1 + + clocks: + items: + - description: High Frequency Oscillator + - description: Low Frequency Oscillator + + clock-names: + items: + - const: hosc + - const: losc + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + ccu: clock-controller@1c20000 { + compatible = "allwinner,sun8i-b288-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/sun8i-b288-ccu.h b/include/dt-bindings/clock/sun8i-b288-ccu.h new file mode 100644 index 000000000000..3dc1704d001e --- /dev/null +++ b/include/dt-bindings/clock/sun8i-b288-ccu.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +#ifndef _DT_BINDINGS_CLK_SUN8I_B288_H_ +#define _DT_BINDINGS_CLK_SUN8I_B288_H_ + +#define CLK_PLL_CPUX 0 +#define CLK_PLL_AUDIO_BASE 1 +#define CLK_PLL_VIDEO0 2 +#define CLK_PLL_DDR0 3 +#define CLK_PLL_PERIPH0 4 +#define CLK_PLL_VIDEO1 5 +#define CLK_PLL_24M 6 +#define CLK_PLL_PERIPH1 7 +#define CLK_PLL_DE 8 +#define CLK_PLL_DDR1 9 + +#define CLK_PLL_PERIPH0_2X 10 +#define CLK_PLL_PERIPH1_2X 11 +#define CLK_CPUX 12 +#define CLK_AXI 13 +#define CLK_CPUAPB 14 +#define CLK_AHB1 15 +#define CLK_APB1 16 +#define CLK_APB2 17 + +#define CLK_NAND 18 +#define CLK_MMC0 19 +#define CLK_MMC1 20 +#define CLK_MMC2 21 +#define CLK_MMC3 22 +#define CLK_SPI0 23 +#define CLK_SPI1 24 +#define CLK_SPI2 25 +#define CLK_DRAM 26 +#define CLK_DE 27 +#define CLK_EE 28 +#define CLK_EDMA 29 +#define CLK_TCON0 30 +#define CLK_MBUS 31 + +#define CLK_BUS_THS 32 +#define CLK_BUS_NAND 33 +#define CLK_BUS_SDMMC0_BUS 34 +#define CLK_BUS_SDMMC1_BUS 35 +#define CLK_BUS_SDMMC2_BUS 36 +#define CLK_BUS_SDMMC3_BUS 37 +#define CLK_BUS_SPI0 38 +#define CLK_BUS_SPI1 39 +#define CLK_BUS_SPI2 40 +#define CLK_BUS_I2S0 41 +#define CLK_BUS_I2S1 42 +#define CLK_BUS_SPDIF 43 +#define CLK_BUS_DSD 44 +#define CLK_BUS_DMIC 45 +#define CLK_BUS_USBOHCI0 46 +#define CLK_BUS_USBEHCI0 47 +#define CLK_BUS_USBOTG 48 +#define CLK_BUS_DE 49 +#define CLK_BUS_EE 50 +#define CLK_BUS_TCON0 51 +#define CLK_BUS_CSI_S 52 +#define CLK_BUS_CSI_M 53 +#define CLK_BUS_CSI_MISC 54 +#define CLK_BUS_ADDA 55 +#define CLK_BUS_SDRAM 56 +#define CLK_BUS_PSRAM 57 +#define CLK_BUS_DMA 58 +#define CLK_BUS_UART0 59 +#define CLK_BUS_UART1 60 +#define CLK_BUS_UART2 61 +#define CLK_BUS_UART3 62 +#define CLK_BUS_UART4 63 +#define CLK_BUS_UART5 64 +#define CLK_BUS_TWI0 65 +#define CLK_BUS_TWI1 66 +#define CLK_BUS_TWI2 67 +#define CLK_BUS_PIO 68 +#define CLK_BUS_GPADC 69 +#define CLK_BUS_KEYADC 70 + +/* + * mmc0 and mmc1 are v4p1x controllers driven in the old timing mode, which + * needs the sample and output phase clocks. mmc2 and mmc3 are newer blocks + * that do their own delay calibration and have none. + */ +#define CLK_MMC0_SAMPLE 71 +#define CLK_MMC0_OUTPUT 72 +#define CLK_MMC1_SAMPLE 73 +#define CLK_MMC1_OUTPUT 74 + +#endif diff --git a/include/dt-bindings/reset/sun8i-b288-ccu.h b/include/dt-bindings/reset/sun8i-b288-ccu.h new file mode 100644 index 000000000000..675145654548 --- /dev/null +++ b/include/dt-bindings/reset/sun8i-b288-ccu.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +#ifndef _DT_BINDINGS_RST_SUN8I_B288_H_ +#define _DT_BINDINGS_RST_SUN8I_B288_H_ + +#define RST_BUS_THS 0 +#define RST_BUS_NAND 1 +#define RST_BUS_MMC0 2 +#define RST_BUS_MMC1 3 +#define RST_BUS_MMC2 4 +#define RST_BUS_MMC3 5 +#define RST_BUS_SPI0 6 +#define RST_BUS_SPI1 7 +#define RST_BUS_SPI2 8 +#define RST_BUS_I2S0 9 +#define RST_BUS_I2S1 10 +#define RST_BUS_SPDIF 11 +#define RST_BUS_DSD 12 +#define RST_BUS_DMIC 13 +#define RST_USBPHY0 14 +#define RST_BUS_OHCI0 15 +#define RST_BUS_EHCI0 16 +#define RST_BUS_OTG 17 +#define RST_BUS_DE 18 +#define RST_BUS_EE 19 +#define RST_BUS_TCON0 20 +#define RST_BUS_CSI 21 +#define RST_BUS_ADDA 22 +#define RST_BUS_WLAN 23 +#define RST_MBUS 24 +#define RST_BUS_DRAM 25 +#define RST_BUS_PSRAM 26 +#define RST_BUS_DMA 27 +#define RST_BUS_UART0 28 +#define RST_BUS_UART1 29 +#define RST_BUS_UART2 30 +#define RST_BUS_UART3 31 +#define RST_BUS_UART4 32 +#define RST_BUS_UART5 33 +#define RST_BUS_I2C0 34 +#define RST_BUS_I2C1 35 +#define RST_BUS_I2C2 36 +#define RST_BUS_GPADC 37 +#define RST_BUS_KEYADC 38 + +#endif From patchwork Wed Sep 23 20:16:52 2026 Content-Type: text/plain; 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[78.137.176.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae5c8a44sm177243566b.20.2026.09.23.13.22.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 13:22:52 -0700 (PDT) From: Pablo Mazzini To: Brian Masney , Chen-Yu Tsai , Jernej Skrabec , Jerome Brunet , Samuel Holland , Stephen Boyd Cc: Pablo Mazzini , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v1 02/11] clk: sunxi-ng: add Allwinner B288 CCU driver Date: Wed, 23 Sep 2026 21:16:52 +0100 Message-ID: <20260923201701.43391-2-pmazzini@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260923201701.43391-1-pmazzini@gmail.com> References: <20260923201701.43391-1-pmazzini@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [0.34 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.234.253.10:from]; SUSPICIOUS_RECIPS(1.50)[]; DMARC_POLICY_SOFTFAIL(1.00)[gmail.com : SPF not aligned (relaxed), No valid DKIM,none]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; MAILLIST(-0.15)[generic]; BAD_REP_POLICIES(0.10)[]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; FORGED_SENDER_MAILLIST(0.00)[]; FROM_HAS_DN(0.00)[]; PRECEDENCE_BULK(0.00)[]; TAGGED_RCPT(0.00)[clk]; FREEMAIL_CC(0.00)[gmail.com,lists.infradead.org,vger.kernel.org,lists.linux.dev]; DBL_BLOCKED_OPENRESOLVER(0.00)[sea.lore.kernel.org:rdns,sea.lore.kernel.org:helo]; RCVD_COUNT_FIVE(0.00)[6]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; TAGGED_FROM(0.00)[bounces-26207-noreply=patchwork.local]; R_SPF_ALLOW(0.00)[+ip4:172.234.253.10:c]; FREEMAIL_FROM(0.00)[gmail.com]; TO_DN_SOME(0.00)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.234.253.10:from]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[78.137.176.146:received,74.125.228.171:received,100.90.174.1:received]; FROM_NEQ_ENVFROM(0.00)[pmazzini@gmail.com,linux-sunxi@lists.linux.dev]; RCPT_COUNT_SEVEN(0.00)[11]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; ASN(0.00)[asn:63949, ipnet:172.234.224.0/19, country:SG]; FREEMAIL_TO(0.00)[redhat.com,kernel.org,gmail.com,baylibre.com,sholland.org]; RCVD_TLS_LAST(0.00)[]; MIME_TRACE(0.00)[0:+]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 347061C2AE8 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Covers the PLLs, the CPU/AHB/APB tree, the module clocks and the bus gates and resets. Signed-off-by: Pablo Mazzini --- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-sun8i-b288.c | 669 ++++++++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun8i-b288.h | 10 + 4 files changed, 685 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-b288.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-b288.h diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 6af2d020e03e..5bdfb8574794 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -88,6 +88,11 @@ config SUN6I_RTC_CCU default ARCH_SUNXI depends on MACH_SUN8I || ARM64 || RISCV || COMPILE_TEST +config SUN8I_B288_CCU + tristate "Support for the Allwinner B288 CCU" + default ARCH_SUNXI + depends on MACH_SUN8I || COMPILE_TEST + config SUN8I_A23_CCU tristate "Support for the Allwinner A23 CCU" default ARCH_SUNXI diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index a1c4087d7241..dcc377a09ccc 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_SUN4I_A10_CCU) += sun4i-a10-ccu.o obj-$(CONFIG_SUN5I_CCU) += sun5i-ccu.o obj-$(CONFIG_SUN6I_A31_CCU) += sun6i-a31-ccu.o obj-$(CONFIG_SUN6I_RTC_CCU) += sun6i-rtc-ccu.o +obj-$(CONFIG_SUN8I_B288_CCU) += ccu-sun8i-b288.o obj-$(CONFIG_SUN8I_A23_CCU) += sun8i-a23-ccu.o obj-$(CONFIG_SUN8I_A33_CCU) += sun8i-a33-ccu.o obj-$(CONFIG_SUN8I_A83T_CCU) += sun8i-a83t-ccu.o diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-b288.c b/drivers/clk/sunxi-ng/ccu-sun8i-b288.c new file mode 100644 index 000000000000..4c3ce02878d2 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun8i-b288.c @@ -0,0 +1,669 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Clock Control Unit driver for the Allwinner B288 (sun8iw10p1). + * + * Closely related to the A64: nine of eleven PLLs are bit-identical. + * Transcribed from the BSP clk-sun8iw10.{c,h} and cross-checked against + * ccu-sun50i-a64.c; divergences are called out inline. + * + * The audio clock tree (i2s/spdif/dsd/dmic/adda) is not implemented. + */ + +#include +#include +#include +#include +#include + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_mult.h" +#include "ccu_nk.h" +#include "ccu_nkm.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" +#include "ccu_phase.h" + +#include "ccu-sun8i-b288.h" + +/* + * PLL_CPU @ 0x000 -- N[12:8] K[5:4] M[1:0] P[17:16], gate 31, lock 28. + * Identical to sun50i-a64. + */ +static struct ccu_nkmp pll_cpux_clk = { + .enable = BIT(31), + .lock = BIT(28), + .n = _SUNXI_CCU_MULT(8, 5), + .k = _SUNXI_CCU_MULT(4, 2), + .m = _SUNXI_CCU_DIV(0, 2), + .p = _SUNXI_CCU_DIV_MAX(16, 2, 4), + .common = { + .reg = 0x000, + .hw.init = CLK_HW_INIT("pll-cpux", "osc24M", + &ccu_nkmp_ops, + CLK_SET_RATE_UNGATE), + }, +}; + +/* + * PLL_AUDIO @ 0x008 -- N[14:8] M[4:0], gate 31, lock 28. + * The vendor also writes a sigma-delta pattern at PLL_AUDIOPAT (0x284); + * not transcribed, so plain NM here. + */ +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", + "osc24M", 0x008, + 8, 7, /* N */ + 0, 5, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +/* PLL_VIDEO0 @ 0x010 -- identical to sun50i-a64. */ +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", + "osc24M", 0x010, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +/* + * PLL_DDR0 @ 0x020 -- DIVERGES FROM A64, which is NKM with N[12:8] K[5:4]. + * The B288 has a 7-bit N and no K, confirmed on hardware: with DRAM up, + * PLL_DDR1 reads 0x90003700, i.e. N[14:8] = 55 -> 56 x 24MHz = 1344MHz, + * half of which is the 672MHz boot0 configures. Bit 13 is set, so the + * value cannot be expressed in A64's 5-bit N field at all. + * + * The vendor's bit-30 apply/update has no mainline equivalent and is not + * modelled, nor are the sigma-delta patterns at 0x2ac..0x2b8. + */ +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0", + "osc24M", 0x020, + 8, 7, /* N */ + 0, 2, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +/* PLL_PERIPH0 @ 0x028 -- identical to sun50i-a64, incl. fixed post-div 2. */ +static struct ccu_nk pll_periph0_clk = { + .enable = BIT(31), + .lock = BIT(28), + .n = _SUNXI_CCU_MULT(8, 5), + .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), + .fixed_post_div = 2, + .common = { + .reg = 0x028, + .features = CCU_FEATURE_FIXED_POSTDIV, + .hw.init = CLK_HW_INIT("pll-periph0", "osc24M", + &ccu_nk_ops, 0), + }, +}; + +/* PLL_VIDEO1 @ 0x030 -- same layout as PLL_VIDEO0. */ +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1", + "osc24M", 0x030, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +/* + * PLL_24M @ 0x034 -- B288 only, no a64 equivalent. + * Vendor: N[14:8] K[20:16] M[1:0] P[7:4]. The unusual K position means the + * generic NKMP macro cannot be used; declared longhand. + */ +static struct ccu_nkmp pll_24m_clk = { + .enable = BIT(31), + .lock = BIT(28), + .n = _SUNXI_CCU_MULT(8, 7), + .k = _SUNXI_CCU_MULT(16, 5), + .m = _SUNXI_CCU_DIV(0, 2), + .p = _SUNXI_CCU_DIV(4, 4), + .common = { + .reg = 0x034, + .hw.init = CLK_HW_INIT("pll-24m", "osc24M", + &ccu_nkmp_ops, + CLK_SET_RATE_UNGATE), + }, +}; + +/* PLL_PERIPH1 @ 0x044 -- identical to sun50i-a64. */ +static struct ccu_nk pll_periph1_clk = { + .enable = BIT(31), + .lock = BIT(28), + .n = _SUNXI_CCU_MULT(8, 5), + .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), + .fixed_post_div = 2, + .common = { + .reg = 0x044, + .features = CCU_FEATURE_FIXED_POSTDIV, + .hw.init = CLK_HW_INIT("pll-periph1", "osc24M", + &ccu_nk_ops, 0), + }, +}; + +/* PLL_DE @ 0x048 -- identical to sun50i-a64. */ +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", + "osc24M", 0x048, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +/* PLL_DDR1 @ 0x04c -- B288 only. Same layout; this is the one feeding DRAM. */ +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", + "osc24M", 0x04c, + 8, 7, /* N */ + 0, 2, /* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); + +/* + * Multiplied PLL outputs. pll_periph{0,1} carry a fixed /2 post-divider, so + * the "2x" clocks the vendor's periphx2_parents refer to are the raw outputs. + */ +static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x", + &pll_periph0_clk.common.hw, + 1, 2, 0); +static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x", + &pll_periph1_clk.common.hw, + 1, 2, 0); + +/* + * CPU_CFG @ 0x050 -- mux[17:16], CPUAPB divider [9:8], AXI divider [1:0]. + * Same layout as the H3 and the A64. + */ +/* vendor: cpu_parents */ +static const char * const cpux_parents[] = { "osc32k", "osc24M", + "pll-cpux", "pll-cpux" }; +static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, + 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT); + +static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0); +static SUNXI_CCU_M(cpuapb_clk, "cpuapb", "cpux", 0x050, 8, 2, 0); + +/* + * AHB1_CFG @ 0x054 -- mux[13:12], AHB1 P2 divider [5:4], PLL_PERIPH0-only + * pre-divider [7:6], APB1 divider [9:8]. + */ +/* vendor: ahb1_parents, with pll_periphahb0 folded into the prediv */ +static const char * const ahb1_parents[] = { "osc32k", "osc24M", + "axi", "pll-periph0" }; +static const struct ccu_mux_var_prediv ahb1_predivs[] = { + { .index = 3, .shift = 6, .width = 2 }, +}; + +static struct ccu_div ahb1_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), + + .mux = { + .shift = 12, + .width = 2, + + .var_predivs = ahb1_predivs, + .n_var_predivs = ARRAY_SIZE(ahb1_predivs), + }, + + .common = { + .reg = 0x054, + .features = CCU_FEATURE_VARIABLE_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("ahb1", + ahb1_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct clk_div_table apb1_div_table[] = { + { .val = 0, .div = 2 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 8 }, + { /* Sentinel */ }, +}; + +static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", + 0x054, 8, 2, apb1_div_table, 0); + +/* + * APB2_CFG @ 0x058 -- M[4:0] P[17:16] mux[25:24]. The divider matches the + * H3, but mux index 2 selects PLL_24M here rather than PLL_PERIPH0_2X. + */ +/* vendor: apb2_parents */ +static const char * const apb2_parents[] = { "osc32k", "osc24M", + "pll-24m", "pll-periph0-2x" }; +static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, + 0, 5, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + 0); + +/* vendor: periphx2_parents */ +static const char * const mod0_parents[] = { "osc24M", "pll-periph0-2x", + "pll-periph1-2x" }; +/* vendor: de_parents */ +static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" }; +/* vendor: tcon0_parents */ +static const char * const tcon0_parents[] = { "pll-video0", "pll-video1" }; +/* vendor: mbus_parents */ +static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", + "pll-ddr0", "pll-ddr1" }; +/* vendor: sdram_parents */ +static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1", + "pll-periph0-2x" }; + +/* NAND_CFG @ 0x080 -- M[3:0] P[17:16] mux[25:24] gate 31 */ +static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_parents, 0x080, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +/* + * SD{0..3}_CFG @ 0x088/0x08c/0x090/0x094 -- same layout as NAND. + * + * The four controllers are not the same IP. The vendor device tree calls + * mmc0 and mmc1 "sunxi-mmc-v4p1x" and mmc3 "sunxi-mmc-v4p5x" (mmc2 is a + * different block again). The v4p1x pair run in the old timing mode: no + * internal halving, so no post-divider, and they need the sample and output + * phase clocks. mmc2 and mmc3 use the new timing mode like the A64, where + * the module clock is internally halved -- hence the post-divider of two. + */ +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_parents, 0x088, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0", 0x088, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0", 0x088, 8, 3, 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_parents, 0x08c, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1", 0x08c, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1", 0x08c, 8, 3, 0); +static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mod0_parents, + 0x090, 0, 4, 16, 2, 24, 2, + BIT(31), 2, 0); +static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc3_clk, "mmc3", mod0_parents, + 0x094, 0, 4, 16, 2, 24, 2, + BIT(31), 2, 0); + +/* SPI{0..2}_CFG @ 0x0a0/0x0a4/0x0a8 -- same layout as NAND. */ +static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_parents, 0x0a0, + 0, 4, 16, 2, 24, 2, BIT(31), 0); +static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_parents, 0x0a4, + 0, 4, 16, 2, 24, 2, BIT(31), 0); +static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_parents, 0x0a8, + 0, 4, 16, 2, 24, 2, BIT(31), 0); + +/* DRAM_CFG @ 0x0f4 -- M[1:0] mux[21:20] gate 31 */ +static SUNXI_CCU_M_WITH_MUX_GATE(dram_clk, "dram", dram_parents, 0x0f4, + 0, 2, /* M */ + 20, 2, /* mux */ + BIT(31), /* gate */ + CLK_IS_CRITICAL); + +/* DE_CFG @ 0x104, EE_CFG @ 0x108, EDMA_CFG @ 0x10c -- M[3:0] mux[26:24] gate 31 */ +static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 0x104, + 0, 4, 24, 3, BIT(31), CLK_SET_RATE_PARENT); +static SUNXI_CCU_M_WITH_MUX_GATE(ee_clk, "ee", de_parents, 0x108, + 0, 4, 24, 3, BIT(31), CLK_SET_RATE_PARENT); +static SUNXI_CCU_M_WITH_MUX_GATE(edma_clk, "edma", de_parents, 0x10c, + 0, 4, 24, 3, BIT(31), CLK_SET_RATE_PARENT); + +/* TCON_CFG @ 0x118 -- mux[26:24] gate 31, no divider */ +static SUNXI_CCU_MUX_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents, 0x118, + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +/* MBUS_CFG @ 0x15c -- M[2:0] mux[25:24] gate 31 */ +static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x15c, + 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); + +static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", + 0x068, BIT(8), 0); +static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1", + 0x060, BIT(13), 0); +static SUNXI_CCU_GATE(bus_sdmmc0_bus_clk, "bus-sdmmc0-bus", "ahb1", + 0x060, BIT(8), 0); +static SUNXI_CCU_GATE(bus_sdmmc1_bus_clk, "bus-sdmmc1-bus", "ahb1", + 0x060, BIT(9), 0); +static SUNXI_CCU_GATE(bus_sdmmc2_bus_clk, "bus-sdmmc2-bus", "ahb1", + 0x060, BIT(10), 0); +static SUNXI_CCU_GATE(bus_sdmmc3_bus_clk, "bus-sdmmc3-bus", "ahb1", + 0x060, BIT(11), 0); +static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", + 0x060, BIT(20), 0); +static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1", + 0x060, BIT(21), 0); +static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb1", + 0x060, BIT(22), 0); +static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", + 0x068, BIT(12), 0); +static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", + 0x068, BIT(13), 0); +static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", + 0x068, BIT(1), 0); +static SUNXI_CCU_GATE(bus_dsd_clk, "bus-dsd", "apb1", + 0x068, BIT(2), 0); +static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", + 0x068, BIT(3), 0); +static SUNXI_CCU_GATE(bus_usbohci0_clk, "bus-usbohci0", "ahb1", + 0x060, BIT(29), 0); +static SUNXI_CCU_GATE(bus_usbehci0_clk, "bus-usbehci0", "ahb1", + 0x060, BIT(26), 0); +static SUNXI_CCU_GATE(bus_usbotg_clk, "bus-usbotg", "ahb1", + 0x060, BIT(24), 0); +static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1", + 0x064, BIT(12), 0); +static SUNXI_CCU_GATE(bus_ee_clk, "bus-ee", "ahb1", + 0x064, BIT(13), 0); +static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1", + 0x064, BIT(4), 0); +static SUNXI_CCU_GATE(bus_csi_s_clk, "bus-csi-s", "ahb1", + 0x064, BIT(8), 0); +static SUNXI_CCU_GATE(bus_csi_m_clk, "bus-csi-m", "ahb1", + 0x064, BIT(8), 0); +static SUNXI_CCU_GATE(bus_csi_misc_clk, "bus-csi-misc", "ahb1", + 0x064, BIT(8), 0); +static SUNXI_CCU_GATE(bus_adda_clk, "bus-adda", "apb1", + 0x068, BIT(0), 0); +static SUNXI_CCU_GATE(bus_sdram_clk, "bus-sdram", "ahb1", + 0x060, BIT(14), 0); +static SUNXI_CCU_GATE(bus_psram_clk, "bus-psram", "ahb1", + 0x060, BIT(15), 0); +static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", + 0x060, BIT(6), 0); +static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", + 0x06c, BIT(16), 0); +static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", + 0x06c, BIT(17), 0); +static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", + 0x06c, BIT(18), 0); +static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", + 0x06c, BIT(19), 0); +static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", + 0x06c, BIT(20), 0); +static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2", + 0x06c, BIT(21), 0); +static SUNXI_CCU_GATE(bus_twi0_clk, "bus-twi0", "apb2", + 0x06c, BIT(0), 0); +static SUNXI_CCU_GATE(bus_twi1_clk, "bus-twi1", "apb2", + 0x06c, BIT(1), 0); +static SUNXI_CCU_GATE(bus_twi2_clk, "bus-twi2", "apb2", + 0x06c, BIT(2), 0); +static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", + 0x068, BIT(5), 0); +static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb1", + 0x068, BIT(10), 0); +static SUNXI_CCU_GATE(bus_keyadc_clk, "bus-keyadc", "apb1", + 0x068, BIT(9), 0); +/* losc_out: reg LOSC_OUT_GATE=0x1c20460 lies outside the CCU window; belongs to another block */ + +static const struct ccu_reset_map sun8i_b288_ccu_resets[] = { + [RST_BUS_THS] = { 0x2d0, BIT(8) }, + [RST_BUS_NAND] = { 0x2c0, BIT(13) }, + [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, + [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, + [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, + [RST_BUS_MMC3] = { 0x2c0, BIT(11) }, + [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, + [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, + [RST_BUS_SPI2] = { 0x2c0, BIT(22) }, + [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, + [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, + [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, + [RST_BUS_DSD] = { 0x2d0, BIT(2) }, + [RST_BUS_DMIC] = { 0x2d0, BIT(3) }, + [RST_USBPHY0] = { 0x0cc, BIT(0) }, + [RST_BUS_OHCI0] = { 0x2c0, BIT(29) }, + [RST_BUS_EHCI0] = { 0x2c0, BIT(26) }, + [RST_BUS_OTG] = { 0x2c0, BIT(24) }, + [RST_BUS_DE] = { 0x2c4, BIT(12) }, + [RST_BUS_EE] = { 0x2c4, BIT(13) }, + [RST_BUS_TCON0] = { 0x2c4, BIT(4) }, + [RST_BUS_CSI] = { 0x2c4, BIT(8) }, + [RST_BUS_ADDA] = { 0x2d0, BIT(0) }, + [RST_BUS_WLAN] = { 0x2c4, BIT(1) }, + [RST_MBUS] = { 0x0fc, BIT(31) }, + [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, + [RST_BUS_PSRAM] = { 0x2c0, BIT(15) }, + [RST_BUS_DMA] = { 0x2c0, BIT(6) }, + [RST_BUS_UART0] = { 0x2d8, BIT(16) }, + [RST_BUS_UART1] = { 0x2d8, BIT(17) }, + [RST_BUS_UART2] = { 0x2d8, BIT(18) }, + [RST_BUS_UART3] = { 0x2d8, BIT(19) }, + [RST_BUS_UART4] = { 0x2d8, BIT(20) }, + [RST_BUS_UART5] = { 0x2d8, BIT(21) }, + [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, + [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, + [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, + [RST_BUS_GPADC] = { 0x2d0, BIT(10) }, + [RST_BUS_KEYADC] = { 0x2d0, BIT(9) }, +}; + +static struct ccu_common *sun8i_b288_ccu_clks[] = { + &pll_cpux_clk.common, + &pll_audio_base_clk.common, + &pll_video0_clk.common, + &pll_ddr0_clk.common, + &pll_periph0_clk.common, + &pll_video1_clk.common, + &pll_24m_clk.common, + &pll_periph1_clk.common, + &pll_de_clk.common, + &pll_ddr1_clk.common, + &cpux_clk.common, + &axi_clk.common, + &cpuapb_clk.common, + &ahb1_clk.common, + &apb1_clk.common, + &apb2_clk.common, + &nand_clk.common, + &mmc0_clk.common, + &mmc0_sample_clk.common, + &mmc0_output_clk.common, + &mmc1_clk.common, + &mmc1_sample_clk.common, + &mmc1_output_clk.common, + &mmc2_clk.common, + &mmc3_clk.common, + &spi0_clk.common, + &spi1_clk.common, + &spi2_clk.common, + &dram_clk.common, + &de_clk.common, + &ee_clk.common, + &edma_clk.common, + &tcon0_clk.common, + &mbus_clk.common, + &bus_ths_clk.common, + &bus_nand_clk.common, + &bus_sdmmc0_bus_clk.common, + &bus_sdmmc1_bus_clk.common, + &bus_sdmmc2_bus_clk.common, + &bus_sdmmc3_bus_clk.common, + &bus_spi0_clk.common, + &bus_spi1_clk.common, + &bus_spi2_clk.common, + &bus_i2s0_clk.common, + &bus_i2s1_clk.common, + &bus_spdif_clk.common, + &bus_dsd_clk.common, + &bus_dmic_clk.common, + &bus_usbohci0_clk.common, + &bus_usbehci0_clk.common, + &bus_usbotg_clk.common, + &bus_de_clk.common, + &bus_ee_clk.common, + &bus_tcon0_clk.common, + &bus_csi_s_clk.common, + &bus_csi_m_clk.common, + &bus_csi_misc_clk.common, + &bus_adda_clk.common, + &bus_sdram_clk.common, + &bus_psram_clk.common, + &bus_dma_clk.common, + &bus_uart0_clk.common, + &bus_uart1_clk.common, + &bus_uart2_clk.common, + &bus_uart3_clk.common, + &bus_uart4_clk.common, + &bus_uart5_clk.common, + &bus_twi0_clk.common, + &bus_twi1_clk.common, + &bus_twi2_clk.common, + &bus_pio_clk.common, + &bus_gpadc_clk.common, + &bus_keyadc_clk.common, +}; + +static struct clk_hw_onecell_data sun8i_b288_hw_clks = { + .hws = { + [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, + [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, + [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, + [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, + [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, + [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, + [CLK_PLL_24M] = &pll_24m_clk.common.hw, + [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, + [CLK_PLL_DE] = &pll_de_clk.common.hw, + [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, + [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, + [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw, + [CLK_CPUX] = &cpux_clk.common.hw, + [CLK_AXI] = &axi_clk.common.hw, + [CLK_CPUAPB] = &cpuapb_clk.common.hw, + [CLK_AHB1] = &ahb1_clk.common.hw, + [CLK_APB1] = &apb1_clk.common.hw, + [CLK_APB2] = &apb2_clk.common.hw, + [CLK_NAND] = &nand_clk.common.hw, + [CLK_MMC0] = &mmc0_clk.common.hw, + [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, + [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, + [CLK_MMC1] = &mmc1_clk.common.hw, + [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, + [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, + [CLK_MMC2] = &mmc2_clk.common.hw, + [CLK_MMC3] = &mmc3_clk.common.hw, + [CLK_SPI0] = &spi0_clk.common.hw, + [CLK_SPI1] = &spi1_clk.common.hw, + [CLK_SPI2] = &spi2_clk.common.hw, + [CLK_DRAM] = &dram_clk.common.hw, + [CLK_DE] = &de_clk.common.hw, + [CLK_EE] = &ee_clk.common.hw, + [CLK_EDMA] = &edma_clk.common.hw, + [CLK_TCON0] = &tcon0_clk.common.hw, + [CLK_MBUS] = &mbus_clk.common.hw, + [CLK_BUS_THS] = &bus_ths_clk.common.hw, + [CLK_BUS_NAND] = &bus_nand_clk.common.hw, + [CLK_BUS_SDMMC0_BUS] = &bus_sdmmc0_bus_clk.common.hw, + [CLK_BUS_SDMMC1_BUS] = &bus_sdmmc1_bus_clk.common.hw, + [CLK_BUS_SDMMC2_BUS] = &bus_sdmmc2_bus_clk.common.hw, + [CLK_BUS_SDMMC3_BUS] = &bus_sdmmc3_bus_clk.common.hw, + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, + [CLK_BUS_SPI2] = &bus_spi2_clk.common.hw, + [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, + [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, + [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, + [CLK_BUS_DSD] = &bus_dsd_clk.common.hw, + [CLK_BUS_DMIC] = &bus_dmic_clk.common.hw, + [CLK_BUS_USBOHCI0] = &bus_usbohci0_clk.common.hw, + [CLK_BUS_USBEHCI0] = &bus_usbehci0_clk.common.hw, + [CLK_BUS_USBOTG] = &bus_usbotg_clk.common.hw, + [CLK_BUS_DE] = &bus_de_clk.common.hw, + [CLK_BUS_EE] = &bus_ee_clk.common.hw, + [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw, + [CLK_BUS_CSI_S] = &bus_csi_s_clk.common.hw, + [CLK_BUS_CSI_M] = &bus_csi_m_clk.common.hw, + [CLK_BUS_CSI_MISC] = &bus_csi_misc_clk.common.hw, + [CLK_BUS_ADDA] = &bus_adda_clk.common.hw, + [CLK_BUS_SDRAM] = &bus_sdram_clk.common.hw, + [CLK_BUS_PSRAM] = &bus_psram_clk.common.hw, + [CLK_BUS_DMA] = &bus_dma_clk.common.hw, + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, + [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, + [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, + [CLK_BUS_UART5] = &bus_uart5_clk.common.hw, + [CLK_BUS_TWI0] = &bus_twi0_clk.common.hw, + [CLK_BUS_TWI1] = &bus_twi1_clk.common.hw, + [CLK_BUS_TWI2] = &bus_twi2_clk.common.hw, + [CLK_BUS_PIO] = &bus_pio_clk.common.hw, + [CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw, + [CLK_BUS_KEYADC] = &bus_keyadc_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static const struct sunxi_ccu_desc sun8i_b288_ccu_desc = { + .ccu_clks = sun8i_b288_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_b288_ccu_clks), + + .hw_clks = &sun8i_b288_hw_clks, + + .resets = sun8i_b288_ccu_resets, + .num_resets = ARRAY_SIZE(sun8i_b288_ccu_resets), + +}; + +static int sun8i_b288_ccu_probe(struct platform_device *pdev) +{ + void __iomem *reg; + + reg = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_b288_ccu_desc); +} + +static const struct of_device_id sun8i_b288_ccu_ids[] = { + { .compatible = "allwinner,sun8i-b288-ccu" }, + { } +}; +MODULE_DEVICE_TABLE(of, sun8i_b288_ccu_ids); + +static struct platform_driver sun8i_b288_ccu_driver = { + .probe = sun8i_b288_ccu_probe, + .driver = { + .name = "sun8i-b288-ccu", + .suppress_bind_attrs = true, + .of_match_table = sun8i_b288_ccu_ids, + }, +}; +module_platform_driver(sun8i_b288_ccu_driver); + +MODULE_IMPORT_NS("SUNXI_CCU"); +MODULE_DESCRIPTION("Allwinner B288 (sun8iw10p1) CCU driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-b288.h b/drivers/clk/sunxi-ng/ccu-sun8i-b288.h new file mode 100644 index 000000000000..805df2d6d99c --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun8i-b288.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _CCU_SUN8I_B288_H_ +#define _CCU_SUN8I_B288_H_ + +#include +#include + +#define CLK_NUMBER (CLK_MMC1_OUTPUT + 1) + +#endif /* _CCU_SUN8I_B288_H_ */ From patchwork Wed Sep 23 20:16:53 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pablo Mazzini X-Patchwork-Id: 3454 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 5DCC11C0E12 for ; Wed, 23 Sep 2026 22:38:51 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=gmail.com; spf=pass (sender IP is 172.234.253.10) smtp.mailfrom=linux-sunxi+bounces-26208-noreply=patchwork.local@lists.linux.dev smtp.helo=sea.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.234.253.10 as permitted sender) client-ip=172.234.253.10; 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[78.137.176.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae5c8a44sm177243566b.20.2026.09.23.13.22.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 13:22:57 -0700 (PDT) From: Pablo Mazzini To: Chen-Yu Tsai , Conor Dooley , Jernej Skrabec , Krzysztof Kozlowski , Linus Walleij , Rob Herring , Samuel Holland Cc: Pablo Mazzini , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v1 03/11] dt-bindings: pinctrl: add Allwinner B288 pin controller Date: Wed, 23 Sep 2026 21:16:53 +0100 Message-ID: <20260923201701.43391-3-pmazzini@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260923201701.43391-1-pmazzini@gmail.com> References: <20260923201701.43391-1-pmazzini@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= One controller at 0x01c20800 with four external interrupt banks. Signed-off-by: Pablo Mazzini --- .../pinctrl/allwinner,sun8i-b288-pinctrl.yaml | 108 ++++++++++++++++++ 1 file changed, 108 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml new file mode 100644 index 000000000000..806da97ab708 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun8i-b288-pinctrl.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/allwinner,sun8i-b288-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner B288 Pin Controller + +maintainers: + - Chen-Yu Tsai + - Jernej Skrabec + +properties: + compatible: + const: allwinner,sun8i-b288-pinctrl + + reg: + maxItems: 1 + + interrupts: + description: + One interrupt per bank of external interrupt capable pins. + maxItems: 4 + + clocks: + items: + - description: Bus Clock + - description: High Frequency Oscillator + - description: Low Frequency Oscillator + + clock-names: + items: + - const: apb + - const: hosc + - const: losc + + gpio-controller: true + interrupt-controller: true + gpio-line-names: true + + "#gpio-cells": + const: 3 + + "#interrupt-cells": + const: 3 + +patternProperties: + "-pins$": + type: object + $ref: /schemas/pinctrl/pincfg-node.yaml# + additionalProperties: false + + properties: + pins: true + function: true + bias-pull-up: true + bias-pull-down: true + bias-disable: true + drive-strength: + enum: [10, 20, 30, 40] + + required: + - pins + - function + + "^vcc-p[bcdfg]-supply$": + description: + Power supplies for pin banks. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - gpio-controller + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + pio: pinctrl@1c20800 { + compatible = "allwinner,sun8i-b288-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = , + , + , + ; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; + function = "sdc0"; + drive-strength = <30>; + bias-pull-up; + }; + }; From patchwork Wed Sep 23 20:16:54 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pablo Mazzini X-Patchwork-Id: 3451 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sto.lore.kernel.org (sto.lore.kernel.org [172.232.135.74]) by mxe881.netcup.net (Postfix) with ESMTPS id 8A2571C0146 for ; Wed, 23 Sep 2026 22:30:12 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=gmail.com; spf=pass (sender IP is 172.232.135.74) smtp.mailfrom=linux-sunxi+bounces-26209-noreply=patchwork.local@lists.linux.dev smtp.helo=sto.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.232.135.74 as permitted sender) client-ip=172.232.135.74; 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[78.137.176.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae5c8a44sm177243566b.20.2026.09.23.13.22.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 13:22:59 -0700 (PDT) From: Pablo Mazzini To: Chen-Yu Tsai , Jernej Skrabec , Linus Walleij , Samuel Holland Cc: Pablo Mazzini , linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v1 04/11] pinctrl: sunxi: add Allwinner B288 pin controller driver Date: Wed, 23 Sep 2026 21:16:54 +0100 Message-ID: <20260923201701.43391-4-pmazzini@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260923201701.43391-1-pmazzini@gmail.com> References: <20260923201701.43391-1-pmazzini@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [5.84 / 15.00]; RBL_SENDERSCORE(2.00)[172.232.135.74:from]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; DMARC_POLICY_SOFTFAIL(1.00)[gmail.com : SPF not aligned (relaxed), No valid DKIM,none]; R_MISSING_CHARSET(0.50)[]; MAILLIST(-0.15)[generic]; MIME_GOOD(-0.10)[text/plain]; BAD_REP_POLICIES(0.10)[]; HAS_LIST_UNSUB(-0.01)[]; FROM_HAS_DN(0.00)[]; PRECEDENCE_BULK(0.00)[]; TAGGED_RCPT(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FREEMAIL_CC(0.00)[gmail.com,lists.infradead.org,vger.kernel.org,lists.linux.dev]; DBL_BLOCKED_OPENRESOLVER(0.00)[sto.lore.kernel.org:rdns,sto.lore.kernel.org:helo,csie.org:email]; FORGED_SENDER_MAILLIST(0.00)[]; RCVD_COUNT_FIVE(0.00)[6]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; TAGGED_FROM(0.00)[bounces-26209-noreply=patchwork.local]; FREEMAIL_FROM(0.00)[gmail.com]; R_SPF_ALLOW(0.00)[+ip4:172.232.135.74]; TO_DN_SOME(0.00)[]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[100.90.174.1:received,74.125.228.140:received,78.137.176.146:received]; FROM_NEQ_ENVFROM(0.00)[pmazzini@gmail.com,linux-sunxi@lists.linux.dev]; RCPT_COUNT_SEVEN(0.00)[9]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; ASN(0.00)[asn:63949, ipnet:172.232.128.0/19, country:SG]; FREEMAIL_TO(0.00)[kernel.org,gmail.com,sholland.org]; RCVD_TLS_LAST(0.00)[]; MIME_TRACE(0.00)[0:+]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[172.232.135.74:from] X-Rspamd-Queue-Id: 8A2571C0146 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= 78 pins across ports B, C, D, F and G. PH0 is BSP FPGA-only and omitted. Signed-off-by: Pablo Mazzini --- drivers/pinctrl/sunxi/Kconfig | 10 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c | 623 +++++++++++++++++++++ 3 files changed, 634 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index dc62eba96348..a08186133090 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -56,6 +56,16 @@ config PINCTRL_SUN8I_A23_R default MACH_SUN8I select PINCTRL_SUNXI +config PINCTRL_SUN8I_B288 + bool "Support for the Allwinner B288 PIO" + default MACH_SUN8I + select PINCTRL_SUNXI + help + Say Y here to enable pin controller and GPIO support for the + Allwinner B288 (sun8iw10p1) SoC, as used in e-book readers such + as the PocketBook Verse. This covers ports B, C, D, F and G, + including the four banks of external interrupt capable pins. + config PINCTRL_SUN8I_H3 bool "Support for the Allwinner H3 PIO" default MACH_SUN8I diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 951b3f1e4b4f..5129c0f19f3e 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_SUN50I_A100) += pinctrl-sun50i-a100.o obj-$(CONFIG_PINCTRL_SUN50I_A100_R) += pinctrl-sun50i-a100-r.o obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o +obj-$(CONFIG_PINCTRL_SUN8I_B288) += pinctrl-sun8i-b288.o obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c new file mode 100644 index 000000000000..ffd7eef68d19 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-b288.c @@ -0,0 +1,623 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Allwinner B288 (sun8iw10p1) SoC pinctrl driver. + * + * Derived from Allwinner's BSP driver pinctrl-sun8iw10p1.c, which is: + * Copyright (C) 2014 Jackie Hwang + * + * Based on pinctrl-sun8i-a23.c, which is: + * Copyright (C) 2014 Chen-Yu Tsai + * Copyright (C) 2014 Maxime Ripard + */ + +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun8i_b288_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), + SUNXI_FUNCTION(0x3, "jtag0"), + SUNXI_FUNCTION(0x5, "vdevice"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), + SUNXI_FUNCTION(0x3, "jtag0"), + SUNXI_FUNCTION(0x4, "spdif0"), + SUNXI_FUNCTION(0x5, "vdevice"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), + SUNXI_FUNCTION(0x3, "jtag0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), + SUNXI_FUNCTION(0x3, "jtag0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), + SUNXI_FUNCTION(0x3, "pwm0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), + SUNXI_FUNCTION(0x3, "pwm1"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "twi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "twi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), + SUNXI_FUNCTION(0x3, "uart4"), + SUNXI_FUNCTION(0x4, "pwm2"), + SUNXI_FUNCTION(0x5, "wifi_uart0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), + SUNXI_FUNCTION(0x3, "uart4"), + SUNXI_FUNCTION(0x4, "pwm3"), + SUNXI_FUNCTION(0x5, "wifi_uart0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), + SUNXI_FUNCTION(0x4, "pwm4"), + SUNXI_FUNCTION(0x5, "uart3"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), + SUNXI_FUNCTION(0x4, "pwm5"), + SUNXI_FUNCTION(0x5, "uart3"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), + SUNXI_FUNCTION(0x3, "ac0"), + SUNXI_FUNCTION(0x4, "twi1"), + SUNXI_FUNCTION(0x5, "uart3"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s1"), + SUNXI_FUNCTION(0x3, "ac0"), + SUNXI_FUNCTION(0x4, "twi1"), + SUNXI_FUNCTION(0x5, "uart3"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), + /*Hole*/ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x4, "spi0"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x4, "spi0"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x4, "spi0"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x4, "spi0"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x4, "uart1"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x4, "uart1"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x4, "uart1"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x4, "uart1"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x4, "uart1"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x4, "uart1"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x4, "uart1"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x4, "uart1"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), + SUNXI_FUNCTION(0x3, "sdc2"), + SUNXI_FUNCTION(0x5, "sdc3"), + SUNXI_FUNCTION(0x7, "io_disabled")), + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "uart1"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "uart1"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "uart5"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "uart5"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "uart5"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "uart5"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "uart1"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "uart1"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 17)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 18)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 19)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 20)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 21)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 22)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x4, "csi0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 23)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "spi2"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 24)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "spi2"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 25)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "spi2"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 26)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), + SUNXI_FUNCTION(0x3, "spi2"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 27)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 28)), + + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sdc0"), + SUNXI_FUNCTION(0x4, "jtag0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sdc0"), + SUNXI_FUNCTION(0x4, "jtag0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sdc0"), + SUNXI_FUNCTION(0x4, "uart0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sdc0"), + SUNXI_FUNCTION(0x4, "jtag0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sdc0"), + SUNXI_FUNCTION(0x4, "uart0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "sdc0"), + SUNXI_FUNCTION(0x4, "jtag0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), + + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm6"), + SUNXI_FUNCTION(0x3, "dmic0"), + SUNXI_FUNCTION(0x4, "spi1"), + SUNXI_FUNCTION(0x5, "sdc1"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm7"), + SUNXI_FUNCTION(0x3, "dmic0"), + SUNXI_FUNCTION(0x4, "spi1"), + SUNXI_FUNCTION(0x5, "sdc1"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "twi1"), + SUNXI_FUNCTION(0x3, "dmic0"), + SUNXI_FUNCTION(0x4, "spi1"), + SUNXI_FUNCTION(0x5, "sdc1"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "twi1"), + SUNXI_FUNCTION(0x3, "dmic0"), + SUNXI_FUNCTION(0x4, "spi1"), + SUNXI_FUNCTION(0x5, "sdc1"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "twi2"), + SUNXI_FUNCTION(0x3, "dmic0"), + SUNXI_FUNCTION(0x4, "spi1"), + SUNXI_FUNCTION(0x5, "sdc1"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "twi2"), + SUNXI_FUNCTION(0x4, "ac0"), + SUNXI_FUNCTION(0x5, "sdc1"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), + SUNXI_FUNCTION(0x3, "dsd0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), + SUNXI_FUNCTION(0x3, "dsd0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), + SUNXI_FUNCTION(0x3, "dsd0"), + SUNXI_FUNCTION(0x4, "bist_result0"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s0"), + SUNXI_FUNCTION(0x3, "dsd0"), + SUNXI_FUNCTION(0x4, "bist_result1"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spdif0"), + SUNXI_FUNCTION(0x4, "pll_lock_dbg"), + SUNXI_FUNCTION(0x7, "io_disabled"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), + +}; + +static const struct sunxi_pinctrl_desc sun8i_b288_pinctrl_data = { + .pins = sun8i_b288_pins, + .npins = ARRAY_SIZE(sun8i_b288_pins), + .irq_banks = 4, +}; + +static int sun8i_b288_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun8i_b288_pinctrl_data); +} + +static const struct of_device_id sun8i_b288_pinctrl_match[] = { + { .compatible = "allwinner,sun8i-b288-pinctrl", }, + {} +}; + +static struct platform_driver sun8i_b288_pinctrl_driver = { + .probe = sun8i_b288_pinctrl_probe, + .driver = { + .name = "sun8i-b288-pinctrl", + .of_match_table = sun8i_b288_pinctrl_match, + }, +}; +builtin_platform_driver(sun8i_b288_pinctrl_driver); From patchwork Wed Sep 23 20:16:55 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pablo Mazzini X-Patchwork-Id: 3464 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 6FAFC1C2AD5 for ; Wed, 23 Sep 2026 22:52:16 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=gmail.com; spf=pass (sender IP is 172.234.253.10) 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[78.137.176.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae5c8a44sm177243566b.20.2026.09.23.13.23.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 13:23:02 -0700 (PDT) From: Pablo Mazzini To: Alexandre Belloni , Chen-Yu Tsai , Conor Dooley , Jernej Skrabec , Krzysztof Kozlowski , Maxime Ripard , Rob Herring , Samuel Holland Cc: Pablo Mazzini , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v1 05/11] dt-bindings: rtc: sun6i-a31: add Allwinner B288 Date: Wed, 23 Sep 2026 21:16:55 +0100 Message-ID: <20260923201701.43391-5-pmazzini@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260923201701.43391-1-pmazzini@gmail.com> References: <20260923201701.43391-1-pmazzini@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The B288 RTC wires one alarm interrupt, not two. Signed-off-by: Pablo Mazzini --- .../devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml index f2b91186ed37..1699e3576b91 100644 --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml @@ -19,6 +19,7 @@ properties: - enum: - allwinner,sun6i-a31-rtc - allwinner,sun8i-a23-rtc + - allwinner,sun8i-b288-rtc - allwinner,sun8i-h3-rtc - allwinner,sun8i-r40-rtc - allwinner,sun8i-v3-rtc @@ -162,6 +163,7 @@ allOf: compatible: contains: enum: + - allwinner,sun8i-b288-rtc - allwinner,sun8i-r40-rtc - allwinner,sun50i-h616-rtc - allwinner,sun50i-r329-rtc From patchwork Wed Sep 23 20:16:56 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pablo Mazzini X-Patchwork-Id: 3455 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 1047A1C013B for ; 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[78.137.176.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae5c8a44sm177243566b.20.2026.09.23.13.23.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 13:23:04 -0700 (PDT) From: Pablo Mazzini To: Alexandre Belloni , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Pablo Mazzini , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v1 06/11] rtc: sun6i: add Allwinner B288 compatible Date: Wed, 23 Sep 2026 21:16:56 +0100 Message-ID: <20260923201701.43391-6-pmazzini@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260923201701.43391-1-pmazzini@gmail.com> References: <20260923201701.43391-1-pmazzini@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The driver only uses one alarm interrupt, so no functional change. Signed-off-by: Pablo Mazzini --- drivers/rtc/rtc-sun6i.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c index 7fc60880e409..cd6ac5bb20cd 100644 --- a/drivers/rtc/rtc-sun6i.c +++ b/drivers/rtc/rtc-sun6i.c @@ -859,6 +859,7 @@ static int sun6i_rtc_probe(struct platform_device *pdev) static const struct of_device_id sun6i_rtc_dt_ids[] = { { .compatible = "allwinner,sun6i-a31-rtc" }, { .compatible = "allwinner,sun8i-a23-rtc" }, + { .compatible = "allwinner,sun8i-b288-rtc" }, { .compatible = "allwinner,sun8i-h3-rtc" }, { .compatible = "allwinner,sun8i-r40-rtc" }, { .compatible = "allwinner,sun8i-v3-rtc" }, From patchwork Wed Sep 23 20:16:58 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pablo Mazzini X-Patchwork-Id: 3457 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 82E7A1C2AD3 for ; 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[78.137.176.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae5c8a44sm177243566b.20.2026.09.23.13.23.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 13:23:09 -0700 (PDT) From: Pablo Mazzini To: Chen-Yu Tsai , Conor Dooley , Jernej Skrabec , Krzysztof Kozlowski , Maxime Ripard , Rob Herring , Samuel Holland , Ulf Hansson Cc: Pablo Mazzini , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v1 08/11] dt-bindings: mmc: sun4i-a10-mmc: add Allwinner B288 Date: Wed, 23 Sep 2026 21:16:58 +0100 Message-ID: <20260923201701.43391-8-pmazzini@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260923201701.43391-1-pmazzini@gmail.com> References: <20260923201701.43391-1-pmazzini@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= Add the MMC and eMMC compatibles. Signed-off-by: Pablo Mazzini --- .../devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml index 9e9610bb1eda..c2ec7151dccf 100644 --- a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml +++ b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml @@ -32,10 +32,12 @@ properties: - items: - enum: - allwinner,sun8i-a83t-mmc + - allwinner,sun8i-b288-mmc - allwinner,suniv-f1c100s-mmc - const: allwinner,sun7i-a20-mmc - items: - enum: + - allwinner,sun8i-b288-emmc - allwinner,sun8i-r40-emmc - allwinner,sun50i-h5-emmc - allwinner,sun50i-h6-emmc From patchwork Wed Sep 23 20:16:59 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pablo Mazzini X-Patchwork-Id: 3456 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id 8B5F21C013B for ; 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Signed-off-by: Pablo Mazzini --- .../interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml index bb9273ec2457..179e7842bf46 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml @@ -29,6 +29,7 @@ properties: - const: allwinner,sun55i-a523-nmi - items: - enum: + - allwinner,sun8i-b288-nmi - allwinner,sun8i-v3s-nmi - allwinner,sun50i-a100-nmi - allwinner,sun50i-h616-nmi From patchwork Wed Sep 23 20:17:00 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pablo Mazzini X-Patchwork-Id: 3452 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10]) by mxe881.netcup.net (Postfix) with ESMTPS id AF8611C0146 for ; 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[78.137.176.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae5c8a44sm177243566b.20.2026.09.23.13.23.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 13:23:13 -0700 (PDT) From: Pablo Mazzini To: Chen-Yu Tsai , Conor Dooley , Jernej Skrabec , Krzysztof Kozlowski , Maxime Ripard , Rob Herring , Samuel Holland Cc: Pablo Mazzini , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v1 10/11] dt-bindings: arm: sunxi: add PocketBook Verse Date: Wed, 23 Sep 2026 21:17:00 +0100 Message-ID: <20260923201701.43391-10-pmazzini@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260923201701.43391-1-pmazzini@gmail.com> References: <20260923201701.43391-1-pmazzini@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= A 6" e-book reader built around the Allwinner B288. Signed-off-by: Pablo Mazzini Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index f04db28c630a..f66c681d3788 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -811,6 +811,11 @@ properties: - const: pocketbook,614-plus - const: allwinner,sun5i-a13 + - description: PocketBook Verse (PB629) + items: + - const: pocketbook,verse + - const: allwinner,sun8i-b288 + - description: Point of View Protab2-IPS9 items: - const: pov,protab2-ips9 From patchwork Wed Sep 23 20:17:01 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pablo Mazzini X-Patchwork-Id: 3453 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from sto.lore.kernel.org (sto.lore.kernel.org [172.232.135.74]) by mxe881.netcup.net (Postfix) with ESMTPS id 031AB1C0146 for ; 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[78.137.176.146]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2aae5c8a44sm177243566b.20.2026.09.23.13.23.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2026 13:23:15 -0700 (PDT) From: Pablo Mazzini To: Chen-Yu Tsai , Conor Dooley , Jernej Skrabec , Krzysztof Kozlowski , Rob Herring , Russell King , Samuel Holland Cc: Pablo Mazzini , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH v1 11/11] ARM: sunxi: add B288 and the PocketBook Verse board Date: Wed, 23 Sep 2026 21:17:01 +0100 Message-ID: <20260923201701.43391-11-pmazzini@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260923201701.43391-1-pmazzini@gmail.com> References: <20260923201701.43391-1-pmazzini@gmail.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= arm,cpu-registers-not-fw-configured is required: Allwinner's boot0 sets neither CNTFRQ nor CNTVOFF, so the virtual timer storms. Same reason as commit 121b96cd9d7e ("ARM: sun6i: Enable ARM arch timers"). The watchdog interrupt was measured on hardware via GICD_ISPENDR. Signed-off-by: Pablo Mazzini --- arch/arm/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun8i-b288-pocketbook-verse.dts | 122 +++++++ arch/arm/boot/dts/allwinner/sun8i-b288.dtsi | 300 ++++++++++++++++++ arch/arm/mach-sunxi/sunxi.c | 1 + 4 files changed, 424 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-b288-pocketbook-verse.dts create mode 100644 arch/arm/boot/dts/allwinner/sun8i-b288.dtsi diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile index 75b2b6a2f7a6..2dfdc01e4825 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -227,6 +227,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a83t-bananapi-m3.dtb \ sun8i-a83t-cubietruck-plus.dtb \ sun8i-a83t-tbs-a711.dtb \ + sun8i-b288-pocketbook-verse.dtb \ sun8i-h2-plus-bananapi-m2-zero.dtb \ sun8i-h2-plus-libretech-all-h3-cc.dtb \ sun8i-h2-plus-orangepi-r1.dtb \ diff --git a/arch/arm/boot/dts/allwinner/sun8i-b288-pocketbook-verse.dts b/arch/arm/boot/dts/allwinner/sun8i-b288-pocketbook-verse.dts new file mode 100644 index 000000000000..91c89d5a097e --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-b288-pocketbook-verse.dts @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * PocketBook Verse (PB629), an Allwinner B288 based e-reader. + */ + +/dts-v1/; +#include "sun8i-b288.dtsi" + +#include + +/ { + model = "PocketBook Verse"; + compatible = "pocketbook,verse", "allwinner,sun8i-b288"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x20000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_dldo2>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc3 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dldo1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&pio { + vcc-pc-supply = <®_dldo1>; + vcc-pd-supply = <®_dldo1>; + /* + * PC and PD are named in the vendor rail list; PF is not. It is not + * on dldo2: with that rail off, a pull-up on PF6 still reads card + * detect correctly, so the bank has its own supply. dcdc1 is the + * only remaining candidate, carrying vcc-io and vcc-card. Derived + * from the rail naming plus that measurement, not from a schematic. + */ + vcc-pf-supply = <®_dcdc1>; +}; + +&i2c0 { + status = "okay"; + + axp22x: pmic@34 { + compatible = "x-powers,axp221"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp22x.dtsi" + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-io"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1260000>; + regulator-max-microvolt = <1260000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vcc-dram"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pc"; +}; + +®_dldo2 { + /* Powers the microSD slot (slot pin 4), switched per card scan. */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-sdcv"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-b288.dtsi b/arch/arm/boot/dts/allwinner/sun8i-b288.dtsi new file mode 100644 index 000000000000..58668d581368 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-b288.dtsi @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Allwinner B288 (sun8iw10p1) SoC + * + * Addresses and interrupts come from the PocketBook Verse (PB629) vendor + * device tree, cross-checked against the BSP clk-sun8iw10.c. + */ + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + clocks { + osc24M: osc24M-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + arm,cpu-registers-not-fw-configured; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * mmc0 is a v4p1x controller, so it runs in the old timing + * mode and needs the sample and output phase clocks. Do not + * give it the sun50i-a64-mmc fallback: that selects the new + * timing mode, which this block does not implement. + */ + nmi_intc: interrupt-controller@1c000d0 { + compatible = "allwinner,sun8i-b288-nmi", + "allwinner,sun9i-a80-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c000d0 0x0c>; + interrupts = ; + }; + + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun8i-b288-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_SDMMC0_BUS>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", "mmc", "output", "sample"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* SDXC v4.5. The soldered eMMC; shares the PC pads with mmc2. */ + mmc3: mmc@1c12000 { + compatible = "allwinner,sun8i-b288-emmc", + "allwinner,sun50i-a64-emmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ccu CLK_BUS_SDMMC3_BUS>, <&ccu CLK_MMC3>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC3>; + reset-names = "ahb"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* + * mmc2 (0x01c11000) is an SDHCI-style controller, not SDXC, and + * has no upstream binding. It loses the PC pad arbitration to + * mmc3 and is unused here, so it is left undescribed rather than + * given a wrong compatible. + */ + + ccu: clock-controller@1c20000 { + compatible = "allwinner,sun8i-b288-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + rtc: rtc@1c20400 { + compatible = "allwinner,sun8i-b288-rtc"; + reg = <0x01c20400 0x400>; + interrupts = ; + clock-output-names = "osc32k"; + clocks = <&osc32k>; + #clock-cells = <1>; + }; + + pio: pinctrl@1c20800 { + compatible = "allwinner,sun8i-b288-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = , + , + , + ; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + function = "sdc0"; + drive-strength = <30>; + bias-pull-up; + }; + + i2c0_pins: i2c0-pins { + pins = "PB6", "PB7"; + function = "twi0"; + }; + + mmc3_pins: mmc3-pins { + pins = "PC1", "PC4", "PC5", "PC6", + "PC7", "PC8", "PC9", "PC10", + "PC11", "PC12", "PC13", "PC14"; + function = "sdc3"; + drive-strength = <40>; + bias-pull-up; + }; + + uart0_pb_pins: uart0-pb-pins { + pins = "PB4", "PB5"; + function = "uart0"; + }; + }; + + wdt: watchdog@1c20ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = ; + clocks = <&osc24M>; + }; + + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@1c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + uart4: serial@1c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun8i-b288-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_TWI0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun8i-b288-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_TWI1>; + resets = <&ccu RST_BUS_I2C1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun8i-b288-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_TWI2>; + resets = <&ccu RST_BUS_I2C2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; +}; diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index e1b7945aac99..c5b19d0e63f9 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -61,6 +61,7 @@ MACHINE_END static const char * const sun8i_board_dt_compat[] = { "allwinner,sun8i-a23", "allwinner,sun8i-a33", + "allwinner,sun8i-b288", "allwinner,sun8i-h2-plus", "allwinner,sun8i-h3", "allwinner,sun8i-r40",