From patchwork Sat Sep 26 23:21:41 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 3488 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114]) by mxe881.netcup.net (Postfix) with ESMTPS id 0C6981C2F89 for ; Sun, 27 Sep 2026 01:26:41 +0200 (CEST) Authentication-Results: mxe881; dkim=pass header.d=arm.com; spf=pass (sender IP is 172.105.105.114) smtp.mailfrom=linux-sunxi+bounces-26287-noreply=patchwork.local@lists.linux.dev smtp.helo=tor.lore.kernel.org Received-SPF: pass (mxe881: domain of lists.linux.dev designates 172.105.105.114 as permitted sender) client-ip=172.105.105.114; envelope-from=linux-sunxi+bounces-26287-noreply=patchwork.local@lists.linux.dev; helo=tor.lore.kernel.org; Received: from smtp.subspace.kernel.org (conduit.subspace.kernel.org [100.90.174.1]) by tor.lore.kernel.org (Postfix) with ESMTP id 279BF28F2F for ; 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Sat, 26 Sep 2026 16:26:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790465196; bh=W5iZHw/9hbynSVMkDHufc1P8AF2PukWPWeCd4BJBy1A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CqGsx+28/+rPIouDhtlPfUGK+LTE/N5Ngf5iiuR+uTaiPTkCeXrkmQ6AN5VDAOEb5 UYPD346wMwDFLuEDgIoEi1/CKXXZLVmk2vpElrw/OCil08N1jhq57fIKJ66fHw0QTK QlxtmAcS7VAoIiOc3FbLSfqP8jZEcz67LvkWEHEs= From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Per Larsson Subject: [PATCH v2 1/2] arm64: dts: allwinner: a523: add EPHY 25MHz clock fanout pins Date: Sun, 27 Sep 2026 01:21:41 +0200 Message-ID: <20260926232142.5244-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.4 In-Reply-To: <20260926232142.5244-1-andre.przywara@arm.com> References: <20260926232142.5244-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Rspamd-Server: rspamd-worker-8404 X-Spamd-Result: default: False [-0.66 / 15.00]; BAYES_HAM(-5.50)[100.00%]; RBL_SENDERSCORE(2.00)[172.105.105.114:from]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; MAILLIST(-0.15)[generic]; BAD_REP_POLICIES(0.10)[]; MIME_GOOD(-0.10)[text/plain]; HAS_LIST_UNSUB(-0.01)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[tor.lore.kernel.org:rdns,tor.lore.kernel.org:helo,arm.com:email,arm.com:dkim,0.30.132.128:email]; RCVD_COUNT_FIVE(0.00)[6]; FROM_HAS_DN(0.00)[]; TAGGED_RCPT(0.00)[dt]; R_DKIM_ALLOW(0.00)[arm.com:s=foss]; PRECEDENCE_BULK(0.00)[]; FROM_NEQ_ENVFROM(0.00)[andre.przywara@arm.com,linux-sunxi@lists.linux.dev]; ARC_ALLOW(0.00)[subspace.kernel.org:s=arc-20240116:i=1]; TAGGED_FROM(0.00)[bounces-26287-noreply=patchwork.local]; DKIM_TRACE(0.00)[arm.com:+]; DMARC_POLICY_ALLOW(0.00)[arm.com,none]; R_SPF_ALLOW(0.00)[+ip4:172.105.105.114:c]; TO_DN_SOME(0.00)[]; FORGED_SENDER_MAILLIST(0.00)[]; RCPT_COUNT_SEVEN(0.00)[10]; FORGED_RECIPIENTS_MAILLIST(0.00)[]; ASN(0.00)[asn:63949, ipnet:172.105.96.0/20, country:SG]; FREEMAIL_TO(0.00)[kernel.org,gmail.com,sholland.org]; RCVD_TLS_LAST(0.00)[]; MIME_TRACE(0.00)[0:+]; RCVD_VIA_SMTP_AUTH(0.00)[] X-Rspamd-Queue-Id: 0C6981C2F89 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The Allwinner A523 SoC family provides two clock fanout pins, which are backed by gated clocks fixed to 25 MHz, divided down from the main peripheral PLL. Those are meant to clock an Ethernet PHY, and allow to save an external crystal oscillator typically employed for that purpose. Add the pin descriptions of the two pins for those clocks, one is within the RGMII0 pins, the other within the RGMII1 pins, although the clock fanout works completely independently from the two MACs. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index 85ef492ffeae7..ce01fad22b469 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -147,6 +147,20 @@ pio: pinctrl@2000000 { interrupt-controller; #interrupt-cells = <3>; + /omit-if-no-ref/ + ephy0_25m_pin: ephy0-25m-pin { + pins = "PH13"; + allwinner,pinmux = <5>; + function = "ephy_25m"; + }; + + /omit-if-no-ref/ + ephy1_25m_pin: ephy1-25m-pin { + pins = "PJ10"; + allwinner,pinmux = <5>; + function = "ephy_25m"; + }; + /omit-if-no-ref/ i2s2_pi_pins: i2s2-pi-pins { pins = "PI2", "PI3", "PI4", "PI5"; From patchwork Sat Sep 26 23:21:42 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 3487 Return-Path: X-Original-To: noreply@patchwork.local Delivered-To: noreply@patchwork.local Received: from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114]) by mxe881.netcup.net (Postfix) with ESMTPS id 111CB1C2F8A for ; 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arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0F9B11570; Sat, 26 Sep 2026 16:26:35 -0700 (PDT) Received: from ryzen.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AA47E3F85F; Sat, 26 Sep 2026 16:26:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1790465198; bh=18BAa8o4E9lvNw8wwNFzP1FIpKXx6SRGQiiHFQNFT/M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vegZt+4Dru+hnxX89KGXOyf2wnZKm+shsFlnfiTbPpYispoyRFxWxoVRmpMO8y6IM Lmv7M4/ECvjdExyThNWiINNxwALXjKqf/lVKaQLIoK8FJCi3hGwA+MXxIoWQuYS7rF 5T38ZgwJpioR0xK/WfKKcOmGQ5czwoXDSA7KxNc4= From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Per Larsson Subject: [PATCH v2 2/2] arm64: dts: allwinner: a523: x96qpro+: enable Ethernet support Date: Sun, 27 Sep 2026 01:21:42 +0200 Message-ID: <20260926232142.5244-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.4 In-Reply-To: <20260926232142.5244-1-andre.przywara@arm.com> References: <20260926232142.5244-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MORS-Enabled: yes X-MORS-DOMAIN: patchwork.local X-MORS-HOSTING: hosting172546 X-MORS-USER: hosting172546 X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= The X96QPro+ TV Box features a Gigabit Ethernet capable port, which is driven by the secondary EMAC, and supported by a Maxio MAE0621A PHY. Add the required devicetree nodes to enable that port. The PHY is not clocked by an external crystal oscillator, but relies on a SoC-provided clock fanout pin for its 25 MHz reference input clock. The clock is referenced in the PHY DT node, which not all systems might enable before scanning the MDIO bus. To help with that problem, the PHY compatible string is using the PHY ID, which means the MDIO bus scanning can be skipped. Signed-off-by: Andre Przywara Tested-by: Per Larsson --- .../dts/allwinner/sun55i-h728-x96qpro+.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts index eb9fd0a65b41c..8015473ecb7ae 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts @@ -13,6 +13,7 @@ / { aliases { serial0 = &uart0; + ethernet0 = &gmac1; }; chosen { @@ -72,11 +73,38 @@ &ehci1 { status = "okay"; }; +&gmac1 { + clocks = <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins>; + phy-mode = "rgmii-id"; + phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_cldo3>; + + tx-internal-delay-ps = <200>; + rx-internal-delay-ps = <500>; + + status = "okay"; +}; + &gpu { mali-supply = <®_dcdc2>; status = "okay"; }; +&mdio1 { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-id7b74.4411"; + reg = <1>; + clocks = <&ccu CLK_EMAC1_25M>; + pinctrl-names = "default"; + pinctrl-0 = <&ephy1_25m_pin>; + reset-gpios = <&pio 9 16 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <150000>; + }; +}; + &mmc0 { vmmc-supply = <®_vcc3v3>; cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */